SPRUIN7C March   2020  – March 2024 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation From Texas Instruments
    5.     Support Resources
    6.     Trademarks
  3. 1 C2000™ Microcontrollers Software Support
    1. 1.1 Introduction
    2. 1.2 C2000Ware Structure
    3. 1.3 Documentation
    4. 1.4 Devices
    5. 1.5 Libraries
    6. 1.6 Code Composer Studio™ Integrated Development Environment (IDE)
    7. 1.7 SysConfig and PinMUX Tool
  4. 2 C28x Processor
    1. 2.1 Introduction
    2. 2.2 C28X Related Collateral
    3. 2.3 Features
    4. 2.4 Floating-Point Unit
    5. 2.5 Trigonometric Math Unit (TMU)
    6. 2.6 VCRC Unit
  5. 3 System Control and Interrupts
    1. 3.1  Introduction
      1. 3.1.1 SYSCTL Related Collateral
      2. 3.1.2 LOCK Protection on System Configuration Registers
      3. 3.1.3 EALLOW Protection
    2. 3.2  Power Management
    3. 3.3  Device Identification and Configuration Registers
    4. 3.4  Resets
      1. 3.4.1  Reset Sources
      2. 3.4.2  External Reset (XRS)
      3. 3.4.3  Simulate External Reset
      4. 3.4.4  Power-On Reset (POR)
      5. 3.4.5  Brown-Out-Reset (BOR)
      6. 3.4.6  Debugger Reset (SYSRS)
      7. 3.4.7  Simulate CPU Reset
      8. 3.4.8  Watchdog Reset (WDRS)
      9. 3.4.9  Hardware BIST Reset (HWBISTRS)
      10. 3.4.10 NMI Watchdog Reset (NMIWDRS)
      11. 3.4.11 DCSM Safe Code Copy Reset (SCCRESET)
    5. 3.5  Peripheral Interrupts
      1. 3.5.1 Interrupt Concepts
      2. 3.5.2 Interrupt Architecture
        1. 3.5.2.1 Peripheral Stage
        2. 3.5.2.2 PIE Stage
        3. 3.5.2.3 CPU Stage
      3. 3.5.3 Interrupt Entry Sequence
      4. 3.5.4 Configuring and Using Interrupts
        1. 3.5.4.1 Enabling Interrupts
        2. 3.5.4.2 Handling Interrupts
        3. 3.5.4.3 Disabling Interrupts
        4. 3.5.4.4 Nesting Interrupts
        5. 3.5.4.5 Vector Address Validity Check
      5. 3.5.5 PIE Channel Mapping
        1. 3.5.5.1 PIE Interrupt Priority
          1. 3.5.5.1.1 Channel Priority
          2. 3.5.5.1.2 Group Priority
      6. 3.5.6 Vector Tables
    6. 3.6  Exceptions and Non-Maskable Interrupts
      1. 3.6.1 Configuring and Using NMIs
      2. 3.6.2 Emulation Considerations
      3. 3.6.3 NMI Sources
        1. 3.6.3.1 Missing Clock Detection
        2. 3.6.3.2 RAM Uncorrectable ECC Error
        3. 3.6.3.3 Flash Uncorrectable ECC Error
        4. 3.6.3.4 CPU HWBIST Error
        5. 3.6.3.5 Software-Forced Error
      4. 3.6.4 CRC Fail
      5. 3.6.5 ERAD NMI
      6. 3.6.6 Illegal Instruction Trap (ITRAP)
      7. 3.6.7 Error Pin
    7. 3.7  Clocking
      1. 3.7.1  Clock Sources
        1. 3.7.1.1 Primary Internal Oscillator (INTOSC2)
        2. 3.7.1.2 Backup Internal Oscillator (INTOSC1)
        3. 3.7.1.3 External Oscillator (XTAL)
      2. 3.7.2  Derived Clocks
        1. 3.7.2.1 Oscillator Clock (OSCCLK)
        2. 3.7.2.2 System PLL Output Clock (PLLRAWCLK)
      3. 3.7.3  Device Clock Domains
        1. 3.7.3.1 System Clock (PLLSYSCLK)
        2. 3.7.3.2 CPU Clock (CPUCLK)
        3. 3.7.3.3 CPU Subsystem Clock (SYSCLK and PERx.SYSCLK)
        4. 3.7.3.4 Low-Speed Peripheral Clock (LSPCLK and PERx.LSPCLK)
        5. 3.7.3.5 CAN Bit Clock
        6. 3.7.3.6 CPU Timer2 Clock (TIMER2CLK)
      4. 3.7.4  XCLKOUT
      5. 3.7.5  Clock Connectivity
      6. 3.7.6  Clock Source and PLL Setup
      7. 3.7.7  Using an External Crystal or Resonator
        1. 3.7.7.1 X1/X2 Precondition Circuit
      8. 3.7.8  Using an External Oscillator
      9. 3.7.9  Choosing PLL Settings
      10. 3.7.10 System Clock Setup
      11. 3.7.11 SYS PLL Bypass
      12. 3.7.12 Clock (OSCCLK) Failure Detection
        1. 3.7.12.1 Missing Clock Detection
    8. 3.8  32-Bit CPU Timers 0/1/2
    9. 3.9  Watchdog Timer
      1. 3.9.1 Servicing the Watchdog Timer
      2. 3.9.2 Minimum Window Check
      3. 3.9.3 Watchdog Reset or Watchdog Interrupt Mode
      4. 3.9.4 Watchdog Operation in Low-Power Modes
      5. 3.9.5 Emulation Considerations
    10. 3.10 Low-Power Modes
      1. 3.10.1 Clock-Gating Low-Power Modes
      2. 3.10.2 IDLE
      3. 3.10.3 STANDBY
      4. 3.10.4 HALT
      5. 3.10.5 Flash Power-down Considerations
    11. 3.11 Memory Controller Module
      1. 3.11.1 Functional Description
        1. 3.11.1.1 Dedicated RAM (Mx RAM)
        2. 3.11.1.2 Local Shared RAM (LSx RAM)
        3. 3.11.1.3 Global Shared RAM (GSx RAM)
        4. 3.11.1.4 Access Arbitration
        5. 3.11.1.5 Access Protection
          1. 3.11.1.5.1 CPU Fetch Protection
          2. 3.11.1.5.2 CPU Write Protection
          3. 3.11.1.5.3 CPU Read Protection
          4. 3.11.1.5.4 HIC Write Protection
          5. 3.11.1.5.5 DMA Write Protection
        6. 3.11.1.6 Memory Error Detection, Correction and Error Handling
          1. 3.11.1.6.1 Error Detection and Correction
          2. 3.11.1.6.2 Error Handling
        7. 3.11.1.7 Application Test Hooks for Error Detection and Correction
        8. 3.11.1.8 RAM Initialization
    12. 3.12 JTAG
      1. 3.12.1 JTAG Noise and TAP_STATUS
    13. 3.13 Dual Code Security Module (DCSM)
      1. 3.13.1 Functional Description
        1. 3.13.1.1 CSM Passwords
        2. 3.13.1.2 Emulation Code Security Logic (ECSL)
        3. 3.13.1.3 CPU Secure Logic
        4. 3.13.1.4 Execute-Only Protection
        5. 3.13.1.5 Password Lock
        6. 3.13.1.6 JTAG Lock
        7. 3.13.1.7 Link Pointer and Zone Select
      2. 3.13.2 C Code Example to Get Zone Select Block Addr for Zone1 in BANK0
      3. 3.13.3 Flash and OTP Erase/Program
      4. 3.13.4 Safe Copy Code
      5. 3.13.5 SafeCRC
      6. 3.13.6 CSM Impact on Other On-Chip Resources
      7. 3.13.7 Incorporating Code Security in User Applications
        1. 3.13.7.1 Environments That Require Security Unlocking
        2. 3.13.7.2 CSM Password Match Flow
        3. 3.13.7.3 C Code Example to Unsecure C28x Zone1
        4.       150
        5. 3.13.7.4 C Code Example to Resecure C28x Zone1
        6.       152
        7. 3.13.7.5 Environments That Require ECSL Unlocking
        8. 3.13.7.6 ECSL Password Match Flow
        9. 3.13.7.7 ECSL Disable Considerations for Any Zone
          1. 3.13.7.7.1 C Code Example to Disable ECSL for C28x-Zone1
        10.       157
        11. 3.13.7.8 Device Unique ID
    14. 3.14 System Control Register Configuration Restrictions
    15. 3.15 Software
      1. 3.15.1 SYSCTL Examples
        1. 3.15.1.1 Missing clock detection (MCD)
        2. 3.15.1.2 XCLKOUT (External Clock Output) Configuration
      2. 3.15.2 DCSM Examples
        1. 3.15.2.1 Empty DCSM Tool Example
      3. 3.15.3 MEMCFG Examples
        1. 3.15.3.1 Correctable & Uncorrectable Memory Error Handling
      4. 3.15.4 NMI Examples
      5. 3.15.5 TIMER Examples
        1. 3.15.5.1 CPU Timers
        2. 3.15.5.2 CPU Timers
      6. 3.15.6 WATCHDOG Examples
        1. 3.15.6.1 Watchdog
    16. 3.16 System Control Registers
      1. 3.16.1  SYSCTRL Base Address Table
      2. 3.16.2  CPUTIMER_REGS Registers
      3. 3.16.3  PIE_CTRL_REGS Registers
      4. 3.16.4  WD_REGS Registers
      5. 3.16.5  NMI_INTRUPT_REGS Registers
      6. 3.16.6  XINT_REGS Registers
      7. 3.16.7  SYNC_SOC_REGS Registers
      8. 3.16.8  DMA_CLA_SRC_SEL_REGS Registers
      9. 3.16.9  DEV_CFG_REGS Registers
      10. 3.16.10 CLK_CFG_REGS Registers
      11. 3.16.11 CPU_SYS_REGS Registers
      12. 3.16.12 PERIPH_AC_REGS Registers
      13. 3.16.13 DCSM_BANK0_Z1_REGS Registers
      14. 3.16.14 DCSM_BANK0_Z2_REGS Registers
      15. 3.16.15 DCSM_COMMON_REGS Registers
      16. 3.16.16 MEM_CFG_REGS Registers
      17. 3.16.17 ACCESS_PROTECTION_REGS Registers
      18. 3.16.18 MEMORY_ERROR_REGS Registers
      19. 3.16.19 TEST_ERROR_REGS Registers
      20. 3.16.20 UID_REGS Registers
      21. 3.16.21 DCSM_BANK0_Z1_OTP Registers
      22. 3.16.22 DCSM_BANK0_Z2_OTP Registers
      23. 3.16.23 Register to Driverlib Function Mapping
        1. 3.16.23.1 ASYSCTL Registers to Driverlib Functions
        2. 3.16.23.2 CPUTIMER Registers to Driverlib Functions
        3. 3.16.23.3 DCSM Registers to Driverlib Functions
        4. 3.16.23.4 MEMCFG Registers to Driverlib Functions
        5. 3.16.23.5 NMI Registers to Driverlib Functions
        6. 3.16.23.6 PIE Registers to Driverlib Functions
        7. 3.16.23.7 SYSCTL Registers to Driverlib Functions
        8. 3.16.23.8 XINT Registers to Driverlib Functions
  6. 4 ROM Code and Peripheral Booting
    1. 4.1 Introduction
      1. 4.1.1 ROM Related Collateral
    2. 4.2 Device Boot Sequence
    3. 4.3 Device Boot Modes
    4. 4.4 Device Boot Configurations
      1. 4.4.1 Configuring Boot Mode Pins
      2. 4.4.2 Configuring Boot Mode Table Options
      3. 4.4.3 Boot Mode Example Use Cases
        1. 4.4.3.1 Zero Boot Mode Select Pins
        2. 4.4.3.2 One Boot Mode Select Pin
        3. 4.4.3.3 Three Boot Mode Select Pins
    5. 4.5 Device Boot Flow Diagrams
      1. 4.5.1 Boot Flow
    6. 4.6 Device Reset and Exception Handling
      1. 4.6.1 Reset Causes and Handling
      2. 4.6.2 Exceptions and Interrupts Handling
    7. 4.7 Boot ROM Description
      1. 4.7.1  Boot ROM Configuration Registers
        1. 4.7.1.1 GPREG2 Usage and MPOST Configuration
      2. 4.7.2  Entry Points
      3. 4.7.3  Wait Points
      4. 4.7.4  Memory Maps
        1. 4.7.4.1 Boot ROM Memory Maps
        2. 4.7.4.2 Reserved RAM Memory Maps
      5. 4.7.5  ROM Tables
      6. 4.7.6  Boot Modes and Loaders
        1. 4.7.6.1 Boot Modes
          1. 4.7.6.1.1 Wait Boot
          2. 4.7.6.1.2 Flash Boot
          3. 4.7.6.1.3 RAM Boot
        2. 4.7.6.2 Bootloaders
          1. 4.7.6.2.1 SCI Boot Mode
          2. 4.7.6.2.2 SPI Boot Mode
          3. 4.7.6.2.3 I2C Boot Mode
          4. 4.7.6.2.4 Parallel Boot Mode
          5. 4.7.6.2.5 CAN Boot Mode
      7. 4.7.7  GPIO Assignments
      8. 4.7.8  Secure ROM Function APIs
      9. 4.7.9  Clock Initializations
      10. 4.7.10 Boot Status Information
        1. 4.7.10.1 Booting Status
        2. 4.7.10.2 Boot Mode and MPOST (Memory Power On Self-Test) Status
      11. 4.7.11 ROM Version
    8. 4.8 Application Notes for Using the Bootloaders
      1. 4.8.1 Boot Data Stream Structure
        1. 4.8.1.1 Bootloader Data Stream Structure
          1. 4.8.1.1.1 Data Stream Structure 8-bit
      2. 4.8.2 The C2000 Hex Utility
        1. 4.8.2.1 HEX2000.exe Command Syntax
    9. 4.9 Software
      1. 4.9.1 BOOT Examples
  7. 5 Flash Module
    1. 5.1  Introduction to Flash and OTP Memory
      1. 5.1.1 FLASH Related Collateral
      2. 5.1.2 Features
      3. 5.1.3 Flash Tools
      4. 5.1.4 Default Flash Configuration
    2. 5.2  Flash Bank, OTP, and Pump
    3. 5.3  Flash Module Controller (FMC)
    4. 5.4  Flash and OTP Memory Power-Down Modes and Wakeup
    5. 5.5  Active Grace Period
    6. 5.6  Flash and OTP Memory Performance
    7. 5.7  Flash Read Interface
      1. 5.7.1 C28x-FMC Flash Read Interface
        1. 5.7.1.1 Standard Read Mode
        2. 5.7.1.2 Prefetch Mode
          1. 5.7.1.2.1 Data Cache
    8. 5.8  Flash Erase and Program
      1. 5.8.1 Erase
      2. 5.8.2 Program
      3. 5.8.3 Verify
    9. 5.9  Error Correction Code (ECC) Protection
      1. 5.9.1 Single-Bit Data Error
      2. 5.9.2 Uncorrectable Error
      3. 5.9.3 SECDED Logic Correctness Check
    10. 5.10 Reserved Locations Within Flash and OTP Memory
    11. 5.11 Migrating an Application from RAM to Flash
    12. 5.12 Procedure to Change the Flash Control Registers
    13. 5.13 Software
      1. 5.13.1 FLASH Examples
        1. 5.13.1.1 Live Firmware Update Example
        2. 5.13.1.2 Flash Programming with AutoECC, DataAndECC, DataOnly and EccOnly
        3. 5.13.1.3 Flash ECC Test Mode
        4. 5.13.1.4 Boot Source Code
        5. 5.13.1.5 Erase Source Code
        6. 5.13.1.6 Live DFU Command Functionality
        7. 5.13.1.7 Verify Source Code
        8. 5.13.1.8 SCI Boot Mode Routines
        9. 5.13.1.9 Flash Programming Solution using SCI
    14. 5.14 Flash Registers
      1. 5.14.1 FLASH Base Address Table
      2. 5.14.2 FLASH_CTRL_REGS Registers
      3. 5.14.3 FLASH_ECC_REGS Registers
      4. 5.14.4 FLASH Registers to Driverlib Functions
  8. 6 Dual-Clock Comparator (DCC)
    1. 6.1 Introduction
      1. 6.1.1 Features
      2. 6.1.2 Block Diagram
    2. 6.2 Module Operation
      1. 6.2.1 Configuring DCC Counters
      2. 6.2.2 Single-Shot Measurement Mode
      3. 6.2.3 Continuous Monitoring Mode
      4. 6.2.4 Error Conditions
    3. 6.3 Interrupts
    4. 6.4 Software
      1. 6.4.1 DCC Examples
        1. 6.4.1.1 DCC Single shot Clock verification
        2. 6.4.1.2 DCC Single shot Clock measurement
        3. 6.4.1.3 DCC Continuous clock monitoring
        4. 6.4.1.4 DCC Continuous clock monitoring
        5. 6.4.1.5 DCC Detection of clock failure
    5. 6.5 DCC Registers
      1. 6.5.1 DCC Base Address Table
      2. 6.5.2 DCC_REGS Registers
      3. 6.5.3 DCC Registers to Driverlib Functions
  9. 7 Background CRC-32 (BGCRC)
    1. 7.1 Introduction
      1. 7.1.1 BGCRC Related Collateral
      2. 7.1.2 Features
      3. 7.1.3 Block Diagram
      4. 7.1.4 Memory Wait States and Memory Map
    2. 7.2 Functional Description
      1. 7.2.1 Data Read Unit
      2. 7.2.2 CRC-32 Compute Unit
      3. 7.2.3 CRC Notification Unit
        1. 7.2.3.1 CPU Interrupt and NMI
      4. 7.2.4 Operating Modes
        1. 7.2.4.1 CRC Mode
        2. 7.2.4.2 Scrub Mode
      5. 7.2.5 BGCRC Watchdog
      6. 7.2.6 Hardware and Software Faults Protection
    3. 7.3 Application of the BGCRC
      1. 7.3.1 Software Configuration
      2. 7.3.2 Decision on Error Response Severity
      3. 7.3.3 Execution of Time Critical Code from Wait-Stated Memories
      4. 7.3.4 BGCRC Execution
      5. 7.3.5 Debug/Error Response for BGCRC Errors
      6. 7.3.6 BGCRC Golden CRC-32 Value Computation
    4. 7.4 Software
      1. 7.4.1 BGCRC Examples
        1. 7.4.1.1 BGCRC CPU Interrupt Example
        2. 7.4.1.2 BGCRC Example with Watchdog and Lock
    5. 7.5 BGCRC Registers
      1. 7.5.1 BGCRC Base Address Table
      2. 7.5.2 BGCRC_REGS Registers
      3. 7.5.3 BGCRC Registers to Driverlib Functions
  10. 8 General-Purpose Input/Output (GPIO)
    1. 8.1 Introduction
      1. 8.1.1 GPIO Related Collateral
    2. 8.2 Configuration Overview
    3. 8.3 Digital Inputs on ADC Pins (AIOs)
    4. 8.4 Digital General-Purpose I/O Control
    5. 8.5 Input Qualification
      1. 8.5.1 No Synchronization (Asynchronous Input)
      2. 8.5.2 Synchronization to SYSCLKOUT Only
      3. 8.5.3 Qualification Using a Sampling Window
    6. 8.6 GPIO and Peripheral Muxing
      1. 8.6.1 GPIO Muxing
      2. 8.6.2 Peripheral Muxing
    7. 8.7 Internal Pullup Configuration Requirements
    8. 8.8 Software
      1. 8.8.1 GPIO Examples
        1. 8.8.1.1 Device GPIO Setup
        2. 8.8.1.2 Device GPIO Toggle
        3. 8.8.1.3 Device GPIO Interrupt
        4. 8.8.1.4 External Interrupt (XINT)
      2. 8.8.2 LED Examples
        1. 8.8.2.1 LED Blinky Example with DCSM
    9. 8.9 GPIO Registers
      1. 8.9.1 GPIO Base Address Table
      2. 8.9.2 GPIO_CTRL_REGS Registers
      3. 8.9.3 GPIO_DATA_REGS Registers
      4. 8.9.4 GPIO_DATA_READ_REGS Registers
      5. 8.9.5 GPIO Registers to Driverlib Functions
  11. 9 Crossbar (X-BAR)
    1. 9.1 Input X-BAR and CLB Input X-BAR
      1. 9.1.1 CLB Input X-BAR
    2. 9.2 ePWM, CLB, and GPIO Output X-BAR
      1. 9.2.1 ePWM X-BAR
        1. 9.2.1.1 ePWM X-BAR Architecture
      2. 9.2.2 CLB X-BAR
        1. 9.2.2.1 CLB X-BAR Architecture
      3. 9.2.3 GPIO Output X-BAR
        1. 9.2.3.1 GPIO Output X-BAR Architecture
      4. 9.2.4 CLB Output X-BAR
        1. 9.2.4.1 CLB Output X-BAR Architecture
      5. 9.2.5 X-BAR Flags
    3. 9.3 XBAR Registers
      1. 9.3.1 XBAR Base Address Table
      2. 9.3.2 INPUT_XBAR_REGS Registers
      3. 9.3.3 XBAR_REGS Registers
      4. 9.3.4 EPWM_XBAR_REGS Registers
      5. 9.3.5 CLB_XBAR_REGS Registers
      6. 9.3.6 OUTPUT_XBAR_REGS Registers
      7. 9.3.7 Register to Driverlib Function Mapping
        1. 9.3.7.1 INPUTXBAR Registers to Driverlib Functions
        2. 9.3.7.2 XBAR Registers to Driverlib Functions
        3. 9.3.7.3 EPWMXBAR Registers to Driverlib Functions
        4. 9.3.7.4 CLBXBAR Registers to Driverlib Functions
        5. 9.3.7.5 OUTPUTXBAR Registers to Driverlib Functions
        6. 9.3.7.6 TRIGXBAR Registers to Driverlib Functions
  12. 10Direct Memory Access (DMA)
    1. 10.1 Introduction
      1. 10.1.1 Features
      2. 10.1.2 Block Diagram
    2. 10.2 Architecture
      1. 10.2.1 Peripheral Interrupt Event Trigger Sources
      2. 10.2.2 DMA Bus
    3. 10.3 Address Pointer and Transfer Control
    4. 10.4 Pipeline Timing and Throughput
    5. 10.5 Channel Priority
      1. 10.5.1 Round-Robin Mode
      2. 10.5.2 Channel 1 High-Priority Mode
    6. 10.6 Overrun Detection Feature
    7. 10.7 Software
      1. 10.7.1 DMA Examples
        1. 10.7.1.1 DMA GSRAM Transfer (dma_ex1_gsram_transfer)
        2. 10.7.1.2 DMA GSRAM Transfer (dma_ex2_gsram_transfer)
    8. 10.8 DMA Registers
      1. 10.8.1 DMA Base Address Table
      2. 10.8.2 DMA_REGS Registers
      3. 10.8.3 DMA_CH_REGS Registers
      4. 10.8.4 DMA Registers to Driverlib Functions
  13. 11Embedded Real-time Analysis and Diagnostic (ERAD)
    1. 11.1 Introduction
      1. 11.1.1 ERAD Related Collateral
    2. 11.2 Enhanced Bus Comparator Unit
      1. 11.2.1 Enhanced Bus Comparator Unit Operations
      2. 11.2.2 Event Masking and Exporting
    3. 11.3 System Event Counter Unit
      1. 11.3.1 System Event Counter Modes
        1. 11.3.1.1 Counting Active Levels Versus Edges
        2. 11.3.1.2 Max Mode
        3. 11.3.1.3 Cumulative Mode
        4. 11.3.1.4 Input Signal Selection
      2. 11.3.2 Reset on Event
      3. 11.3.3 Operation Conditions
    4. 11.4 ERAD Ownership, Initialization and Reset
    5. 11.5 ERAD Programming Sequence
      1. 11.5.1 Hardware Breakpoint and Hardware Watch Point Programming Sequence
      2. 11.5.2 Timer and Counter Programming Sequence
    6. 11.6 Cyclic Redundancy Check Unit
      1. 11.6.1 CRC Unit Qualifier
      2. 11.6.2 CRC Unit Programming Sequence
    7. 11.7 Software
      1. 11.7.1 ERAD Examples
        1. 11.7.1.1  ERAD Profiling Interrupts
        2. 11.7.1.2  ERAD Profile Function
        3. 11.7.1.3  ERAD Profile Function
        4. 11.7.1.4  ERAD HWBP Monitor Program Counter
        5. 11.7.1.5  ERAD HWBP Monitor Program Counter
        6. 11.7.1.6  ERAD Profile Function
        7. 11.7.1.7  ERAD HWBP Stack Overflow Detection
        8. 11.7.1.8  ERAD HWBP Stack Overflow Detection
        9. 11.7.1.9  ERAD Stack Overflow
        10. 11.7.1.10 ERAD Profiling Interrupts
        11. 11.7.1.11 ERAD Profiling Interrupts
        12. 11.7.1.12 ERAD MEMORY ACCESS RESTRICT
        13. 11.7.1.13 ERAD INTERRUPT ORDER
        14. 11.7.1.14 ERAD AND CLB
        15. 11.7.1.15 ERAD PWM PROTECTION
    8. 11.8 ERAD Registers
      1. 11.8.1 ERAD Base Address Table
      2. 11.8.2 ERAD_GLOBAL_REGS Registers
      3. 11.8.3 ERAD_HWBP_REGS Registers
      4. 11.8.4 ERAD_COUNTER_REGS Registers
      5. 11.8.5 ERAD_CRC_GLOBAL_REGS Registers
      6. 11.8.6 ERAD_CRC_REGS Registers
      7. 11.8.7 ERAD Registers to Driverlib Functions
  14. 12Configurable Logic Block (CLB)
    1. 12.1 Introduction
      1. 12.1.1 CLB Related Collateral
    2. 12.2 Description
      1. 12.2.1 CLB Clock
    3. 12.3 CLB Input/Output Connection
      1. 12.3.1 Overview
      2. 12.3.2 CLB Input Selection
      3. 12.3.3 CLB Output Selection
      4. 12.3.4 CLB Output Signal Multiplexer
    4. 12.4 CLB Tile
      1. 12.4.1 Static Switch Block
      2. 12.4.2 Counter Block
        1. 12.4.2.1 Counter Description
        2. 12.4.2.2 Counter Operation
        3. 12.4.2.3 Serializer Mode
        4. 12.4.2.4 Linear Feedback Shift Register (LFSR) Mode
      3. 12.4.3 FSM Block
      4. 12.4.4 LUT4 Block
      5. 12.4.5 Output LUT Block
      6. 12.4.6 Asynchronous Output Conditioning (AOC) Block
      7. 12.4.7 High Level Controller (HLC)
        1. 12.4.7.1 High Level Controller Events
        2. 12.4.7.2 High Level Controller Instructions
        3. 12.4.7.3 <Src> and <Dest>
        4. 12.4.7.4 Operation of the PUSH and PULL Instructions (Overflow and Underflow Detection)
    5. 12.5 CPU Interface
      1. 12.5.1 Register Description
      2. 12.5.2 Non-Memory Mapped Registers
    6. 12.6 DMA Access
    7. 12.7 CLB Data Export Through SPI RX Buffer
    8. 12.8 Software
      1. 12.8.1 CLB Examples
        1. 12.8.1.1  CLB Empty Project
        2. 12.8.1.2  CLB Combinational Logic
        3. 12.8.1.3  CLB GPIO Input Filter
        4. 12.8.1.4  CLB Auxilary PWM
        5. 12.8.1.5  CLB PWM Protection
        6. 12.8.1.6  CLB Signal Generator
        7. 12.8.1.7  CLB State Machine
        8. 12.8.1.8  CLB External Signal AND Gate
        9. 12.8.1.9  CLB Timer
        10. 12.8.1.10 CLB Timer Two States
        11. 12.8.1.11 CLB Interrupt Tag
        12. 12.8.1.12 CLB Output Intersect
        13. 12.8.1.13 CLB PUSH PULL
        14. 12.8.1.14 CLB Multi Tile
        15. 12.8.1.15 CLB Glue Logic
        16. 12.8.1.16 CLB AOC Control
        17. 12.8.1.17 CLB AOC Release Control
        18. 12.8.1.18 CLB XBARs
        19. 12.8.1.19 CLB AOC Control
        20. 12.8.1.20 CLB Serializer
        21. 12.8.1.21 CLB LFSR
        22. 12.8.1.22 CLB Lock Output Mask
        23. 12.8.1.23 CLB INPUT Pipeline Mode
        24. 12.8.1.24 CLB Clocking and PIPELINE Mode
        25. 12.8.1.25 CLB SPI Data Export
        26. 12.8.1.26 CLB SPI Data Export DMA
        27. 12.8.1.27 CLB Trip Zone Timestamp
        28. 12.8.1.28 CLB CRC
        29. 12.8.1.29 CLB TDM Serial Port
        30. 12.8.1.30 CLB LED Driver
    9. 12.9 CLB Registers
      1. 12.9.1 CLB Base Address Table
      2. 12.9.2 CLB_LOGIC_CONFIG_REGS Registers
      3. 12.9.3 CLB_LOGIC_CONTROL_REGS Registers
      4. 12.9.4 CLB_DATA_EXCHANGE_REGS Registers
      5. 12.9.5 CLB Registers to Driverlib Functions
  15. 13Host Interface Controller (HIC)
    1. 13.1 Introduction
      1. 13.1.1 HIC Related Collateral
      2. 13.1.2 Features
      3. 13.1.3 Block Diagram
    2. 13.2 Functional Description
      1. 13.2.1 Memory Map
      2. 13.2.2 Connections
        1. 13.2.2.1 Functions of the Connections
      3. 13.2.3 Interrupts and Triggers
    3. 13.3 Operation
      1. 13.3.1 Mailbox Access Mode Overview
        1. 13.3.1.1 Mailbox Access Mode Operation
        2. 13.3.1.2 Configuring HIC Registers With External Host
        3. 13.3.1.3 Mailbox Access Mode Read/Write
      2. 13.3.2 Direct Access Mode Overview
        1. 13.3.2.1 Direct Access Mode Operation
        2. 13.3.2.2 Direct Access Mode Read/Write
      3. 13.3.3 Controlling Reads and Writes
        1. 13.3.3.1 Single-Pin Read/Write Mode (nOE/RnW Pin)
        2. 13.3.3.2 Dual-Pin Read/Write Mode (nOE and nWE Pins)
      4. 13.3.4 Data Lines, Data Width, Data Packing and Unpacking
      5. 13.3.5 Address Translation
      6. 13.3.6 Access Errors
      7. 13.3.7 Security
      8. 13.3.8 HIC Usage
    4. 13.4 Usage Scenarious for Reduced Number of Pins
    5. 13.5 Software
      1. 13.5.1 HIC Examples
        1. 13.5.1.1 HIC 16-bit Memory Access Example
        2. 13.5.1.2 HIC 8-bit Memory Access Example
        3. 13.5.1.3 HIC 16-bit Memory Access FSI Example
    6. 13.6 HIC Registers
      1. 13.6.1 HIC Base Address Table
      2. 13.6.2 HIC_CFG_REGS Registers
      3. 13.6.3 HIC Registers to Driverlib Functions
  16. 14Analog Subsystem
    1. 14.1 Introduction
      1. 14.1.1 Features
      2. 14.1.2 Block Diagram
    2. 14.2 Optimizing Power-Up Time
    3. 14.3 Digital Inputs on ADC Pins (AIOs)
    4. 14.4 Digital Inputs and Outputs on ADC Pins (AGPIOs)
    5. 14.5 Analog Pins and Internal Connections
    6. 14.6 Analog Subsystem Registers
      1. 14.6.1 ASBSYS Base Address Table
      2. 14.6.2 ANALOG_SUBSYS_REGS Registers
  17. 15Analog-to-Digital Converter (ADC)
    1. 15.1  Introduction
      1. 15.1.1 ADC Related Collateral
      2. 15.1.2 Features
      3. 15.1.3 Block Diagram
    2. 15.2  ADC Configurability
      1. 15.2.1 Clock Configuration
      2. 15.2.2 Resolution
      3. 15.2.3 Voltage Reference
        1. 15.2.3.1 External Reference Mode
        2. 15.2.3.2 Internal Reference Mode
        3. 15.2.3.3 Selecting Reference Mode
      4. 15.2.4 Signal Mode
      5. 15.2.5 Expected Conversion Results
      6. 15.2.6 Interpreting Conversion Results
    3. 15.3  SOC Principle of Operation
      1. 15.3.1 SOC Configuration
      2. 15.3.2 Trigger Operation
      3. 15.3.3 ADC Acquisition (Sample and Hold) Window
      4. 15.3.4 ADC Input Models
      5. 15.3.5 Channel Selection
    4. 15.4  SOC Configuration Examples
      1. 15.4.1 Single Conversion from ePWM Trigger
      2. 15.4.2 Oversampled Conversion from ePWM Trigger
      3. 15.4.3 Multiple Conversions from CPU Timer Trigger
      4. 15.4.4 Software Triggering of SOCs
    5. 15.5  ADC Conversion Priority
    6. 15.6  Burst Mode
      1. 15.6.1 Burst Mode Example
      2. 15.6.2 Burst Mode Priority Example
    7. 15.7  EOC and Interrupt Operation
      1. 15.7.1 Interrupt Overflow
      2. 15.7.2 Continue to Interrupt Mode
      3. 15.7.3 Early Interrupt Configuration Mode
    8. 15.8  Post-Processing Blocks
      1. 15.8.1 PPB Offset Correction
      2. 15.8.2 PPB Error Calculation
      3. 15.8.3 PPB Limit Detection and Zero-Crossing Detection
      4. 15.8.4 PPB Sample Delay Capture
    9. 15.9  Opens/Shorts Detection Circuit (OSDETECT)
      1. 15.9.1 Implementation
      2. 15.9.2 Detecting an Open Input Pin
      3. 15.9.3 Detecting a Shorted Input Pin
    10. 15.10 Power-Up Sequence
    11. 15.11 ADC Calibration
      1. 15.11.1 ADC Zero Offset Calibration
    12. 15.12 ADC Timings
      1. 15.12.1 ADC Timing Diagrams
    13. 15.13 Additional Information
      1. 15.13.1 Ensuring Synchronous Operation
        1. 15.13.1.1 Basic Synchronous Operation
        2. 15.13.1.2 Synchronous Operation with Multiple Trigger Sources
        3. 15.13.1.3 Synchronous Operation with Uneven SOC Numbers
        4. 15.13.1.4 Non-overlapping Conversions
      2. 15.13.2 Choosing an Acquisition Window Duration
      3. 15.13.3 Achieving Simultaneous Sampling
      4. 15.13.4 Result Register Mapping
      5. 15.13.5 Internal Temperature Sensor
      6. 15.13.6 Designing an External Reference Circuit
      7. 15.13.7 ADC-DAC Loopback Testing
      8. 15.13.8 Internal Test Mode
      9. 15.13.9 ADC Gain and Offset Calibration
    14. 15.14 Software
      1. 15.14.1 ADC Examples
        1. 15.14.1.1  ADC Software Triggering
        2. 15.14.1.2  ADC ePWM Triggering
        3. 15.14.1.3  ADC Temperature Sensor Conversion
        4. 15.14.1.4  ADC Synchronous SOC Software Force (adc_soc_software_sync)
        5. 15.14.1.5  ADC Continuous Triggering (adc_soc_continuous)
        6. 15.14.1.6  ADC Continuous Conversions Read by DMA (adc_soc_continuous_dma)
        7. 15.14.1.7  ADC PPB Offset (adc_ppb_offset)
        8. 15.14.1.8  ADC PPB Limits (adc_ppb_limits)
        9. 15.14.1.9  ADC PPB Delay Capture (adc_ppb_delay)
        10. 15.14.1.10 ADC ePWM Triggering Multiple SOC
        11. 15.14.1.11 ADC Burst Mode
        12. 15.14.1.12 ADC Burst Mode Oversampling
        13. 15.14.1.13 ADC SOC Oversampling
        14. 15.14.1.14 ADC PPB PWM trip (adc_ppb_pwm_trip)
        15. 15.14.1.15 ADC Open Shorts Detection (adc_open_shorts_detection)
    15. 15.15 ADC Registers
      1. 15.15.1 ADC Base Address Table
      2. 15.15.2 ADC_RESULT_REGS Registers
      3. 15.15.3 ADC_REGS Registers
      4. 15.15.4 ADC Registers to Driverlib Functions
  18. 16Comparator Subsystem (CMPSS)
    1. 16.1 Introduction
      1. 16.1.1 CMPSS Related Collateral
      2. 16.1.2 Features
      3. 16.1.3 Block Diagram
    2. 16.2 Comparator
    3. 16.3 Reference DAC
    4. 16.4 Ramp Generator
      1. 16.4.1 Ramp Generator Overview
      2. 16.4.2 Ramp Generator Behavior
      3. 16.4.3 Ramp Generator Behavior at Corner Cases
    5. 16.5 Digital Filter
      1. 16.5.1 Filter Initialization Sequence
    6. 16.6 Using the CMPSS
      1. 16.6.1 LATCHCLR, EPWMSYNCPER, and EPWMBLANK Signals
      2. 16.6.2 Synchronizer, Digital Filter, and Latch Delays
      3. 16.6.3 Calibrating the CMPSS
      4. 16.6.4 Enabling and Disabling the CMPSS Clock
    7. 16.7 Software
      1. 16.7.1 CMPSS Examples
        1. 16.7.1.1 CMPSS Asynchronous Trip
        2. 16.7.1.2 CMPSS Digital Filter Configuration
    8. 16.8 CMPSS Registers
      1. 16.8.1 CMPSS Base Address Table
      2. 16.8.2 CMPSS_REGS Registers
      3. 16.8.3 CMPSS Registers to Driverlib Functions
  19. 17Enhanced Pulse Width Modulator (ePWM)
    1. 17.1  Introduction
      1. 17.1.1 EPWM Related Collateral
      2. 17.1.2 Submodule Overview
    2. 17.2  Configuring Device Pins
    3. 17.3  ePWM Modules Overview
    4. 17.4  Time-Base (TB) Submodule
      1. 17.4.1 Purpose of the Time-Base Submodule
      2. 17.4.2 Controlling and Monitoring the Time-Base Submodule
      3. 17.4.3 Calculating PWM Period and Frequency
        1. 17.4.3.1 Time-Base Period Shadow Register
        2. 17.4.3.2 Time-Base Clock Synchronization
        3. 17.4.3.3 Time-Base Counter Synchronization
        4. 17.4.3.4 ePWM SYNC Selection
      4. 17.4.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules
      5. 17.4.5 Simultaneous Writes to TBPRD and CMPx Registers Between ePWM Modules
      6. 17.4.6 Time-Base Counter Modes and Timing Waveforms
      7. 17.4.7 Global Load
        1. 17.4.7.1 Global Load Pulse Pre-Scalar
        2. 17.4.7.2 One-Shot Load Mode
        3. 17.4.7.3 One-Shot Sync Mode
    5. 17.5  Counter-Compare (CC) Submodule
      1. 17.5.1 Purpose of the Counter-Compare Submodule
      2. 17.5.2 Controlling and Monitoring the Counter-Compare Submodule
      3. 17.5.3 Operational Highlights for the Counter-Compare Submodule
      4. 17.5.4 Count Mode Timing Waveforms
    6. 17.6  Action-Qualifier (AQ) Submodule
      1. 17.6.1 Purpose of the Action-Qualifier Submodule
      2. 17.6.2 Action-Qualifier Submodule Control and Status Register Definitions
      3. 17.6.3 Action-Qualifier Event Priority
      4. 17.6.4 AQCTLA and AQCTLB Shadow Mode Operations
      5. 17.6.5 Configuration Requirements for Common Waveforms
    7. 17.7  Dead-Band Generator (DB) Submodule
      1. 17.7.1 Purpose of the Dead-Band Submodule
      2. 17.7.2 Dead-band Submodule Additional Operating Modes
      3. 17.7.3 Operational Highlights for the Dead-Band Submodule
    8. 17.8  PWM Chopper (PC) Submodule
      1. 17.8.1 Purpose of the PWM Chopper Submodule
      2. 17.8.2 Operational Highlights for the PWM Chopper Submodule
      3. 17.8.3 Waveforms
        1. 17.8.3.1 One-Shot Pulse
        2. 17.8.3.2 Duty Cycle Control
    9. 17.9  Trip-Zone (TZ) Submodule
      1. 17.9.1 Purpose of the Trip-Zone Submodule
      2. 17.9.2 Operational Highlights for the Trip-Zone Submodule
        1. 17.9.2.1 Trip-Zone Configurations
      3. 17.9.3 Generating Trip Event Interrupts
    10. 17.10 Event-Trigger (ET) Submodule
      1. 17.10.1 Operational Overview of the ePWM Event-Trigger Submodule
    11. 17.11 Digital Compare (DC) Submodule
      1. 17.11.1 Purpose of the Digital Compare Submodule
      2. 17.11.2 Enhanced Trip Action Using CMPSS
      3. 17.11.3 Using CMPSS to Trip the ePWM on a Cycle-by-Cycle Basis
      4. 17.11.4 Operation Highlights of the Digital Compare Submodule
        1. 17.11.4.1 Digital Compare Events
        2. 17.11.4.2 Event Filtering
        3. 17.11.4.3 Valley Switching
    12. 17.12 ePWM Crossbar (X-BAR)
    13. 17.13 Applications to Power Topologies
      1. 17.13.1  Overview of Multiple Modules
      2. 17.13.2  Key Configuration Capabilities
      3. 17.13.3  Controlling Multiple Buck Converters With Independent Frequencies
      4. 17.13.4  Controlling Multiple Buck Converters With Same Frequencies
      5. 17.13.5  Controlling Multiple Half H-Bridge (HHB) Converters
      6. 17.13.6  Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
      7. 17.13.7  Practical Applications Using Phase Control Between PWM Modules
      8. 17.13.8  Controlling a 3-Phase Interleaved DC/DC Converter
      9. 17.13.9  Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter
      10. 17.13.10 Controlling a Peak Current Mode Controlled Buck Module
      11. 17.13.11 Controlling H-Bridge LLC Resonant Converter
    14. 17.14 Register Lock Protection
    15. 17.15 High-Resolution Pulse Width Modulator (HRPWM)
      1. 17.15.1 Operational Description of HRPWM
        1. 17.15.1.1 Controlling the HRPWM Capabilities
        2. 17.15.1.2 HRPWM Source Clock
        3. 17.15.1.3 Configuring the HRPWM
        4. 17.15.1.4 Configuring High-Resolution in Deadband Rising-Edge and Falling-Edge Delay
        5. 17.15.1.5 Principle of Operation
          1. 17.15.1.5.1 Edge Positioning
          2. 17.15.1.5.2 Scaling Considerations
          3. 17.15.1.5.3 Duty Cycle Range Limitation
          4. 17.15.1.5.4 High-Resolution Period
            1. 17.15.1.5.4.1 High-Resolution Period Configuration
        6. 17.15.1.6 Deadband High-Resolution Operation
        7. 17.15.1.7 Scale Factor Optimizing Software (SFO)
        8. 17.15.1.8 HRPWM Examples Using Optimized Assembly Code
          1. 17.15.1.8.1 #Defines for HRPWM Header Files
          2. 17.15.1.8.2 Implementing a Simple Buck Converter
            1. 17.15.1.8.2.1 HRPWM Buck Converter Initialization Code
            2. 17.15.1.8.2.2 HRPWM Buck Converter Run-Time Code
          3. 17.15.1.8.3 Implementing a DAC Function Using an R+C Reconstruction Filter
            1. 17.15.1.8.3.1 PWM DAC Function Initialization Code
            2. 17.15.1.8.3.2 PWM DAC Function Run-Time Code
      2. 17.15.2 SFO Library Software - SFO_TI_Build_V8.lib
        1. 17.15.2.1 Scale Factor Optimizer Function - int SFO()
        2. 17.15.2.2 Software Usage
          1. 17.15.2.2.1 A Sample of How to Add "Include" Files
          2.        799
          3. 17.15.2.2.2 Declaring an Element
          4.        801
          5. 17.15.2.2.3 Initializing With a Scale Factor Value
          6.        803
          7. 17.15.2.2.4 SFO Function Calls
    16. 17.16 Software
      1. 17.16.1 EPWM Examples
        1. 17.16.1.1  ePWM Trip Zone
        2. 17.16.1.2  ePWM Up Down Count Action Qualifier
        3. 17.16.1.3  ePWM Synchronization
        4. 17.16.1.4  ePWM Digital Compare
        5. 17.16.1.5  ePWM Digital Compare Event Filter Blanking Window
        6. 17.16.1.6  ePWM Valley Switching
        7. 17.16.1.7  ePWM Digital Compare Edge Filter
        8. 17.16.1.8  ePWM Deadband
        9. 17.16.1.9  ePWM DMA
        10. 17.16.1.10 ePWM Chopper
        11. 17.16.1.11 EPWM Configure Signal
        12. 17.16.1.12 Realization of Monoshot mode
        13. 17.16.1.13 EPWM Action Qualifier (epwm_up_aq)
      2. 17.16.2 HRPWM Examples
        1. 17.16.2.1 HRPWM Duty Control with SFO
        2. 17.16.2.2 HRPWM Slider
        3. 17.16.2.3 HRPWM Period Control
        4. 17.16.2.4 HRPWM Duty Control with UPDOWN Mode
        5. 17.16.2.5 HRPWM Slider Test
        6. 17.16.2.6 HRPWM Duty Up Count
        7. 17.16.2.7 HRPWM Period Up-Down Count
    17. 17.17 ePWM Registers
      1. 17.17.1 EPWM Base Address Table
      2. 17.17.2 EPWM_REGS Registers
      3. 17.17.3 Register to Driverlib Function Mapping
        1. 17.17.3.1 EPWM Registers to Driverlib Functions
        2. 17.17.3.2 HRPWM Registers to Driverlib Functions
  20. 18Enhanced Capture (eCAP)
    1. 18.1 Introduction
      1. 18.1.1 Features
      2. 18.1.2 ECAP Related Collateral
    2. 18.2 Description
    3. 18.3 Configuring Device Pins for the eCAP
    4. 18.4 Capture and APWM Operating Mode
    5. 18.5 Capture Mode Description
      1. 18.5.1  Event Prescaler
      2. 18.5.2  Edge Polarity Select and Qualifier
      3. 18.5.3  Continuous/One-Shot Control
      4. 18.5.4  32-Bit Counter and Phase Control
      5. 18.5.5  CAP1-CAP4 Registers
      6. 18.5.6  eCAP Synchronization
        1. 18.5.6.1 Example 1 - Using SWSYNC with ECAP Module
      7. 18.5.7  Interrupt Control
      8. 18.5.8  DMA Interrupt
      9. 18.5.9  Shadow Load and Lockout Control
      10. 18.5.10 APWM Mode Operation
    6. 18.6 Application of the eCAP Module
      1. 18.6.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger
      2. 18.6.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger
      3. 18.6.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger
      4. 18.6.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger
    7. 18.7 Application of the APWM Mode
      1. 18.7.1 Example 1 - Simple PWM Generation (Independent Channels)
    8. 18.8 Software
      1. 18.8.1 ECAP Examples
        1. 18.8.1.1 eCAP APWM Example
        2. 18.8.1.2 eCAP Capture PWM Example
        3. 18.8.1.3 eCAP APWM Phase-shift Example
        4. 18.8.1.4 eCAP Software Sync Example
    9. 18.9 eCAP Registers
      1. 18.9.1 ECAP Base Address Table
      2. 18.9.2 ECAP_REGS Registers
      3. 18.9.3 ECAP Registers to Driverlib Functions
  21. 19High Resolution Capture (HRCAP)
    1. 19.1 Introduction
      1. 19.1.1 HRCAP Related Collateral
      2. 19.1.2 Features
      3. 19.1.3 Description
    2. 19.2 Operational Details
      1. 19.2.1 HRCAP Clocking
      2. 19.2.2 HRCAP Initialization Sequence
      3. 19.2.3 HRCAP Interrupts
      4. 19.2.4 HRCAP Calibration
        1. 19.2.4.1 Applying the Scale Factor
    3. 19.3 Known Exceptions
    4. 19.4 Software
      1. 19.4.1 HRCAP Examples
        1. 19.4.1.1 HRCAP Capture and Calibration Example
    5. 19.5 HRCAP Registers
      1. 19.5.1 HRCAP Base Address Table
      2. 19.5.2 HRCAP_REGS Registers
      3. 19.5.3 HRCAP Registers to Driverlib Functions
  22. 20Enhanced Quadrature Encoder Pulse (eQEP)
    1. 20.1  Introduction
      1. 20.1.1 EQEP Related Collateral
    2. 20.2  Configuring Device Pins
    3. 20.3  Description
      1. 20.3.1 EQEP Inputs
      2. 20.3.2 Functional Description
      3. 20.3.3 eQEP Memory Map
    4. 20.4  Quadrature Decoder Unit (QDU)
      1. 20.4.1 Position Counter Input Modes
        1. 20.4.1.1 Quadrature Count Mode
        2. 20.4.1.2 Direction-Count Mode
        3. 20.4.1.3 Up-Count Mode
        4. 20.4.1.4 Down-Count Mode
      2. 20.4.2 eQEP Input Polarity Selection
      3. 20.4.3 Position-Compare Sync Output
    5. 20.5  Position Counter and Control Unit (PCCU)
      1. 20.5.1 Position Counter Operating Modes
        1. 20.5.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM]=00)
        2. 20.5.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM]=01)
        3. 20.5.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
        4. 20.5.1.4 Position Counter Reset on Unit Time-out Event (QEPCTL[PCRM] = 11)
      2. 20.5.2 Position Counter Latch
        1. 20.5.2.1 Index Event Latch
        2. 20.5.2.2 Strobe Event Latch
      3. 20.5.3 Position Counter Initialization
      4. 20.5.4 eQEP Position-compare Unit
    6. 20.6  eQEP Edge Capture Unit
    7. 20.7  eQEP Watchdog
    8. 20.8  eQEP Unit Timer Base
    9. 20.9  QMA Module
      1. 20.9.1 Modes of Operation
        1. 20.9.1.1 QMA Mode-1 (QMACTRL[MODE]=1)
        2. 20.9.1.2 QMA Mode-2 (QMACTRL[MODE]=2)
      2. 20.9.2 Interrupt and Error Generation
    10. 20.10 eQEP Interrupt Structure
    11. 20.11 Software
      1. 20.11.1 EQEP Examples
        1. 20.11.1.1 Frequency Measurement Using eQEP
        2. 20.11.1.2 Position and Speed Measurement Using eQEP
        3. 20.11.1.3 ePWM frequency Measurement Using eQEP via xbar connection
        4. 20.11.1.4 Frequency Measurement Using eQEP via unit timeout interrupt
        5. 20.11.1.5 Motor speed and direction measurement using eQEP via unit timeout interrupt
    12. 20.12 eQEP Registers
      1. 20.12.1 EQEP Base Address Table
      2. 20.12.2 EQEP_REGS Registers
      3. 20.12.3 EQEP Registers to Driverlib Functions
  23. 21Controller Area Network (CAN)
    1. 21.1  Introduction
      1. 21.1.1 DCAN Related Collateral
      2. 21.1.2 Features
      3. 21.1.3 Block Diagram
        1. 21.1.3.1 CAN Core
        2. 21.1.3.2 Message Handler
        3. 21.1.3.3 Message RAM
        4. 21.1.3.4 Registers and Message Object Access (IFx)
    2. 21.2  Functional Description
      1. 21.2.1 Configuring Device Pins
      2. 21.2.2 Address/Data Bus Bridge
    3. 21.3  Operating Modes
      1. 21.3.1 Initialization
      2. 21.3.2 CAN Message Transfer (Normal Operation)
        1. 21.3.2.1 Disabled Automatic Retransmission
        2. 21.3.2.2 Auto-Bus-On
      3. 21.3.3 Test Modes
        1. 21.3.3.1 Silent Mode
        2. 21.3.3.2 Loopback Mode
        3. 21.3.3.3 External Loopback Mode
        4. 21.3.3.4 Loopback Combined with Silent Mode
    4. 21.4  Multiple Clock Source
    5. 21.5  Interrupt Functionality
      1. 21.5.1 Message Object Interrupts
      2. 21.5.2 Status Change Interrupts
      3. 21.5.3 Error Interrupts
      4. 21.5.4 Peripheral Interrupt Expansion (PIE) Module Nomenclature for DCAN Interrupts
      5. 21.5.5 Interrupt Topologies
    6. 21.6  DMA Functionality
    7. 21.7  Parity Check Mechanism
      1. 21.7.1 Behavior on Parity Error
    8. 21.8  Debug Mode
    9. 21.9  Module Initialization
    10. 21.10 Configuration of Message Objects
      1. 21.10.1 Configuration of a Transmit Object for Data Frames
      2. 21.10.2 Configuration of a Transmit Object for Remote Frames
      3. 21.10.3 Configuration of a Single Receive Object for Data Frames
      4. 21.10.4 Configuration of a Single Receive Object for Remote Frames
      5. 21.10.5 Configuration of a FIFO Buffer
    11. 21.11 Message Handling
      1. 21.11.1  Message Handler Overview
      2. 21.11.2  Receive/Transmit Priority
      3. 21.11.3  Transmission of Messages in Event Driven CAN Communication
      4. 21.11.4  Updating a Transmit Object
      5. 21.11.5  Changing a Transmit Object
      6. 21.11.6  Acceptance Filtering of Received Messages
      7. 21.11.7  Reception of Data Frames
      8. 21.11.8  Reception of Remote Frames
      9. 21.11.9  Reading Received Messages
      10. 21.11.10 Requesting New Data for a Receive Object
      11. 21.11.11 Storing Received Messages in FIFO Buffers
      12. 21.11.12 Reading from a FIFO Buffer
    12. 21.12 CAN Bit Timing
      1. 21.12.1 Bit Time and Bit Rate
        1. 21.12.1.1 Synchronization Segment
        2. 21.12.1.2 Propagation Time Segment
        3. 21.12.1.3 Phase Buffer Segments and Synchronization
        4. 21.12.1.4 Oscillator Tolerance Range
      2. 21.12.2 Configuration of the CAN Bit Timing
        1. 21.12.2.1 Calculation of the Bit Timing Parameters
        2. 21.12.2.2 Example for Bit Timing at High Baudrate
        3. 21.12.2.3 Example for Bit Timing at Low Baudrate
    13. 21.13 Message Interface Register Sets
      1. 21.13.1 Message Interface Register Sets 1 and 2 (IF1 and IF2)
      2. 21.13.2 Message Interface Register Set 3 (IF3)
    14. 21.14 Message RAM
      1. 21.14.1 Structure of Message Objects
      2. 21.14.2 Addressing Message Objects in RAM
      3. 21.14.3 Message RAM Representation in Debug Mode
    15. 21.15 Software
      1. 21.15.1 CAN Examples
        1. 21.15.1.1 CAN External Loopback
        2. 21.15.1.2 CAN External Loopback with Interrupts
        3. 21.15.1.3 CAN External Loopback with DMA
        4. 21.15.1.4 CAN Transmit and Receive Configurations
        5. 21.15.1.5 CAN Error Generation Example
        6. 21.15.1.6 CAN Remote Request Loopback
        7. 21.15.1.7 CAN example that illustrates the usage of Mask registers
    16. 21.16 CAN Registers
      1. 21.16.1 CAN Base Address Table
      2. 21.16.2 CAN_REGS Registers
      3. 21.16.3 CAN Registers to Driverlib Functions
  24. 22Fast Serial Interface (FSI)
    1. 22.1 Introduction
      1. 22.1.1 FSI Related Collateral
      2. 22.1.2 FSI Features
    2. 22.2 System-level Integration
      1. 22.2.1 CPU Interface
      2. 22.2.2 Signal Description
        1. 22.2.2.1 Configuring Device Pins
      3. 22.2.3 FSI Interrupts
        1. 22.2.3.1 Transmitter Interrupts
        2. 22.2.3.2 Receiver Interrupts
        3. 22.2.3.3 Configuring Interrupts
        4. 22.2.3.4 Handling Interrupts
      4. 22.2.4 DMA Interface
      5. 22.2.5 External Frame Trigger Mux
    3. 22.3 FSI Functional Description
      1. 22.3.1  Introduction to Operation
      2. 22.3.2  FSI Transmitter Module
        1. 22.3.2.1 Initialization
        2. 22.3.2.2 FSI_TX Clocking
        3. 22.3.2.3 Transmitting Frames
          1. 22.3.2.3.1 Software Triggered Frames
          2. 22.3.2.3.2 Externally Triggered Frames
          3. 22.3.2.3.3 Ping Frame Generation
            1. 22.3.2.3.3.1 Automatic Ping Frames
            2. 22.3.2.3.3.2 Software Triggered Ping Frame
            3. 22.3.2.3.3.3 Externally Triggered Ping Frame
          4. 22.3.2.3.4 Transmitting Frames with DMA
        4. 22.3.2.4 Transmit Buffer Management
        5. 22.3.2.5 CRC Submodule
        6. 22.3.2.6 Conditions in Which the Transmitter Must Undergo a Soft Reset
        7. 22.3.2.7 Reset
      3. 22.3.3  FSI Receiver Module
        1. 22.3.3.1  Initialization
        2. 22.3.3.2  FSI_RX Clocking
        3. 22.3.3.3  Receiving Frames
          1. 22.3.3.3.1 Receiving Frames with DMA
        4. 22.3.3.4  Ping Frame Watchdog
        5. 22.3.3.5  Frame Watchdog
        6. 22.3.3.6  Delay Line Control
        7. 22.3.3.7  Buffer Management
        8. 22.3.3.8  CRC Submodule
        9. 22.3.3.9  Using the Zero Bits of the Receiver Tag Registers
        10. 22.3.3.10 Conditions in Which the Receiver Must Undergo a Soft Reset
        11. 22.3.3.11 FSI_RX Reset
      4. 22.3.4  Frame Format
        1. 22.3.4.1 FSI Frame Phases
        2. 22.3.4.2 Frame Types
          1. 22.3.4.2.1 Ping Frames
          2. 22.3.4.2.2 Error Frames
          3. 22.3.4.2.3 Data Frames
        3. 22.3.4.3 Multi-Lane Transmission
      5. 22.3.5  Flush Sequence
      6. 22.3.6  Internal Loopback
      7. 22.3.7  CRC Generation
      8. 22.3.8  ECC Module
      9. 22.3.9  Tag Matching
      10. 22.3.10 TDM Configurations
      11. 22.3.11 FSI Trigger Generation
      12. 22.3.12 FSI-SPI Compatibility Mode
        1. 22.3.12.1 Available SPI Modes
          1. 22.3.12.1.1 FSITX as SPI Master, Transmit Only
            1. 22.3.12.1.1.1 Initialization
            2. 22.3.12.1.1.2 Operation
          2. 22.3.12.1.2 FSIRX as SPI Slave, Receive Only
            1. 22.3.12.1.2.1 Initialization
            2. 22.3.12.1.2.2 Operation
          3. 22.3.12.1.3 FSITX and FSIRX Emulating a Full Duplex SPI Master
            1. 22.3.12.1.3.1 Initialization
            2. 22.3.12.1.3.2 Operation
    4. 22.4 FSI Programing Guide
      1. 22.4.1 Establishing the Communication Link
        1. 22.4.1.1 Establishing the Communication Link from the Master Device
        2. 22.4.1.2 Establishing the Communication Link from the Slave Device
      2. 22.4.2 Register Protection
      3. 22.4.3 Emulation Mode
    5. 22.5 Software
      1. 22.5.1 FSI Examples
        1. 22.5.1.1  FSI Loopback:CPU Control
        2. 22.5.1.2  FSI DMA frame transfers:DMA Control
        3. 22.5.1.3  FSI data transfer by external trigger
        4. 22.5.1.4  FSI data transfers upon CPU Timer event
        5. 22.5.1.5  FSI and SPI communication(fsi_ex6_spi_main_tx)
        6. 22.5.1.6  FSI and SPI communication(fsi_ex7_spi_remote_rx)
        7. 22.5.1.7  FSI P2Point Connection:Rx Side
        8. 22.5.1.8  FSI P2Point Connection:Tx Side
        9. 22.5.1.9  FSI daisy chain topology, lead device example
        10. 22.5.1.10 FSI daisy chain topology, node device example
    6. 22.6 FSI Registers
      1. 22.6.1 FSI Base Address Table
      2. 22.6.2 FSI_TX_REGS Registers
      3. 22.6.3 FSI_RX_REGS Registers
      4. 22.6.4 FSI Registers to Driverlib Functions
  25. 23Inter-Integrated Circuit Module (I2C)
    1. 23.1 Introduction
      1. 23.1.1 I2C Related Collateral
      2. 23.1.2 Features
      3. 23.1.3 Features Not Supported
      4. 23.1.4 Functional Overview
      5. 23.1.5 Clock Generation
      6. 23.1.6 I2C Clock Divider Registers (I2CCLKL and I2CCLKH)
        1. 23.1.6.1 Formula for the Master Clock Period
    2. 23.2 Configuring Device Pins
    3. 23.3 I2C Module Operational Details
      1. 23.3.1  Input and Output Voltage Levels
      2. 23.3.2  Selecting Pullup Resistors
      3. 23.3.3  Data Validity
      4. 23.3.4  Operating Modes
      5. 23.3.5  I2C Module START and STOP Conditions
      6. 23.3.6  Non-repeat Mode versus Repeat Mode
      7. 23.3.7  Serial Data Formats
        1. 23.3.7.1 7-Bit Addressing Format
        2. 23.3.7.2 10-Bit Addressing Format
        3. 23.3.7.3 Free Data Format
        4. 23.3.7.4 Using a Repeated START Condition
      8. 23.3.8  Clock Synchronization
      9. 23.3.9  Arbitration
      10. 23.3.10 Digital Loopback Mode
      11. 23.3.11 NACK Bit Generation
    4. 23.4 Interrupt Requests Generated by the I2C Module
      1. 23.4.1 Basic I2C Interrupt Requests
      2. 23.4.2 I2C FIFO Interrupts
    5. 23.5 Resetting or Disabling the I2C Module
    6. 23.6 Software
      1. 23.6.1 I2C Examples
        1. 23.6.1.1 C28x-I2C Library source file for FIFO interrupts
        2. 23.6.1.2 C28x-I2C Library source file for FIFO using polling
        3. 23.6.1.3 C28x-I2C Library source file for FIFO interrupts
        4. 23.6.1.4 I2C Digital Loopback with FIFO Interrupts
        5. 23.6.1.5 I2C EEPROM
        6. 23.6.1.6 I2C Digital External Loopback with FIFO Interrupts
        7. 23.6.1.7 I2C EEPROM
        8. 23.6.1.8 I2C controller target communication using FIFO interrupts
        9. 23.6.1.9 I2C EEPROM
    7. 23.7 I2C Registers
      1. 23.7.1 I2C Base Address Table
      2. 23.7.2 I2C_REGS Registers
      3. 23.7.3 I2C Registers to Driverlib Functions
  26. 24Local Interconnect Network (LIN)
    1. 24.1 Introduction
      1. 24.1.1 SCI Features
      2. 24.1.2 LIN Features
      3. 24.1.3 LIN Related Collateral
      4. 24.1.4 Block Diagram
    2. 24.2 Serial Communications Interface Module
      1. 24.2.1 SCI Communication Formats
        1. 24.2.1.1 SCI Frame Formats
        2. 24.2.1.2 SCI Asynchronous Timing Mode
        3. 24.2.1.3 SCI Baud Rate
          1. 24.2.1.3.1 Superfractional Divider, SCI Asynchronous Mode
        4. 24.2.1.4 SCI Multiprocessor Communication Modes
          1. 24.2.1.4.1 Idle-Line Multiprocessor Modes
          2. 24.2.1.4.2 Address-Bit Multiprocessor Mode
        5. 24.2.1.5 SCI Multibuffered Mode
      2. 24.2.2 SCI Interrupts
        1. 24.2.2.1 Transmit Interrupt
        2. 24.2.2.2 Receive Interrupt
        3. 24.2.2.3 WakeUp Interrupt
        4. 24.2.2.4 Error Interrupts
      3. 24.2.3 SCI DMA Interface
        1. 24.2.3.1 Receive DMA Requests
        2. 24.2.3.2 Transmit DMA Requests
      4. 24.2.4 SCI Configurations
        1. 24.2.4.1 Receiving Data
          1. 24.2.4.1.1 Receiving Data in Single-Buffer Mode
          2. 24.2.4.1.2 Receiving Data in Multibuffer Mode
        2. 24.2.4.2 Transmitting Data
          1. 24.2.4.2.1 Transmitting Data in Single-Buffer Mode
          2. 24.2.4.2.2 Transmitting Data in Multibuffer Mode
      5. 24.2.5 SCI Low-Power Mode
        1. 24.2.5.1 Sleep Mode for Multiprocessor Communication
    3. 24.3 Local Interconnect Network Module
      1. 24.3.1 LIN Communication Formats
        1. 24.3.1.1  LIN Standards
        2. 24.3.1.2  Message Frame
          1. 24.3.1.2.1 Message Header
          2. 24.3.1.2.2 Response
        3. 24.3.1.3  Synchronizer
        4. 24.3.1.4  Baud Rate
          1. 24.3.1.4.1 Fractional Divider
          2. 24.3.1.4.2 Superfractional Divider
            1. 24.3.1.4.2.1 Superfractional Divider In LIN Mode
        5. 24.3.1.5  Header Generation
          1. 24.3.1.5.1 Event Triggered Frame Handling
          2. 24.3.1.5.2 Header Reception and Adaptive Baud Rate
        6. 24.3.1.6  Extended Frames Handling
        7. 24.3.1.7  Timeout Control
          1. 24.3.1.7.1 No-Response Error (NRE)
          2. 24.3.1.7.2 Bus Idle Detection
          3. 24.3.1.7.3 Timeout After Wakeup Signal and Timeout After Three Wakeup Signals
        8. 24.3.1.8  TXRX Error Detector (TED)
          1. 24.3.1.8.1 Bit Errors
          2. 24.3.1.8.2 Physical Bus Errors
          3. 24.3.1.8.3 ID Parity Errors
          4. 24.3.1.8.4 Checksum Errors
        9. 24.3.1.9  Message Filtering and Validation
        10. 24.3.1.10 Receive Buffers
        11. 24.3.1.11 Transmit Buffers
      2. 24.3.2 LIN Interrupts
      3. 24.3.3 Servicing LIN Interrupts
      4. 24.3.4 LIN DMA Interface
        1. 24.3.4.1 LIN Receive DMA Requests
        2. 24.3.4.2 LIN Transmit DMA Requests
      5. 24.3.5 LIN Configurations
        1. 24.3.5.1 Receiving Data
          1. 24.3.5.1.1 Receiving Data in Single-Buffer Mode
          2. 24.3.5.1.2 Receiving Data in Multibuffer Mode
        2. 24.3.5.2 Transmitting Data
          1. 24.3.5.2.1 Transmitting Data in Single-Buffer Mode
          2. 24.3.5.2.2 Transmitting Data in Multibuffer Mode
    4. 24.4 Low-Power Mode
      1. 24.4.1 Entering Sleep Mode
      2. 24.4.2 Wakeup
      3. 24.4.3 Wakeup Timeouts
    5. 24.5 Emulation Mode
    6. 24.6 Software
      1. 24.6.1 LIN Examples
        1. 24.6.1.1 LIN Internal Loopback with Interrupts
        2. 24.6.1.2 LIN SCI Mode Internal Loopback with Interrupts
        3. 24.6.1.3 LIN SCI MODE Internal Loopback with DMA
        4. 24.6.1.4 LIN Internal Loopback without interrupts(polled mode)
        5. 24.6.1.5 LIN Internal Loopback with Interrupts using Sysconfig
        6. 24.6.1.6 LIN Incomplete Header Detection
        7. 24.6.1.7 LIN SCI MODE (Single Buffer) Internal Loopback with DMA
        8. 24.6.1.8 LIN External Loopback without interrupts(polled mode)
    7. 24.7 SCI/LIN Registers
      1. 24.7.1 LIN Base Address Table
      2. 24.7.2 LIN_REGS Registers
      3. 24.7.3 LIN Registers to Driverlib Functions
  27. 25Power Management Bus Module (PMBus)
    1. 25.1 Introduction
      1. 25.1.1 PMBUS Related Collateral
      2. 25.1.2 Features
      3. 25.1.3 Block Diagram
    2. 25.2 Configuring Device Pins
    3. 25.3 Slave Mode Operation
      1. 25.3.1 Configuration
      2. 25.3.2 Message Handling
        1. 25.3.2.1  Quick Command
        2. 25.3.2.2  Send Byte
        3. 25.3.2.3  Receive Byte
        4. 25.3.2.4  Write Byte and Write Word
        5. 25.3.2.5  Read Byte and Read Word
        6. 25.3.2.6  Process Call
        7. 25.3.2.7  Block Write
        8. 25.3.2.8  Block Read
        9. 25.3.2.9  Block Write-Block Read Process Call
        10. 25.3.2.10 Alert Response
        11. 25.3.2.11 Extended Command
        12. 25.3.2.12 Group Command
    4. 25.4 Master Mode Operation
      1. 25.4.1 Configuration
      2. 25.4.2 Message Handling
        1. 25.4.2.1  Quick Command
        2. 25.4.2.2  Send Byte
        3. 25.4.2.3  Receive Byte
        4. 25.4.2.4  Write Byte and Write Word
        5. 25.4.2.5  Read Byte and Read Word
        6. 25.4.2.6  Process Call
        7. 25.4.2.7  Block Write
        8. 25.4.2.8  Block Read
        9. 25.4.2.9  Block Write-Block Read Process Call
        10. 25.4.2.10 Alert Response
        11. 25.4.2.11 Extended Command
        12. 25.4.2.12 Group Command
    5. 25.5 PMBus Registers
      1. 25.5.1 PMBUS Base Address Table
      2. 25.5.2 PMBUS_REGS Registers
      3. 25.5.3 PMBUS Registers to Driverlib Functions
  28. 26Serial Communications Interface (SCI)
    1. 26.1  Introduction
      1. 26.1.1 Features
      2. 26.1.2 SCI Related Collateral
      3. 26.1.3 Block Diagram
    2. 26.2  Architecture
    3. 26.3  SCI Module Signal Summary
    4. 26.4  Configuring Device Pins
    5. 26.5  Multiprocessor and Asynchronous Communication Modes
    6. 26.6  SCI Programmable Data Format
    7. 26.7  SCI Multiprocessor Communication
      1. 26.7.1 Recognizing the Address Byte
      2. 26.7.2 Controlling the SCI TX and RX Features
      3. 26.7.3 Receipt Sequence
    8. 26.8  Idle-Line Multiprocessor Mode
      1. 26.8.1 Idle-Line Mode Steps
      2. 26.8.2 Block Start Signal
      3. 26.8.3 Wake-Up Temporary (WUT) Flag
        1. 26.8.3.1 Sending a Block Start Signal
      4. 26.8.4 Receiver Operation
    9. 26.9  Address-Bit Multiprocessor Mode
      1. 26.9.1 Sending an Address
    10. 26.10 SCI Communication Format
      1. 26.10.1 Receiver Signals in Communication Modes
      2. 26.10.2 Transmitter Signals in Communication Modes
    11. 26.11 SCI Port Interrupts
      1. 26.11.1 Break Detect
    12. 26.12 SCI Baud Rate Calculations
    13. 26.13 SCI Enhanced Features
      1. 26.13.1 SCI FIFO Description
      2. 26.13.2 SCI Auto-Baud
      3. 26.13.3 Autobaud-Detect Sequence
    14. 26.14 Software
      1. 26.14.1 SCI Examples
        1. 26.14.1.1 Tune Baud Rate via UART Example
        2. 26.14.1.2 SCI FIFO Digital Loop Back
        3. 26.14.1.3 SCI Digital Loop Back with Interrupts
        4. 26.14.1.4 SCI Echoback
        5. 26.14.1.5 stdout redirect example
    15. 26.15 SCI Registers
      1. 26.15.1 SCI Base Address Table
      2. 26.15.2 SCI_REGS Registers
      3. 26.15.3 SCI Registers to Driverlib Functions
  29. 27Serial Peripheral Interface (SPI)
    1. 27.1 Introduction
      1. 27.1.1 Features
      2. 27.1.2 SPI Related Collateral
      3. 27.1.3 Block Diagram
    2. 27.2 System-Level Integration
      1. 27.2.1 SPI Module Signals
      2. 27.2.2 Configuring Device Pins
        1. 27.2.2.1 GPIOs Required for High-Speed Mode
      3. 27.2.3 SPI Interrupts
      4. 27.2.4 DMA Support
    3. 27.3 SPI Operation
      1. 27.3.1  Introduction to Operation
      2. 27.3.2  Master Mode
      3. 27.3.3  Slave Mode
      4. 27.3.4  Data Format
        1. 27.3.4.1 Transmission of Bit from SPIRXBUF
      5. 27.3.5  Baud Rate Selection
        1. 27.3.5.1 Baud Rate Determination
        2. 27.3.5.2 Baud Rate Calculation in Non-High Speed Mode (HS_MODE = 0)
      6. 27.3.6  SPI Clocking Schemes
      7. 27.3.7  SPI FIFO Description
      8. 27.3.8  SPI DMA Transfers
        1. 27.3.8.1 Transmitting Data Using SPI with DMA
        2. 27.3.8.2 Receiving Data Using SPI with DMA
      9. 27.3.9  SPI High-Speed Mode
      10. 27.3.10 SPI 3-Wire Mode Description
    4. 27.4 Programming Procedure
      1. 27.4.1 Initialization Upon Reset
      2. 27.4.2 Configuring the SPI
      3. 27.4.3 Configuring the SPI for High-Speed Mode
      4. 27.4.4 Data Transfer Example
      5. 27.4.5 SPI 3-Wire Mode Code Examples
        1. 27.4.5.1 3-Wire Master Mode Transmit
        2.       1365
          1. 27.4.5.2.1 3-Wire Master Mode Receive
        3.       1367
          1. 27.4.5.2.1 3-Wire Slave Mode Transmit
        4.       1369
          1. 27.4.5.2.1 3-Wire Slave Mode Receive
      6. 27.4.6 SPI STEINV Bit in Digital Audio Transfers
    5. 27.5 Software
      1. 27.5.1 SPI Examples
        1. 27.5.1.1 SPI Digital Loopback
        2. 27.5.1.2 SPI Digital Loopback with FIFO Interrupts
        3. 27.5.1.3 SPI Digital External Loopback without FIFO Interrupts
        4. 27.5.1.4 SPI Digital External Loopback with FIFO Interrupts
        5. 27.5.1.5 SPI Digital Loopback with DMA
        6. 27.5.1.6 SPI EEPROM
        7. 27.5.1.7 SPI DMA EEPROM
    6. 27.6 SPI Registers
      1. 27.6.1 SPI Base Address Table
      2. 27.6.2 SPI_REGS Registers
      3. 27.6.3 SPI Registers to Driverlib Functions
  30. 28Revision History

17.17.2 EPWM_REGS Registers

Table 17-22 lists the memory-mapped registers for the EPWM_REGS registers. All register offset addresses not listed in Table 17-22 should be considered as reserved locations and the register contents should not be modified.

Table 17-22 EPWM_REGS Registers
OffsetAcronymRegister NameWrite ProtectionSection
0hTBCTLTime Base Control RegisterGo
1hTBCTL2Time Base Control Register 2Go
3hEPWMSYNCINSELEPWMxSYNCIN Source Select RegisterGo
4hTBCTRTime Base Counter RegisterGo
5hTBSTSTime Base Status RegisterGo
6hEPWMSYNCOUTENEPWMxSYNCOUT Source Enable RegisterGo
7hTBCTL3Time Base Control Register 3Go
8hCMPCTLCounter Compare Control RegisterGo
9hCMPCTL2Counter Compare Control Register 2Go
ChDBCTLDead-Band Generator Control RegisterGo
DhDBCTL2Dead-Band Generator Control Register 2Go
10hAQCTLAction Qualifier Control RegisterGo
11hAQTSRCSELAction Qualifier Trigger Event Source Select RegisterGo
14hPCCTLPWM Chopper Control RegisterGo
18hVCAPCTLValley Capture Control RegisterGo
19hVCNTCFGValley Counter Config RegisterGo
20hHRCNFGHRPWM Configuration RegisterEALLOWGo
21hHRPWRHRPWM Power RegisterEALLOWGo
26hHRMSTEPHRPWM MEP Step RegisterEALLOWGo
27hHRCNFG2HRPWM Configuration 2 RegisterEALLOWGo
2DhHRPCTLHigh Resolution Period Control RegisterEALLOWGo
2EhTRREMHRPWM High Resolution Remainder RegisterEALLOWGo
34hGLDCTLGlobal PWM Load Control RegisterEALLOWGo
35hGLDCFGGlobal PWM Load Config RegisterEALLOWGo
38hEPWMXLINKEPWMx Link RegisterGo
40hAQCTLAAction Qualifier Control Register For Output AGo
41hAQCTLA2Additional Action Qualifier Control Register For Output AGo
42hAQCTLBAction Qualifier Control Register For Output BGo
43hAQCTLB2Additional Action Qualifier Control Register For Output BGo
47hAQSFRCAction Qualifier Software Force RegisterGo
49hAQCSFRCAction Qualifier Continuous S/W Force RegisterGo
50hDBREDHRDead-Band Generator Rising Edge Delay High Resolution Mirror RegisterGo
51hDBREDDead-Band Generator Rising Edge Delay High Resolution Mirror RegisterGo
52hDBFEDHRDead-Band Generator Falling Edge Delay High Resolution RegisterGo
53hDBFEDDead-Band Generator Falling Edge Delay Count RegisterGo
60hTBPHSTime Base Phase HighGo
62hTBPRDHRTime Base Period High Resolution RegisterGo
63hTBPRDTime Base Period RegisterGo
6AhCMPACounter Compare A RegisterGo
6ChCMPBCompare B RegisterGo
6FhCMPCCounter Compare C RegisterGo
71hCMPDCounter Compare D RegisterGo
74hGLDCTL2Global PWM Load Control Register 2Go
77hSWVDELVALSoftware Valley Mode Delay RegisterGo
80hTZSELTrip Zone Select RegisterEALLOWGo
82hTZDCSELTrip Zone Digital Comparator Select RegisterEALLOWGo
84hTZCTLTrip Zone Control RegisterEALLOWGo
85hTZCTL2Additional Trip Zone Control RegisterEALLOWGo
86hTZCTLDCATrip Zone Control Register Digital Compare AEALLOWGo
87hTZCTLDCBTrip Zone Control Register Digital Compare BEALLOWGo
8DhTZEINTTrip Zone Enable Interrupt RegisterEALLOWGo
93hTZFLGTrip Zone Flag RegisterGo
94hTZCBCFLGTrip Zone CBC Flag RegisterGo
95hTZOSTFLGTrip Zone OST Flag RegisterGo
97hTZCLRTrip Zone Clear RegisterEALLOWGo
98hTZCBCCLRTrip Zone CBC Clear RegisterEALLOWGo
99hTZOSTCLRTrip Zone OST Clear RegisterEALLOWGo
9BhTZFRCTrip Zone Force RegisterEALLOWGo
A4hETSELEvent Trigger Selection RegisterGo
A6hETPSEvent Trigger Pre-Scale RegisterGo
A8hETFLGEvent Trigger Flag RegisterGo
AAhETCLREvent Trigger Clear RegisterGo
AChETFRCEvent Trigger Force RegisterGo
AEhETINTPSEvent-Trigger Interrupt Pre-Scale RegisterGo
B0hETSOCPSEvent-Trigger SOC Pre-Scale RegisterGo
B2hETCNTINITCTLEvent-Trigger Counter Initialization Control RegisterGo
B4hETCNTINITEvent-Trigger Counter Initialization RegisterGo
C0hDCTRIPSELDigital Compare Trip Select RegisterEALLOWGo
C3hDCACTLDigital Compare A Control RegisterEALLOWGo
C4hDCBCTLDigital Compare B Control RegisterEALLOWGo
C7hDCFCTLDigital Compare Filter Control RegisterEALLOWGo
C8hDCCAPCTLDigital Compare Capture Control RegisterEALLOWGo
C9hDCFOFFSETDigital Compare Filter Offset RegisterGo
CAhDCFOFFSETCNTDigital Compare Filter Offset Counter RegisterGo
CBhDCFWINDOWDigital Compare Filter Window RegisterGo
CChDCFWINDOWCNTDigital Compare Filter Window Counter RegisterGo
CFhDCCAPDigital Compare Counter Capture RegisterGo
D2hDCAHTRIPSELDigital Compare AH Trip SelectEALLOWGo
D3hDCALTRIPSELDigital Compare AL Trip SelectEALLOWGo
D4hDCBHTRIPSELDigital Compare BH Trip SelectEALLOWGo
D5hDCBLTRIPSELDigital Compare BL Trip SelectEALLOWGo
FAhEPWMLOCKEPWM Lock RegisterGo
FDhHWVDELVALHardware Valley Mode Delay RegisterGo
FEhVCNTVALHardware Valley Counter RegisterGo

Complex bit access types are encoded to fit into small table cells. Table 17-23 shows the codes that are used for access types in this section.

Table 17-23 EPWM_REGS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
R-0R
-0		Read
Returns 0s
Write Type
WWWrite
W1CW
1C		Write
1 to clear
W1SW
1S		Write
1 to set
WOnceW
Once		Write
Write once
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

17.17.2.1 TBCTL Register (Offset = 0h) [Reset = 0083h]

TBCTL is shown in Figure 17-93 and described in Table 17-24.

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Time Base Control Register

Figure 17-93 TBCTL Register
15141312111098
FREE_SOFTPHSDIRCLKDIVHSPCLKDIV
R/W-0hR/W-0hR/W-0hR/W-1h
76543210
HSPCLKDIVSWFSYNCRESERVEDPRDLDPHSENCTRMODE
R/W-1hR-0/W1S-0hR-0hR/W-0hR/W-0hR/W-3h
Table 17-24 TBCTL Register Field Descriptions
BitFieldTypeResetDescription
15-14FREE_SOFTR/W0hEmulation Mode Bits. These bits select the behavior of the ePWM time-base counter during emulation events

00: Stop after the next time-base counter increment or decrement
01: Stop when counter completes a whole cycle:
- Up-count mode: stop when the time-base counter = period (TBCTR = TBPRD)
- Down-count mode: stop when the time-base counter = 0x00 (TBCTR = 0x00)
- Up-down-count mode: stop when the time-base counter = 0x00 (TBCTR = 0x00)
1x: Free run

Reset type: SYSRSn

13PHSDIRR/W0hPhase Direction Bit

This bit is only used when the time-base counter is configured in the up-down-count mode. The
PHSDIR bit indicates the direction the time-base counter (TBCTR) will count after a synchronization
event occurs and a new phase value is loaded from the phase (TBPHS) register. This is
irrespective of the direction of the counter before the synchronization event..
In the up-count and down-count modes this bit is ignored.

0: Count down after the synchronization event.
1: Count up after the synchronization event.

Reset type: SYSRSn

12-10CLKDIVR/W0hTime Base Clock Pre-Scale Bits

These bits select the time base clock pre-scale value (TBCLK = EPWMCLK/(HSPCLKDIV * CLKDIV):

000: /1 (default on reset)
001: /2
010: /4
011: /8
100: /16
101: /32
110: /64
111: /128

Reset type: SYSRSn

9-7HSPCLKDIVR/W1hHigh Speed Time Base Clock Pre-Scale Bits

These bits determine part of the time-base clock prescale value.
TBCLK = EPWMCLK / (HSPCLKDIV x CLKDIV). This divisor emulates the HSPCLK in the TMS320x281x system as used on the Event Manager (EV) peripheral.

000: /1
001: /2 (default on reset)
010: /4
011: /6
100: /8
101: /10
110: /12
111: /14

Reset type: SYSRSn

6SWFSYNCR-0/W1S0hSoftware Forced Sync Pulse

0: Writing a 0 has no effect and reads always return a 0.
1: Writing a 1 forces a one-time synchronization pulse to be generated.
SWFSYNC can be enabled to affect EPWMxSYNCO by setting the EPWMSYNCOUTEN.SWEN bit.

Reset type: SYSRSn

5-4RESERVEDR0hReserved
3PRDLDR/W0hActive Period Reg Load from Shadow Select

0: The period register (TBPRD) is loaded from its shadow register when the time-base counter, TBCTR, is equal to zero and/or a sync event as determined by the TBCTL2[PRDLDSYNC] bit.
A write/read to the TBPRD register accesses the shadow register.

1: Immediate Mode (Shadow register bypassed): A write or read to the TBPRD register accesses the active register.

Reset type: SYSRSn

2PHSENR/W0hCounter Reg Load from Phase Reg Enable

0: Do not load the time-base counter (TBCTR) from the time-base phase register (TBPHS).
1: Allow Counter to be loaded from the Phase register (TBPHS) and shadow to active load events when an EPWMxSYNCI input signal occurs or a software-forced sync signal, see bit 6.

Reset type: SYSRSn

1-0CTRMODER/W3hCounter Mode

The time-base counter mode is normally configured once and not changed during normal operation. If you change the mode of the counter, the change will take effect at the next TBCLK edge and the current counter value shall increment or decrement from the value before the mode change. These bits set the time-base counter mode of operation as follows:
00: Up-count mode
01: Down-count mode
10: Up-down count mode
11: Freeze counter operation (default on reset)

Reset type: SYSRSn

17.17.2.2 TBCTL2 Register (Offset = 1h) [Reset = 0000h]

TBCTL2 is shown in Figure 17-94 and described in Table 17-25.

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Time Base Control Register 2

Figure 17-94 TBCTL2 Register
15141312111098
PRDLDSYNCRESERVEDRESERVED
R/W-0hR-0hR-0-0h
76543210
OSHTSYNCOSHTSYNCMODERESERVEDRESERVED
R-0/W1S-0hR/W-0hR/W-0hR-0-0h
Table 17-25 TBCTL2 Register Field Descriptions
BitFieldTypeResetDescription
15-14PRDLDSYNCR/W0hShadow to Active Period Register Load on SYNC event

00: Shadow to Active Load of TBPRD occurs only when TBCTR = 0 (same as legacy).
01: Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs.
10: Shadow to Active Load of TBPRD occurs only when a SYNC is received.
11: Reserved

Note: This bit selection is valid only if TBCTL[PRDLD]=0.

Reset type: SYSRSn

13-12RESERVEDR0hReserved
11-8RESERVEDR-00hReserved
7OSHTSYNCR-0/W1S0hOneshot sync bit

0: Writing a '0' has no effect.
1: Allow one sync pulse to propogate.

Reset type: SYSRSn

6OSHTSYNCMODER/W0hOneshot sync enable bit

0: Oneshot sync mode disabled
1: Oneshot sync mode enabled

Reset type: SYSRSn

5RESERVEDR/W0hReserved
4-0RESERVEDR-00hReserved

17.17.2.3 EPWMSYNCINSEL Register (Offset = 3h) [Reset = 0001h]

EPWMSYNCINSEL is shown in Figure 17-95 and described in Table 17-26.

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EPWMxSYNCIN Source Select Register

Figure 17-95 EPWMSYNCINSEL Register
15141312111098
RESERVED
R-0h
76543210
RESERVEDSEL
R-0hR/W-1h
Table 17-26 EPWMSYNCINSEL Register Field Descriptions
BitFieldTypeResetDescription
15-5RESERVEDR0hReserved
4-0SELR/W1hThese bits determine the source of the EPWMxSYNCI signal.
0x00 Disabled
Other Values defined in the 'ePWM SYNC Selection' table

Reset type: SYSRSn

17.17.2.4 TBCTR Register (Offset = 4h) [Reset = 0000h]

TBCTR is shown in Figure 17-96 and described in Table 17-27.

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Time Base Counter Register

Figure 17-96 TBCTR Register
15141312111098
TBCTR
R/W-0h
76543210
TBCTR
R/W-0h
Table 17-27 TBCTR Register Field Descriptions
BitFieldTypeResetDescription
15-0TBCTRR/W0hTime Base Counter Register

Reset type: SYSRSn

17.17.2.5 TBSTS Register (Offset = 5h) [Reset = 0001h]

TBSTS is shown in Figure 17-97 and described in Table 17-28.

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Time Base Status Register

Figure 17-97 TBSTS Register
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDCTRMAXSYNCICTRDIR
R-0-0hR/W1C-0hR/W1C-0hR-1h
Table 17-28 TBSTS Register Field Descriptions
BitFieldTypeResetDescription
15-3RESERVEDR-00hReserved
2CTRMAXR/W1C0hTime-Base Counter Max Latched Status Bit

0: Reading a 0 indicates the time-base counter never reached its maximum value. Writing a 0 will have no effect.
1: Reading a 1 on this bit indicates that the time-base counter reached the max value 0xFFFF. Writing a 1 to this bit will clear the latched event.

Reset type: SYSRSn

1SYNCIR/W1C0hInput Synchronization Latched Status Bit

0: Writing a 0 will have no effect. Reading a 0 indicates no external synchronization event has occurred.
1: Reading a 1 on this bit indicates that an external synchronization event has occurred (EPWMxSYNCI). Writing a 1 to this bit will clear the latched event.

Reset type: SYSRSn

0CTRDIRR1hTime Base Counter Direction Status Bit

0: Time-Base Counter is currently counting down.
1: Time-Base Counter is currently counting up.

Note: This bit is only valid when the counter is not frozen.

Reset type: SYSRSn

17.17.2.6 EPWMSYNCOUTEN Register (Offset = 6h) [Reset = 0001h]

EPWMSYNCOUTEN is shown in Figure 17-98 and described in Table 17-29.

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EPWMxSYNCOUT Source Enable Register

Figure 17-98 EPWMSYNCOUTEN Register
15141312111098
RESERVED
R-0h
76543210
RESERVEDDCBEVT1ENDCAEVT1ENCMPDENCMPCENCMPBENZEROENSWEN
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-1h
Table 17-29 EPWMSYNCOUTEN Register Field Descriptions
BitFieldTypeResetDescription
15-8RESERVEDR0hReserved
7RESERVEDR0hReserved
6DCBEVT1ENR/W0hThis bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal.
0 Disabled
1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event

Reset type: SYSRSn

5DCAEVT1ENR/W0hThis bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal.
0 Disabled
1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event

Reset type: SYSRSn

4CMPDENR/W0hThis bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal.
0 Disabled
1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event (TBCTR = CMPD)

Reset type: SYSRSn

3CMPCENR/W0hThis bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal.
0 Disabled
1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event (TBCTR = CMPC)

Reset type: SYSRSn

2CMPBENR/W0hThis bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal.
0 Disabled
1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event (TBCTR = CMPB)

Reset type: SYSRSn

1ZEROENR/W0hThis bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal.
0 Disabled
1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000

Reset type: SYSRSn

0SWENR/W1hThis bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal.
0 Disabled
1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set

Reset type: SYSRSn

17.17.2.7 TBCTL3 Register (Offset = 7h) [Reset = 0000h]

TBCTL3 is shown in Figure 17-99 and described in Table 17-30.

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Time Base Control Register 3

Figure 17-99 TBCTL3 Register
15141312111098
RESERVED
R-0h
76543210
RESERVEDOSSFRCEN
R-0hR/W-0h
Table 17-30 TBCTL3 Register Field Descriptions
BitFieldTypeResetDescription
15-1RESERVEDR0hReserved
0OSSFRCENR/W0hThis bit determines which bit sets the EPWMxSYNCOUT One Shot Latch.
0 TBCTL2[OSHTSYNC] sets the One Shot Latch
1 GLDCTL2[OSHTLD] sets the One Shot Latch

Reset type: SYSRSn

17.17.2.8 CMPCTL Register (Offset = 8h) [Reset = 0000h]

CMPCTL is shown in Figure 17-100 and described in Table 17-31.

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Counter Compare Control Register

Figure 17-100 CMPCTL Register
15141312111098
RESERVEDLOADBSYNCLOADASYNCSHDWBFULLSHDWAFULL
R-0-0hR/W-0hR/W-0hR-0hR-0h
76543210
RESERVEDSHDWBMODERESERVEDSHDWAMODELOADBMODELOADAMODE
R-0-0hR/W-0hR-0-0hR/W-0hR/W-0hR/W-0h
Table 17-31 CMPCTL Register Field Descriptions
BitFieldTypeResetDescription
15-14RESERVEDR-00hReserved
13-12LOADBSYNCR/W0hShadow to Active CMPB Register Load on SYNC event

00: Shadow to Active Load of CMPB:CMPBHR occurs according to LOADBMODE (bits 1,0) (same as legacy)
01: Shadow to Active Load of CMPB:CMPBHR occurs both according to LOADBMODE bits and when SYNC occurs
10: Shadow to Active Load of CMPB:CMPBHR occurs only when a SYNC is received
11: Reserved

Note: This bit is valid only if CMPCTL[SHDWBMODE] = 0.

Reset type: SYSRSn

11-10LOADASYNCR/W0hShadow to Active CMPA Register Load on SYNC event

00: Shadow to Active Load of CMPA:CMPAHR occurs according to LOADAMODE (bits 1,0) (same as legacy)
01: Shadow to Active Load of CMPA:CMPAHR occurs both according to LOADAMODE bits and when SYNC occurs
10: Shadow to Active Load of CMPA:CMPAHR occurs only when a SYNC is received
11: Reserved

Note: This bit is valid only if CMPCTL[SHDWAMODE] = 0.

Reset type: SYSRSn

9SHDWBFULLR0hCounter-compare B (CMPB) Shadow Register Full Status Flag

This bit self clears once a loadstrobe occurs.

0: CMPB shadow register not full yet
1: Indicates the CMPB shadow register is full
a CPU write will overwrite current shadow value

Reset type: SYSRSn

8SHDWAFULLR0hCounter-compare A (CMPA) Shadow Register Full Status Flag

The flag bit is set when a 32-bit write to CMPA:CMPAHR register or a 16-bit write to CMPA register is made. A 16-bit write to CMPAHR register will not affect the flag. This bit self clears once a load-strobe occurs.

0: CMPA shadow register not full yet
1: Indicates the CMPA shadow register is full, a CPU write will overwrite the current shadow value

Reset type: SYSRSn

7RESERVEDR-00hReserved
6SHDWBMODER/W0hCounter-compare B (CMPB) Register Operating Mode

0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register
1: Immediate mode. Only the active compare B register is used. All writes and reads directly access the active register for immediate compare action

Reset type: SYSRSn

5RESERVEDR-00hReserved
4SHDWAMODER/W0hCounter-compare A (CMPA) Register Operating Mode

0: Shadow mode. Operates as a double buffer. All writes via the CPU access the shadow register
1: Immediate mode. Only the active compare register is used. All writes and reads directly access the active register for immediate compare action

Reset type: SYSRSn

3-2LOADBMODER/W0hActive Counter-Compare B (CMPB) Load From Shadow Select Mode

This bit has no effect in immediate mode (CMPCTL[SHDWBMODE] = 1).

00: Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)
01: Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD)
10: Load on either CTR = Zero or CTR = PRD
11: Freeze (no loads possible)

Reset type: SYSRSn

1-0LOADAMODER/W0hActive Counter-Compare A (CMPA) Load From Shadow Select Mode

This bit has no effect in immediate mode (CMPCTL[SHDWAMODE] = 1).

00: Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)
01: Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD)
10: Load on either CTR = Zero or CTR = PRD
11: Freeze (no loads possible)

Reset type: SYSRSn

17.17.2.9 CMPCTL2 Register (Offset = 9h) [Reset = 0000h]

CMPCTL2 is shown in Figure 17-101 and described in Table 17-32.

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Counter Compare Control Register 2

Figure 17-101 CMPCTL2 Register
15141312111098
RESERVEDLOADDSYNCLOADCSYNCRESERVED
R-0-0hR/W-0hR/W-0hR-0-0h
76543210
RESERVEDSHDWDMODERESERVEDSHDWCMODELOADDMODELOADCMODE
R-0-0hR/W-0hR-0-0hR/W-0hR/W-0hR/W-0h
Table 17-32 CMPCTL2 Register Field Descriptions
BitFieldTypeResetDescription
15-14RESERVEDR-00hReserved
13-12LOADDSYNCR/W0hShadow to Active CMPD Register Load on SYNC event

00: Shadow to Active Load of CMPD occurs according to LOADDMODE
01: Shadow to Active Load of CMPD occurs both according to LOADDMODE bits and when SYNC occurs
10: Shadow to Active Load of CMPD occurs only when a SYNC is received
11: Reserved

Note: This bit is valid only if CMPCTL2[SHDWDMODE] = 0.

Reset type: SYSRSn

11-10LOADCSYNCR/W0hShadow to Active CMPC Register Load on SYNC event

00: Shadow to Active Load of CMPC occurs according to LOADCMODE
01: Shadow to Active Load of CMPC occurs both according to LOADCMODE bits and when SYNC occurs
10: Shadow to Active Load of CMPC occurs only when a SYNC is received
11: Reserved

Note: This bit is valid only if CMPCTL2[SHDWCMODE] = 0.

Reset type: SYSRSn

9-7RESERVEDR-00hReserved
6SHDWDMODER/W0hCounter-Compare D Register Operating Mode

0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register.
1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the Active register for immediate Compare action.

Reset type: SYSRSn

5RESERVEDR-00hReserved
4SHDWCMODER/W0hCounter-Compare C Register Operating Mode

0: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register.
1: Immediate mode - only the Active compare register is used. All writes/reads via the CPU directly access the Active register for immediate Compare action.

Reset type: SYSRSn

3-2LOADDMODER/W0hActive Counter-Compare D (CMPD) Load from Shadow Select Mode

00: Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)
01: Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD)
10: Load on either CTR = Zero or CTR = PRD
11: Freeze (no loads possible)

Note: Has no effect in Immediate mode.

Reset type: SYSRSn

1-0LOADCMODER/W0hActive Counter-Compare C (CMPC) Load from Shadow Select Mode

00: Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)
01: Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD)
10: Load on either CTR = Zero or CTR = PRD
11: Freeze (no loads possible)

Note: Has no effect in Immediate mode.

Reset type: SYSRSn

17.17.2.10 DBCTL Register (Offset = Ch) [Reset = 0000h]

DBCTL is shown in Figure 17-102 and described in Table 17-33.

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Dead-Band Generator Control Register

Figure 17-102 DBCTL Register
15141312111098
HALFCYCLEDEDB_MODEOUTSWAPSHDWDBFEDMODESHDWDBREDMODELOADFEDMODE
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
LOADREDMODEIN_MODEPOLSELOUT_MODE
R/W-0hR/W-0hR/W-0hR/W-0h
Table 17-33 DBCTL Register Field Descriptions
BitFieldTypeResetDescription
15HALFCYCLER/W0hHalf Cycle Clocking Enable Bit

0: Full cycle clocking enabled. The dead-band counters are clocked at the TBCLK rate.
1: Half cycle clocking enabled. The dead-band counters are clocked at TBCLK*2.

Reset type: SYSRSn

14DEDB_MODER/W0hDead Band Dual-Edge B Mode Control (S8 switch)

0: Rising edge delay applied to InA/InB as selected by S4 switch (IN-MODE bits) on A signal path only. Falling edge delay applied to InA/InB as selected by S5 switch (INMODE bits) on B signal path only.
1: Rising edge delay and falling edge delay applied to source selected by S4 switch (INMODE bits) and output to B signal path only. Note: When this bit is set to 1, user should always either set OUT_MODE bits such that Apath = InA OR OUTSWAP bits such that OutA=Bpath
otherwise, OutA will be invalid.

Reset type: SYSRSn

13-12OUTSWAPR/W0hDead Band Output Swap Control

Bit 13 controls the S6 switch and bit 12 controls the S7 switch.

00: OutA and OutB signals are as defined by OUT-MODE bits.
01: OutA = A-path as defined by OUT-MODE bits.
OutB = A-path as defined by OUT-MODE bits (rising edge delay or delay-bypassed A signal path).
10: OutA = B-path as defined by OUT-MODE bits (falling edge delay or delay-bypassed B signal path).
OutB = B-path as defined by OUT-MODE bits.
11: OutA = B-path as defined by OUT-MODE bits (falling edge delay or delay-bypassed B signal path).
OutB = A-path as defined by OUT-MODE bits (rising edge delay or delay-bypassed A signal path).

Reset type: SYSRSn

11SHDWDBFEDMODER/W0hFED Dead-Band Load Mode

0: Immediate mode. Only the active DBFED register is used. All writes/reads via the CPU directly access the active register for immediate 'FED dead-band action.'
1: Shadow mode. Operates as a double buffer. All writes via the CPU access Shadow register. Default at Reset is Immediate mode (for compatibility with legacy).

Reset type: SYSRSn

10SHDWDBREDMODER/W0hRED Dead-Band Load Mode

0: Immediate mode. Only the active DBRED register is used. All writes/reads via the CPU directly access the active register for immediate 'RED dead-band action.'
1: Shadow mode. Operates as a double buffer. All writes via the CPU access Shadow register. Default at Reset is Immediate mode (for compatibility with legacy).

Reset type: SYSRSn

9-8LOADFEDMODER/W0hActive DBFED Load from Shadow Select Mode

00: Load on Counter = 0 (CNT_eq)
01: Load on Counter = Period (PRD_eq)
10: Load on either Counter = 0, or Counter = Period
11: Freeze (no loads possible)

Note: has no effect in Immediate mode.

Reset type: SYSRSn

7-6LOADREDMODER/W0hActive DBRED Load from Shadow Select Mode

00: Load on Counter = 0 (CNT_eq)
01: Load on Counter = Period (PRD_eq)
10: Load on either Counter = 0, or Counter = Period
11: Freeze (no loads possible)

Note: has no effect in Immediate mode.

Reset type: SYSRSn

5-4IN_MODER/W0hDead-Band Input Mode Control

Bit 5 controls the S5 switch and bit 4 controls the S4 switch shown. This allows you to select the input source to the falling-edge and rising-edge delay. To produce classical dead-band waveforms the default is EPWMxA In is the source for both falling and rising-edge delays.

00: EPWMxA In (from the action-qualifier) is the source for both falling-edge and rising-edge delay.
01: EPWMxB In (from the action-qualifier) is the source for rising-edge delayed signal.
EPWMxA In (from the action-qualifier) is the source for falling-edge delayed signal.
10: EPWMxA In (from the action-qualifier) is the source for rising-edge delayed signal.
EPWMxB In (from the action-qualifier) is the source for falling-edge delayed signal.
11: EPWMxB In (from the action-qualifier) is the source for both rising-edge delay and falling-edge delayed signal.

Reset type: SYSRSn

3-2POLSELR/W0hPolarity Select Control

Bit 3 controls the S3 switch and bit 2 controls the S2 switch. This allows you to selectively invert one of the delayed signals before it is sent out of the dead-band submodule. The following descriptions correspond to classical upper/lower switch control as found in one leg of a digital motor control inverter. These assume that DBCTL[OUT_MODE] = 1,1 and DBCTL[IN_MODE] = 0x0. Other enhanced modes are also possible, but not regarded as typical usage modes.

00: Active high (AH) mode. Neither EPWMxA nor EPWMxB is inverted (default).
01: Active low complementary (ALC) mode. EPWMxA is inverted.
10: Active high complementary (AHC). EPWMxB is inverted.
11: Active low (AL) mode. Both EPWMxA and EPWMxB are inverted.

Reset type: SYSRSn

1-0OUT_MODER/W0hDead-Band Output Mode Control

Bit 1 controls the S1 switch and bit 0 controls the S0 switch.

00: DBM is fully disabled or by-passed. In this mode the POLSEL and IN-MODE bits have no effect.
01: Apath = InA (delay is by-passed for A signal path)
Bpath = FED (Falling Edge Delay in B signal path)
10: Apath = RED (Rising Edge Delay in A signal path)
Bpath = InB (delay is by-passed for B signal path)
11: DBM is fully enabled (i.e. both RED and FED active)

Reset type: SYSRSn

17.17.2.11 DBCTL2 Register (Offset = Dh) [Reset = 0000h]

DBCTL2 is shown in Figure 17-103 and described in Table 17-34.

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Dead-Band Generator Control Register 2

Figure 17-103 DBCTL2 Register
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDSHDWDBCTLMODELOADDBCTLMODE
R-0-0hR/W-0hR/W-0h
Table 17-34 DBCTL2 Register Field Descriptions
BitFieldTypeResetDescription
15-3RESERVEDR-00hReserved
2SHDWDBCTLMODER/W0hDBCTL Load Mode

0: Immediate mode - only the Active DBCTL register is used. All writes/reads via the CPU directly access the Active register.
1: Shadow mode - All writes and reads to bits [5:0] of the DBCTL register are shadowed. All other bits still access the active register.

Reset type: SYSRSn

1-0LOADDBCTLMODER/W0hActive DBCTL Load from Shadow Select Mode

00: Load on Counter = 0 (CNT_eq)
01: Load on Counter = Period (PRD_eq)
10: Load on either Counter = 0, or Counter = Period
11: Freeze (no loads possible)

Note: has no effect in Immediate mode

Reset type: SYSRSn

17.17.2.12 AQCTL Register (Offset = 10h) [Reset = 0000h]

AQCTL is shown in Figure 17-104 and described in Table 17-35.

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Action Qualifier Control Register

Figure 17-104 AQCTL Register
15141312111098
RESERVEDLDAQBSYNCLDAQASYNC
R-0-0hR/W-0hR/W-0h
76543210
RESERVEDSHDWAQBMODERESERVEDSHDWAQAMODELDAQBMODELDAQAMODE
R-0-0hR/W-0hR-0-0hR/W-0hR/W-0hR/W-0h
Table 17-35 AQCTL Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR-00hReserved
11-10LDAQBSYNCR/W0hShadow to Active AQCTLB Register Load on SYNC event

00: Shadow to Active Load of AQCTLB occurs according to LDAQBMODE
01: Shadow to Active Load of AQCTLB occurs both according to LDAQBMODE bits and when SYNC occurs.
10: Shadow to Active Load of AQCTLB occurs only when a SYNC is received.
11: Reserved

Note: This bit is valid only if AQCTL[SHDWAQBMODE] = 1.

Reset type: SYSRSn

9-8LDAQASYNCR/W0hShadow to Active AQCTLA Register Load on SYNC event

00: Shadow to Active Load of AQCTLA occurs according to LDAQAMODE
01: Shadow to Active Load of AQCTLA occurs both according to LDAQAMODE bits and when SYNC occurs.
10: Shadow to Active Load of AQCTLA occurs only when a SYNC is received.
11: Reserved

Note: This bit is valid only if AQCTL[SHDWAQAMODE] = 1.

Reset type: SYSRSn

7RESERVEDR-00hReserved
6SHDWAQBMODER/W0hAction Qualifier B Register operating mode

1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register.
0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU directly access the Active register.

Reset type: SYSRSn

5RESERVEDR-00hReserved
4SHDWAQAMODER/W0hAction Qualifier A Register operating mode

1: Shadow mode - operates as a double buffer. All writes via the CPU access Shadow register.
0: Immediate mode - only the Active action qualifier register is used. All writes/reads via the CPU directly access the Active register.

Reset type: SYSRSn

3-2LDAQBMODER/W0hActive Action Qualifier B Load from Shadow Select Mode

00: Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)
01: Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD)
10: Load on either CTR = Zero or CTR = PRD
11: Freeze (no loads possible)

Note: has no effect in Immediate mode.

Reset type: SYSRSn

1-0LDAQAMODER/W0hActive Action Qualifier A Load from Shadow Select Mode

00: Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)
01: Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD)
10: Load on either CTR = Zero or CTR = PRD
11: Freeze (no loads possible)

Note: has no effect in Immediate mode.

Reset type: SYSRSn

17.17.2.13 AQTSRCSEL Register (Offset = 11h) [Reset = 0000h]

AQTSRCSEL is shown in Figure 17-105 and described in Table 17-36.

Return to the Summary Table.

Action Qualifier Trigger Event Source Select Register

Figure 17-105 AQTSRCSEL Register
15141312111098
RESERVED
R-0-0h
76543210
T2SELT1SEL
R/W-0hR/W-0h
Table 17-36 AQTSRCSEL Register Field Descriptions
BitFieldTypeResetDescription
15-8RESERVEDR-00hReserved
7-4T2SELR/W0hT2 Event Source Select Bits

0000: DCAEVT1
0001: DCAEVT2
0010: DCBEVT1
0011: DCBEVT2
0100: TZ1
0101: TZ2
0110: TZ3
0111: EPWMxSYNCI
1000: DCEVTFILT
Others: Reserved

Reset type: SYSRSn

3-0T1SELR/W0hT1 Event Source Select Bits

0000: DCAEVT1
0001: DCAEVT2
0010: DCBEVT1
0011: DCBEVT2
0100: TZ1
0101: TZ2
0110: TZ3
0111: EPWMxSYNCI
1000: DCEVTFILT
Others: Reserved

Reset type: SYSRSn

17.17.2.14 PCCTL Register (Offset = 14h) [Reset = 0000h]

PCCTL is shown in Figure 17-106 and described in Table 17-37.

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PWM Chopper Control Register

Figure 17-106 PCCTL Register
15141312111098
RESERVEDCHPDUTY
R-0-0hR/W-0h
76543210
CHPFREQOSHTWTHCHPEN
R/W-0hR/W-0hR/W-0h
Table 17-37 PCCTL Register Field Descriptions
BitFieldTypeResetDescription
15-11RESERVEDR-00hReserved
10-8CHPDUTYR/W0hChopping Clock Duty Cycle

000: Duty = 1/8 (12.5%)
001: Duty = 2/8 (25.0%)
010: Duty = 3/8 (37.5%)
011: Duty = 4/8 (50.0%)
100: Duty = 5/8 (62.5%)
101: Duty = 6/8 (75.0%)
110: Duty = 7/8 (87.5%)
111: Reserved

Reset type: SYSRSn

7-5CHPFREQR/W0hChopping Clock Frequency

000: Divide by 1 (no prescale, = 12.5 MHz at 100 MHz TBCLK)
001: Divide by 2 (6.25 MHz at 100 MHz TBCLK)
010: Divide by 3 (4.16 MHz at 100 MHz TBCLK)
011: Divide by 4 (3.12 MHz at 100 MHz TBCLK)
100: Divide by 5 (2.50 MHz at 100 MHz TBCLK)
101: Divide by 6 (2.08 MHz at 100 MHz TBCLK)
110: Divide by 7 (1.78 MHz at 100 MHz TBCLK)
111: Divide by 8 (1.56 MHz at 100 MHz TBCLK)

Reset type: SYSRSn

4-1OSHTWTHR/W0hOne-Shot Pulse Width

0000: 1 x EPWMCLK / 8 wide ( = 80 ns at 100 MHz EPWMCLK)
0001: 2 x EPWMCLK / 8 wide ( = 160 ns at 100 MHz EPWMCLK)
0010: 3 x EPWMCLK / 8 wide ( = 240 ns at 100 MHz EPWMCLK)
0011: 4 x EPWMCLK / 8 wide ( = 320 ns at 100 MHz EPWMCLK)
0100: 5 x EPWMCLK / 8 wide ( = 400 ns at 100 MHz EPWMCLK)
0101: 6 x EPWMCLK / 8 wide ( = 480 ns at 100 MHz EPWMCLK)
0110: 7 x EPWMCLK / 8 wide ( = 560 ns at 100 MHz EPWMCLK)
0111: 8 x EPWMCLK / 8 wide ( = 640 ns at 100 MHz EPWMCLK)
1000: 9 x EPWMCLK / 8 wide ( = 720 ns at 100 MHz EPWMCLK)
1001: 10 x EPWMCLK / 8 wide ( = 800 ns at 100 MHz EPWMCLK)
1010: 11 x EPWMCLK / 8 wide ( = 880 ns at 100 MHz EPWMCLK)
1011: 12 x EPWMCLK / 8 wide ( = 960 ns at 100 MHz EPWMCLK)
1100: 13 x EPWMCLK / 8 wide ( = 1040 ns at 100 MHz EPWMCLK)
1101: 14 x EPWMCLK / 8 wide ( = 1120 ns at 100 MHz EPWMCLK)
1110: 15 x EPWMCLK / 8 wide ( = 1200 ns at 100 MHz EPWMCLK)
1111: 16 x EPWMCLK / 8 wide ( = 1280 ns at 100 MHz EPWMCLK)

Reset type: SYSRSn

0CHPENR/W0hPWM-Chopping Enable

0: Disable (bypass) PWM chopping function
1: Enable chopping function

Reset type: SYSRSn

17.17.2.15 VCAPCTL Register (Offset = 18h) [Reset = 0000h]

VCAPCTL is shown in Figure 17-107 and described in Table 17-38.

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Valley Capture Control Register

Figure 17-107 VCAPCTL Register
15141312111098
RESERVEDEDGEFILTDLYSELVDELAYDIV
R-0-0hR/W-0hR/W-0h
76543210
VDELAYDIVRESERVEDTRIGSELVCAPSTARTVCAPE
R/W-0hR-0-0hR/W-0hR-0/W1S-0hR/W-0h
Table 17-38 VCAPCTL Register Field Descriptions
BitFieldTypeResetDescription
15-11RESERVEDR-00hReserved
10EDGEFILTDLYSELR/W0hValley Switching Mode Delay Selection

0: No delay applied to the edge filter output
1: HWDELAYVAL delay applied to the edge filter output

Reset type: SYSRSn

9-7VDELAYDIVR/W0hValley Delay Mode Divide Enable

000: HWVDELVAL = SWVDELVAL
001: HWVDELVAL = VCNTVAL+SWVDELVAL
010: HWVDELVAL = VCNTVAL>>1+SWVDELVAL
011: HWVDELVAL = VCNTVAL>>2+SWVDELVAL
100: HWVDELVAL = VCNTVAL>>4+SWVDELVAL

Note: Delay value between the consecutive edge captures can optionally be divided by using these bits.

Reset type: SYSRSn

6-5RESERVEDR-00hReserved
4-2TRIGSELR/W0hStatus of Numbered of Captured Events

000: Capture sequence is triggered by software via writes to VCAPCTL[VCAPSTART].
001: Capture sequence is triggered by CNT_zero event.
010: Capture sequence is triggered by PRD_eq event.
011: Capture sequence is triggered by CNT_zero or PRD_eq event.
100: Capture sequence is triggered by DCAEVT1 event.
101: Capture sequence is triggered by DCAEVT2 event.
110: Capture sequence is triggered by DCBEVT1 event.
111: Capture sequence is triggered by DCBEVT2 event.

Note: Valley capture sequence triggered by the selected event in this register field. Once the chosen event occurs the capture sequence is armed. Event captures occur based of the event chosen in DCFCTL[SRCSEL] register.

Note: Same event may not be chosen in both DCFCTL[SRCSEL] and VCAPCTL[TRIGSEL] registers.

Note: Once the chosen event in VCAPCTL[TRIGSEL] occurs, irrespective of the current capture status, capture sequence is retriggered.

Reset type: SYSRSn

1VCAPSTARTR-0/W1S0hValley Capture Start

0: Writing a 0 has no effect
1: Trigger the capture sequence once if VCAPCTL[TRIGSEL]=0x0

Note: This bit is used to start valley capture sequence through software. VCAPCTL[TRIGSEL] has to be chosen for software trigger for this bit to have any effect. Writing of 1 will result in one capture sequence trigger.

Reset type: SYSRSn

0VCAPER/W0hValley Capture Enable/Disable

0: Disabled
1: Enabled

Reset type: SYSRSn

17.17.2.16 VCNTCFG Register (Offset = 19h) [Reset = 0000h]

VCNTCFG is shown in Figure 17-108 and described in Table 17-39.

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Valley Counter Config Register

Figure 17-108 VCNTCFG Register
15141312111098
STOPEDGESTSRESERVEDSTOPEDGE
R-0hR-0-0hR/W-0h
76543210
STARTEDGESTSRESERVEDSTARTEDGE
R-0hR-0-0hR/W-0h
Table 17-39 VCNTCFG Register Field Descriptions
BitFieldTypeResetDescription
15STOPEDGESTSR0hStop Edge Status Bit

0: Stop edge has not occurred
1: Stop edge occurred

Note: This bit is set only after the trigger sequence is armed (upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]) and STOPEDGE occurs.

Note:This bit is reset by the occurrence of the trigger pulse selected through VCAPCTL[TRIGSEL]

Reset type: SYSRSn

14-12RESERVEDR-00hReserved
11-8STOPEDGER/W0hCounter Stop Edge Selection

Once the counter operation is armed, upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit field. Stop counting on occurrence of:

0000: Do not stop
0001
1st edge
0010: 2nd edge
0011: 3rd edge
...
1,1,1,1: 15th edge

Reset type: SYSRSn

7STARTEDGESTSR0hStart Edge Status Bit

0: Start edge has not occurred
1: Start edge occurred

Note: This bit is set only after the trigger sequence is armed (upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]) and STARTEDGE occurs.

Note:This bit is reset by the occurrence of the trigger pulse selected through VCAPCTL[TRIGSEL]

Reset type: SYSRSn

6-4RESERVEDR-00hReserved
3-0STARTEDGER/W0hCounter Start Edge Selection

Once the counter operation is armed, upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit field. Start counting on occurrence of

0000: Do not start
0001: 1st edge
0010: 2nd edge
0011: 3rd edge
...
1111: 15th edge

Reset type: SYSRSn

17.17.2.17 HRCNFG Register (Offset = 20h) [Reset = 0000h]

HRCNFG is shown in Figure 17-109 and described in Table 17-40.

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HRPWM Configuration Register

This register is only accessible on EPWM modules with HRPWM capabilities.

Figure 17-109 HRCNFG Register
15141312111098
RESERVEDRESERVEDHRLOADBCTLMODEBEDGMODEB
R/W-0hR-0-0hR/W-0hR/W-0hR/W-0h
76543210
SWAPABAUTOCONVSELOUTBHRLOADCTLMODEEDGMODE
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 17-40 HRCNFG Register Field Descriptions
BitFieldTypeResetDescription
15-14RESERVEDR/W0hReserved
13RESERVEDR-00hReserved
12-11HRLOADBR/W0hShadow Mode Bit

Selects the time event that loads the CMPBHR shadow value into the active register.

00: Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)
01: Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD)
10: Load on either CTR = Zero or CTR = PRD
11: Reserved

Reset type: SYSRSn

10CTLMODEBR/W0hControl Mode Bits

Selects the register (CMP/TBPRD or TBPHS) that controls the MEP:

0: CMPBHR(8) or TBPRDHR(8) Register controls the edge position (i.e., this is duty or period control mode). (Default on Reset)
1: TBPHSHR(8) Register controls the edge position (i.e., this is phase control mode).

Reset type: SYSRSn

9-8EDGMODEBR/W0hEdge Mode Bits

Selects the edge of the PWM that is controlled by the micro-edge position (MEP) logic:

00: HRPWM capability is disabled (default on reset)
01: MEP control of rising edge (CMPBHR)
10: MEP control of falling edge (CMPBHR)
11: MEP control of both edges (TBPHSHR or TBPRDHR)

Reset type: SYSRSn

7SWAPABR/W0hSwap ePWM A & B Output Signals

This bit enables the swapping of the A & B signal outputs. The selection is as follows:

0: ePWMxA and ePWMxB outputs are unchanged.
1: ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA output.

Reset type: SYSRSn

6AUTOCONVR/W0hAuto Convert Delay Line Value

Selects whether the fractional duty cycle/period/phase in the CMPAHR/TBPRDHR/TBPHSHR register is automatically scaled by the MEP scale factor in the HRMSTEP register or manually scaled by calculations in application software. The SFO library function automatically updates the HRMSTEP register with the appropriate MEP scale factor.

0: Automatic HRMSTEP scaling is disabled.
1: Automatic HRMSTEP scaling is enabled.

If application software is manually scaling the fractional duty cycle, or phase (i.e. software sets CMPAHR = (fraction(PWMduty * PWMperiod) * MEP Scale Factor)<<8 + 0x080 for duty cycle), then this mode must be disabled.

Reset type: SYSRSn

5SELOUTBR/W0hEPWMxB Output Select Bit

This bit selects which signal is output on the ePWMxB channel output.
The inversion will take the high resolution mode into account and the inverted signal will contain any high resolution modification. The inversion takes place as the last step in modifying the ePWMxB signal.

0: ePWMxB output is normal.
1: ePWMxB output is inverted version of ePWMxA signal.

Reset type: SYSRSn

4-3HRLOADR/W0hShadow Mode Bit

Selects the time event that loads the CMPAHR shadow value into the active register.

00: Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)
01: Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD)
10: Load on either CTR = Zero or CTR = PRD
11: Reserved

Reset type: SYSRSn

2CTLMODER/W0hControl Mode Bits

Selects the register (CMP/TBPRD or TBPHS) that controls the MEP:

0: CMPAHR(8) or TBPRDHR(8) Register controls the edge position (i.e., this is duty or period control mode). (Default on Reset)
1: TBPHSHR(8) Register controls the edge position (i.e., this is phase control mode).

Reset type: SYSRSn

1-0EDGMODER/W0hEdge Mode Bits

Selects the edge of the PWM that is controlled by the micro-edge position (MEP) logic:

00: HRPWM capability is disabled (default on reset)
01: MEP control of rising edge (CMPAHR)
10: MEP control of falling edge (CMPAHR)
11: MEP control of both edges (TBPHSHR or TBPRDHR)

Reset type: SYSRSn

17.17.2.18 HRPWR Register (Offset = 21h) [Reset = 0000h]

HRPWR is shown in Figure 17-110 and described in Table 17-41.

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HRPWM Power Register

This register is only accessible on EPWM modules with HRPWM capabilities.

Figure 17-110 HRPWR Register
15141312111098
CALPWRONRESERVEDRESERVED
R/W-0hR-0-0hR/W-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R/W-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0h
Table 17-41 HRPWR Register Field Descriptions
BitFieldTypeResetDescription
15CALPWRONR/W0hMEP Calibration Power Bits (only available on ePWM1)

0: Disables MEP calibration logic in the HRPWM and reduces power consumption.
1: Enables MEP calibration logic

Reset type: SYSRSn

14-10RESERVEDR-00hReserved
9-6RESERVEDR/W0hReserved
5RESERVEDR/W0hReserved
4RESERVEDR0hReserved
3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1-0RESERVEDR/W0hReserved

17.17.2.19 HRMSTEP Register (Offset = 26h) [Reset = 0000h]

HRMSTEP is shown in Figure 17-111 and described in Table 17-42.

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HRPWM MEP Step Register

This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values.

Figure 17-111 HRMSTEP Register
15141312111098
RESERVED
R-0-0h
76543210
HRMSTEP
R/W-0h
Table 17-42 HRMSTEP Register Field Descriptions
BitFieldTypeResetDescription
15-8RESERVEDR-00hReserved
7-0HRMSTEPR/W0hHigh Resolution MEP Step

When auto-conversion is enabled (HRCNFG[AUTOCONV] = 1), This 8-bit field contains the MEP_ScaleFactor (number of MEP steps per coarse steps) used by the hardware to automatically convert the value in the CMPAHR, CMPBHR, DBFEDHR, DBREDHR , TBPHSHR, or TBPRDHR register to a scaled micro-edge delay on the high-resolution ePWM output. The value in this register is written by the SFO calibration software at the end of each calibration run.

Reset type: SYSRSn

17.17.2.20 HRCNFG2 Register (Offset = 27h) [Reset = 0000h]

HRCNFG2 is shown in Figure 17-112 and described in Table 17-43.

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HRPWM Configuration 2 Register

This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values.

Figure 17-112 HRCNFG2 Register
15141312111098
RESERVEDRESERVEDRESERVED
R/W-0hR-0/W1S-0hR-0-0h
76543210
RESERVEDCTLMODEDBFEDCTLMODEDBREDEDGMODEDB
R-0-0hR/W-0hR/W-0hR/W-0h
Table 17-43 HRCNFG2 Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR/W0hReserved
14RESERVEDR-0/W1S0hReserved
13-6RESERVEDR-00hReserved
5-4CTLMODEDBFEDR/W0hShadow Mode Bit - selection should match DBCTL[LOADFEDMODE]

Selects the time event that loads the DBFEDHR shadow value into the active register.

00 Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)
01 Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD)
10 Load on either CTR = Zero or CTR = PRD
11 Reserved

Reset type: SYSRSn

3-2CTLMODEDBREDR/W0hShadow Mode Bit - selection should match DBCTL[LOADREDMODE]

Selects the time event that loads the DBREDHR shadow value into the active register.

00 Load on CTR = Zero: Time-base counter equal to zero (TBCTR = 0x0000)
01 Load on CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD)
10 Load on either CTR = Zero or CTR = PRD
11 Reserved

Reset type: SYSRSn

1-0EDGMODEDBR/W0hEdge Mode Bits

Selects the edge of the PWM that is controlled by the micro-edge position (MEP) logic:

00 HRPWM capability is disabled (default on reset)
01 MEP control of rising edge (DBREDHR)
10 MEP control of falling edge (DBFEDHR)
11 MEP control of both edges (rising edge of DBREDHR or falling edge of DBFEDHR )

Reset type: SYSRSn

17.17.2.21 HRPCTL Register (Offset = 2Dh) [Reset = 0000h]

HRPCTL is shown in Figure 17-113 and described in Table 17-44.

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High Resolution Period Control Register

This register is only accessible on EPWM modules with HRPWM capabilities.

Figure 17-113 HRPCTL Register
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDPWMSYNCSELXRESERVEDTBPHSHRLOADEPWMSYNCSELHRPE
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 17-44 HRPCTL Register Field Descriptions
BitFieldTypeResetDescription
15-7RESERVEDR-00hReserved
6-4PWMSYNCSELXR/W0hExtended selection bits for EPWMSYNCPER

000: EPWMSYNCPER is defined by PWMSYNCSEL - > default condition (compatible with previous EPWM versions)
001: Reserved
010: Reserved
011: Reserved
100: CTR = CMPC, Count direction Up
101: CTR = CMPC, Count direction Down
110: CTR = CMPD, Count direction Up
111: CTR = CMPD, Count direction Down

Reset type: SYSRSn

3RESERVEDR/W0hReserved
2TBPHSHRLOADER/W0hTBPHSHR Load Enable

This bit allows you to synchronize ePWM modules with a high-resolution phase on a SYNCIN, TBCTL[SWFSYNC] or digital compare event. This allows for multiple ePWM modules operating at the same frequency to be phase aligned with high-resolution.

0: Disables synchronization of high-resolution phase on a SYNCIN, TBCTL[SWFSYNC] or digital compare event:
1: Synchronize the high-resolution phase on a SYNCIN, TBCTL[SWFSYNC] or digital comparator synchronization event. The phase is synchronized using the contents of the high-resolution phase TBPHSHR register. The TBCTL[PHSEN] bit which enables the loading of the TBCTR register with TBPHS register value on a SYNCIN or TBCTL[SWFSYNC] event works independently. However, users need to enable this bit also if they want to control phase in conjunction with the high-resolution period feature.

This bit and the TBCTL[PHSEN] bit must be set to 1 when high-resolution period is enabled for up-down count mode even if TBPHSHR = 0x0000. This bit does not need to be set when only high-resolution duty is enabled.

Reset type: SYSRSn

1PWMSYNCSELR/W0hPWMSYNC Source Select Bit: This bit selects the source for the EPWMSYNCPER signal that goes to the CMPSS and GPDAC:

0 CTR = PRD: Time-base counter equal to period (TBCTR = TBPRD)
1 CTR = zero: Time-base counter equal to zero (TBCTR = 0x00)

Reset type: SYSRSn

0HRPER/W0hHigh Resolution Period Enable Bit

0: High resolution period feature disabled. In this mode the ePWM behaves as a Type 4 ePWM.
1: High resolution period enabled. In this mode the HRPWM module can control high-resolution of both the duty and frequency. When high-resolution period is enabled, TBCTL[CTRMODE] = 0,1 (down-count mode) is not supported.

Reset type: SYSRSn

17.17.2.22 TRREM Register (Offset = 2Eh) [Reset = 0000h]

TRREM is shown in Figure 17-114 and described in Table 17-45.

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HRPWM High Resolution Remainder Register

This register is only accessible on EPWM modules with HRPWM capabilities.

Figure 17-114 TRREM Register
15141312111098
RESERVEDTRREM
R-0-0hR/W-0h
76543210
TRREM
R/W-0h
Table 17-45 TRREM Register Field Descriptions
BitFieldTypeResetDescription
15-11RESERVEDR-00hReserved
10-0TRREMR/W0hHRPWM Remainder Bits: This 11-bit value keeps track of the remainder portion of the HRPWM algorithm calculations.
This value keeps track of the remainder portion of the HRPWM hardware calculations.
Notes:
1. The lower 8-bits of the TRREM register can be automatically initialized with the TBPHSHR value on a SYNCIN or TBCTL[SWFSYNC] event or DC event (if enabled). The user can also write a value with the CPU.
2. Priority of TRREM register updates:
Sync (software or hardware) TBPHSHR copied to TRREM : Highest Priority
HRPWM Hardware (updates TRREM register): Next priority
CPU Write To TRREM Register: Lowest Priority
3. Bit 10 of TRREM register is not used in asymmetrical mode. This bit can be forced to zero.
TRREM will be initialized to 0x0 and 0x100 in Up and Up-down modes respectively.
Asymmetrical Mode:
TRREM[7:0] = TBPHSHR[15:8]
TRREM[10,9,8] = 0,0,0
Symmetrical Mode:
TRREM[7:0] = TBPHSHR[15:8]
TRREM[10,9,8] = 0,0,1

Reset type: SYSRSn

17.17.2.23 GLDCTL Register (Offset = 34h) [Reset = 0000h]

GLDCTL is shown in Figure 17-115 and described in Table 17-46.

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Global PWM Load Control Register

Figure 17-115 GLDCTL Register
15141312111098
RESERVEDGLDCNTGLDPRD
R-0-0hR-0hR/W-0h
76543210
GLDPRDRESERVEDOSHTMODEGLDMODEGLD
R/W-0hR-0-0hR/W-0hR/W-0hR/W-0h
Table 17-46 GLDCTL Register Field Descriptions
BitFieldTypeResetDescription
15-13RESERVEDR-00hReserved
12-10GLDCNTR0hGlobal Load Strobe Counter Register

These bits indicate how many selected events have occurred:

000: No events
001: 1 event
010: 2 events
011: 3 events
100: 4 events
101: 5 events
110: 6 events
111: 7 events

Reset type: SYSRSn

9-7GLDPRDR/W0hGlobal Load Strobe Period Select Register

These bits select how many selected events need to occur before a load strobe is generated

000: Disable counter
001: Generate strobe on GLDCNT = 001 (1st event)
010: Generate strobe on GLDCNT = 010 (2nd event)
011: Generate strobe on GLDCNT = 011 (3rd event)
100: Generate strobe on GLDCNT = 011 (4th event)
101: Generate strobe on GLDCNT = 001 (5th event)
110: Generate strobe on GLDCNT = 010 (6th event)
111: Generate strobe on GLDCNT = 011 (7th event)

Reset type: SYSRSn

6RESERVEDR-00hReserved
5OSHTMODER/W0hOne Shot Load Mode Control Bit

0: One shot load mode is disabled and shadow to active loading happens continuously on all the chosen load strobes.
1: One shot mode is active. All load strobes are blocked until GLDCTL2[OSHTLD] is written with 1.

Note: One Shot mode can only be used with global shadow to active load mode enabled (GLDCTL[GLD]=1)

Reset type: SYSRSn

4-1GLDMODER/W0hGlobal Load Pulse selection for Shadow to Active Mode Reloads

0000: Load on Counter = 0 (CNT_ZRO)
0001: Load on Counter = Period (PRD_EQ)
0010: Load on either Counter = 0, or Counter = Period
0011: Load on SYNCEVT - this is logical OR of DCAEVT1.sync, DCBEVT1.sync, EPWMxSYNCI and TBCTL[SWFSYNC]
0100: Load on SYNCEVT or CNT_ZRO
0101: Load on SYNCEVT or PRD_EQ
0110: Load on SYNCEVT or CNT_ZRO or PRD_EQ
1000: Reserved
...
1110: Reserved
1111: Load on GLDCTL2[GFRCLD] write

Reset type: SYSRSn

0GLDR/W0hGlobal Shadow to Active Load Event Control

0: Shadow to active reload for all shadowed registers happens as per the individual reload control bits specified (Compatible with previous EPWM versions).

1: When set, all the shadow to active reload events are defined by GLDMODE bits in GLDCTL register. All the shadow registers use same reload pulse from shadow to active reloading. Individual LOADMODE bits are ignored.

Reset type: SYSRSn

17.17.2.24 GLDCFG Register (Offset = 35h) [Reset = 0000h]

GLDCFG is shown in Figure 17-116 and described in Table 17-47.

Return to the Summary Table.

Global PWM Load Config Register

Figure 17-116 GLDCFG Register
15141312111098
RESERVEDAQCSFRCAQCTLB_AQCTLB2AQCTLA_AQCTLA2
R-0-0hR/W-0hR/W-0hR/W-0h
76543210
DBCTLDBFED_DBFEDHRDBRED_DBREDHRCMPDCMPCCMPB_CMPBHRCMPA_CMPAHRTBPRD_TBPRDHR
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 17-47 GLDCFG Register Field Descriptions
BitFieldTypeResetDescription
15-11RESERVEDR-00hReserved
10AQCSFRCR/W0hGlobal load event configuration for AQCSFRC

0: Registers use local reload configuration even if GLDCTL(GLD)=1 (reload is compatible with previous EPWMs)
1: Registers use global load configuration if this bit is set and GLDCTL(GLD)=1

Reset type: SYSRSn

9AQCTLB_AQCTLB2R/W0hGlobal load event configuration for AQCTLB_AQCTLB2

0: Registers use local reload configuration even if GLDCTL(GLD)=1 (reload is compatible with previous EPWMs)
1: Registers use global load configuration if this bit is set and GLDCTL(GLD)=1

Reset type: SYSRSn

8AQCTLA_AQCTLA2R/W0hGlobal load event configuration for AQCTLA_AQCTLA2

0: Registers use local reload configuration even if GLDCTL(GLD)=1 (reload is compatible with previous EPWMs)
1: Registers use global load configuration if this bit is set and GLDCTL(GLD)=1

Reset type: SYSRSn

7DBCTLR/W0hGlobal load event configuration for DBCTL

0: Registers use local reload configuration even if GLDCTL(GLD)=1 (reload is compatible with previous EPWMs)
1: Registers use global load configuration if this bit is set and GLDCTL(GLD)=1

Reset type: SYSRSn

6DBFED_DBFEDHRR/W0hGlobal load event configuration for DBFED_DBFEDHR

0: Registers use local reload configuration even if GLDCTL(GLD)=1 (reload is compatible with previous EPWMs)
1: Registers use global load configuration if this bit is set and GLDCTL(GLD)=1

Reset type: SYSRSn

5DBRED_DBREDHRR/W0hGlobal load event configuration for DBRED_DBREDHR

0: Registers use local reload configuration even if GLDCTL(GLD)=1 (reload is compatible with previous EPWMs)
1: Registers use global load configuration if this bit is set and GLDCTL(GLD)=1

Reset type: SYSRSn

4CMPDR/W0hGlobal load event configuration for CMPD

0: Registers use local reload configuration even if GLDCTL(GLD)=1 (reload is compatible with previous EPWMs)
1: Registers use global load configuration if this bit is set and GLDCTL(GLD)=1

Reset type: SYSRSn

3CMPCR/W0hGlobal load event configuration for CMPC

0: Registers use local reload configuration even if GLDCTL(GLD)=1 (reload is compatible with previous EPWMs)
1: Registers use global load configuration if this bit is set and GLDCTL(GLD)=1

Reset type: SYSRSn

2CMPB_CMPBHRR/W0hGlobal load event configuration for CMPB_CMPBHR

0: Registers use local reload configuration even if GLDCTL(GLD)=1 (reload is compatible with previous EPWMs)
1: Registers use global load configuration if this bit is set and GLDCTL(GLD)=1

Reset type: SYSRSn

1CMPA_CMPAHRR/W0hGlobal load event configuration for CMPA_CMPAHR

0: Registers use local reload configuration even if GLDCTL(GLD)=1 (reload is compatible with previous EPWMs)
1: Registers use global load configuration if this bit is set and GLDCTL(GLD)=1

Reset type: SYSRSn

0TBPRD_TBPRDHRR/W0hGlobal load event configuration for TBPRD_TBPRDHR

0: Registers use local reload configuration even if GLDCTL(GLD)=1 (reload is compatible with previous EPWMs)
1: Registers use global load configuration if this bit is set and GLDCTL(GLD)=1

Reset type: SYSRSn

EPWMXLINK is shown in Figure 17-117 and described in Table 17-48.

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EPWMx Link Register

This register controls which EPWMs are linked to other EPWM modules. The default reset value will vary for each module. The reset value will link each EPWM module to itself to prevent unintentional linking of modules.

Figure 17-117 EPWMXLINK Register
Table 17-48 EPWMXLINK Register Field Descriptions

17.17.2.26 AQCTLA Register (Offset = 40h) [Reset = 0000h]

AQCTLA is shown in Figure 17-118 and described in Table 17-49.

Return to the Summary Table.

Action Qualifier Control Register For Output A

Figure 17-118 AQCTLA Register
15141312111098
RESERVEDCBDCBU
R-0-0hR/W-0hR/W-0h
76543210
CADCAUPRDZRO
R/W-0hR/W-0hR/W-0hR/W-0h
Table 17-49 AQCTLA Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR-00hReserved
11-10CBDR/W0hAction When TBCTR = CMPB on Down Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force EPWMxA output low.
10: Set: force EPWMxA output high.
11: Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

9-8CBUR/W0hAction When TBCTR = CMPB on Up Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force EPWMxA output low.
10: Set: force EPWMxA output high.
11: Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

7-6CADR/W0hAction When TBCTR = CMPA on Down Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force EPWMxA output low.
10: Set: force EPWMxA output high.
11: Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

5-4CAUR/W0hAction When TBCTR = CMPA on Up Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force EPWMxA output low.
10: Set: force EPWMxA output high.
11: Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

3-2PRDR/W0hAction When TBCTR = TBPRD

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force EPWMxA output low.
10: Set: force EPWMxA output high.
11: Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

1-0ZROR/W0hAction When TBCTR = 0

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force EPWMxA output low.
10: Set: force EPWMxA output high.
11: Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

17.17.2.27 AQCTLA2 Register (Offset = 41h) [Reset = 0000h]

AQCTLA2 is shown in Figure 17-119 and described in Table 17-50.

Return to the Summary Table.

Additional Action Qualifier Control Register For Output A

Figure 17-119 AQCTLA2 Register
15141312111098
RESERVED
R-0-0h
76543210
T2DT2UT1DT1U
R/W-0hR/W-0hR/W-0hR/W-0h
Table 17-50 AQCTLA2 Register Field Descriptions
BitFieldTypeResetDescription
15-8RESERVEDR-00hReserved
7-6T2DR/W0hAction when event occurs on T2 in DOWN-Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force EPWMxA output low.
10: Set: force EPWMxA output high.
11: Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

5-4T2UR/W0hAction when event occurs on T2 in UP-Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force EPWMxA output low.
10: Set: force EPWMxA output high.
11: Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

3-2T1DR/W0hAction when event occurs on T1 in DOWN-Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force EPWMxA output low.
10: Set: force EPWMxA output high.
11: Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

1-0T1UR/W0hAction when event occurs on T1 in UP-Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force EPWMxA output low.
10: Set: force EPWMxA output high.
11: Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

17.17.2.28 AQCTLB Register (Offset = 42h) [Reset = 0000h]

AQCTLB is shown in Figure 17-120 and described in Table 17-51.

Return to the Summary Table.

Action Qualifier Control Register For Output B

Figure 17-120 AQCTLB Register
15141312111098
RESERVEDCBDCBU
R-0-0hR/W-0hR/W-0h
76543210
CADCAUPRDZRO
R/W-0hR/W-0hR/W-0hR/W-0h
Table 17-51 AQCTLB Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR-00hReserved
11-10CBDR/W0hAction When TBCTR = CMPB on Down Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force EPWMxB output low.
10: Set: force EPWMxB output high.
11: Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

9-8CBUR/W0hAction When TBCTR = CMPB on Up Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force EPWMxB output low.
10: Set: force EPWMxB output high.
11: Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

7-6CADR/W0hAction When TBCTR = CMPA on Down Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force EPWMxB output low.
10: Set: force EPWMxB output high.
11: Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

5-4CAUR/W0hAction When TBCTR = CMPA on Up Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force EPWMxB output low.
10: Set: force EPWMxB output high.
11: Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

3-2PRDR/W0hAction When TBCTR = TBPRD

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force EPWMxB output low.
10: Set: force EPWMxB output high.
11: Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

1-0ZROR/W0hAction When TBCTR = 0

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force EPWMxB output low.
10: Set: force EPWMxB output high.
11: Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

17.17.2.29 AQCTLB2 Register (Offset = 43h) [Reset = 0000h]

AQCTLB2 is shown in Figure 17-121 and described in Table 17-52.

Return to the Summary Table.

Additional Action Qualifier Control Register For Output B

Figure 17-121 AQCTLB2 Register
15141312111098
RESERVED
R-0-0h
76543210
T2DT2UT1DT1U
R/W-0hR/W-0hR/W-0hR/W-0h
Table 17-52 AQCTLB2 Register Field Descriptions
BitFieldTypeResetDescription
15-8RESERVEDR-00hReserved
7-6T2DR/W0hAction when event occurs on T2 in DOWN-Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force EPWMxB output low.
10: Set: force EPWMxB output high.
11: Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

5-4T2UR/W0hAction when event occurs on T2 in UP-Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force EPWMxB output low.
10: Set: force EPWMxB output high.
11: Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

3-2T1DR/W0hAction when event occurs on T1 in DOWN-Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force EPWMxB output low.
10: Set: force EPWMxB output high.
11: Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

1-0T1UR/W0hAction when event occurs on T1 in UP-Count

Note: By definition, in count up-down mode when the counter equals 0 the direction is defined as 1 or counting up.

00: Do nothing (action disabled)
01: Clear: force EPWMxB output low.
10: Set: force EPWMxB output high.
11: Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low.

Reset type: SYSRSn

17.17.2.30 AQSFRC Register (Offset = 47h) [Reset = 0000h]

AQSFRC is shown in Figure 17-122 and described in Table 17-53.

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Action Qualifier Software Force Register

Figure 17-122 AQSFRC Register
15141312111098
RESERVED
R-0-0h
76543210
RLDCSFOTSFBACTSFBOTSFAACTSFA
R/W-0hR-0/W1S-0hR/W-0hR-0/W1S-0hR/W-0h
Table 17-53 AQSFRC Register Field Descriptions
BitFieldTypeResetDescription
15-8RESERVEDR-00hReserved
7-6RLDCSFR/W0hAQCSFRC Active Register Reload From Shadow Options

00: Load on time-base counter equals zero
01: Load on time-base counter equals period
10: Load on time-base counter equals zero or counter equals period
11: Load immediately (the active register is directly accessed by the CPU and is not loaded from the shadow register).

Reset type: SYSRSn

5OTSFBR-0/W1S0hOne-Time Software Forced Event on Output B

0: Writing a 0 (zero) has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete (i.e., a forced event is initiated.). This is a one-shot forced event. It can be overridden by another subsequent event on output B.
1: Initiates a single software forced event

Reset type: SYSRSn

4-3ACTSFBR/W0hAction When One-Time Software Force B is Invoked

00: Does nothing (action disabled)
01: Clear (low)
10: Set (high)
11: Toggle (Low -> High, High -> Low)

Note: This action is not qualified by counter direction (CNT_dir)

Reset type: SYSRSn

2OTSFAR-0/W1S0hOne-Time Software Forced Event on Output A

0: Writing a 0 (zero) has no effect. Always reads back a 0. This bit is auto cleared once a write to this register is complete ( i.e., a forced event is initiated). This is a one-shot forced event. It can be overridden by another subsequent event on output A.
1: Initiates a single software forced event

Reset type: SYSRSn

1-0ACTSFAR/W0hAction When One-Time Software Force A Is Invoked

00: Does nothing (action disabled)
01: Clear (low)
10: Set (high)
11: Toggle (Low -> High, High -> Low)

Note: This action is not qualified by counter direction (CNT_dir)

Reset type: SYSRSn

17.17.2.31 AQCSFRC Register (Offset = 49h) [Reset = 0000h]

AQCSFRC is shown in Figure 17-123 and described in Table 17-54.

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Action Qualifier Continuous S/W Force Register

Figure 17-123 AQCSFRC Register
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDCSFBCSFA
R-0-0hR/W-0hR/W-0h
Table 17-54 AQCSFRC Register Field Descriptions
BitFieldTypeResetDescription
15-4RESERVEDR-00hReserved
3-2CSFBR/W0hContinuous Software Force on Output B

In immediate mode, a continuous force takes effect on the next TBCLK edge. In shadow mode, a continuous force takes effect on the next TBCLK edge after a shadow load into the active register. To configure shadow mode, use AQSFRC[RLDCSF].

00: Software forcing is disabled and has no effect
01: Forces a continuous low on output B
10: Forces a continuous high on output B
11: Software forcing is disabled and has no effect

Reset type: SYSRSn

1-0CSFAR/W0hContinuous Software Force on Output A

In immediate mode, a continuous force takes effect on the next TBCLK edge. In shadow mode, a continuous force takes effect on the next TBCLK edge after a shadow load into the active register.

00: Software forcing is disabled and has no effect
01: Forces a continuous low on output A
10: Forces a continuous high on output A
11: Software forcing is disabled and has no effect

Reset type: SYSRSn

17.17.2.32 DBREDHR Register (Offset = 50h) [Reset = 0000h]

DBREDHR is shown in Figure 17-124 and described in Table 17-55.

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Dead-Band Generator Rising Edge Delay High Resolution Mirror Register

Figure 17-124 DBREDHR Register
15141312111098
DBREDHRRESERVED
R/W-0hR-0h
76543210
RESERVEDRESERVED
R-0hR-0h
Table 17-55 DBREDHR Register Field Descriptions
BitFieldTypeResetDescription
15-9DBREDHRR/W0hDead Band Rising Edge Delay High Resolution Bits

Reset type: SYSRSn

8RESERVEDR0hReserved
7-1RESERVEDR0hReserved
0RESERVEDR0hReserved

17.17.2.33 DBRED Register (Offset = 51h) [Reset = 0000h]

DBRED is shown in Figure 17-125 and described in Table 17-56.

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Dead-Band Generator Rising Edge Delay High Resolution Mirror Register

Figure 17-125 DBRED Register
15141312111098
RESERVEDDBRED
R-0hR/W-0h
76543210
DBRED
R/W-0h
Table 17-56 DBRED Register Field Descriptions
BitFieldTypeResetDescription
15-14RESERVEDR0hReserved
13-0DBREDR/W0hRising edge delay value

Reset type: SYSRSn

17.17.2.34 DBFEDHR Register (Offset = 52h) [Reset = 0000h]

DBFEDHR is shown in Figure 17-126 and described in Table 17-57.

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Dead-Band Generator Falling Edge Delay High Resolution Register

Figure 17-126 DBFEDHR Register
15141312111098
DBFEDHRRESERVED
R/W-0hR-0h
76543210
RESERVEDRESERVED
R-0hR-0h
Table 17-57 DBFEDHR Register Field Descriptions
BitFieldTypeResetDescription
15-9DBFEDHRR/W0hDead Band Falling Edge Delay High Resolution Bits

Reset type: SYSRSn

8RESERVEDR0hReserved
7-1RESERVEDR0hReserved
0RESERVEDR0hReserved

17.17.2.35 DBFED Register (Offset = 53h) [Reset = 0000h]

DBFED is shown in Figure 17-127 and described in Table 17-58.

Return to the Summary Table.

Dead-Band Generator Falling Edge Delay Count Register

Figure 17-127 DBFED Register
15141312111098
RESERVEDDBFED
R-0hR/W-0h
76543210
DBFED
R/W-0h
Table 17-58 DBFED Register Field Descriptions
BitFieldTypeResetDescription
15-14RESERVEDR0hReserved
13-0DBFEDR/W0hFalling Edge Delay Count

14-bit counter

Reset type: SYSRSn

17.17.2.36 TBPHS Register (Offset = 60h) [Reset = 00000000h]

TBPHS is shown in Figure 17-128 and described in Table 17-59.

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Time Base Phase High

Figure 17-128 TBPHS Register
313029282726252423222120191817161514131211109876543210
TBPHSTBPHSHR
R/W-0hR/W-0h
Table 17-59 TBPHS Register Field Descriptions
BitFieldTypeResetDescription
31-16TBPHSR/W0hPhase Offset Register

These bits set time-base counter phase of the selected ePWM relative to the time-base that is supplying the synchronization input signal.

- If TBCTL[PHSEN] = 0, then the synchronization event is ignored and the time-base counter is not loaded with the phase.
- If TBCTL[PHSEN] = 1, then the time-base counter (TBCTR) will be loaded with the phase (TBPHS) when a synchronization event occurs. The synchronization event can be initiated by the input synchronization signal (EPWMxSYNCI) or by a software forced synchronization.

Reset type: SYSRSn

15-0TBPHSHRR/W0hPhase Offset (High Resolution) Register.
TBPHSHR must not be used. Instead TRREM (HRPWM remainder register) must be used to mimic the functionality of TBPHSHR.

The lower 8 bits in this register are ignored - writes are ignored and reads return zero

Reset type: SYSRSn

17.17.2.37 TBPRDHR Register (Offset = 62h) [Reset = 0000h]

TBPRDHR is shown in Figure 17-129 and described in Table 17-60.

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Time Base Period High Resolution Register

Figure 17-129 TBPRDHR Register
15141312111098
TBPRDHR
R/W-0h
76543210
TBPRDHR
R/W-0h
Table 17-60 TBPRDHR Register Field Descriptions
BitFieldTypeResetDescription
15-0TBPRDHRR/W0hPeriod High Resolution Bits

The upper 8-bits contain the high-resolution portion of the period value. The TBPRDHR register is not affected by the TBCTL[PRDLD] bit. Reads from this register always reflect the shadow register. Likewise writes are also to the shadow register. The TBPRDHR register is only used when the high resolution period feature is enabled. This register is only available with ePWM modules which support high-resolution period control.

The lower 8 bits in this register are ignored - writes are ignored and reads return zero

Reset type: SYSRSn

17.17.2.38 TBPRD Register (Offset = 63h) [Reset = 0000h]

TBPRD is shown in Figure 17-130 and described in Table 17-61.

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Time Base Period Register

Figure 17-130 TBPRD Register
15141312111098
TBPRD
R/W-0h
76543210
TBPRD
R/W-0h
Table 17-61 TBPRD Register Field Descriptions
BitFieldTypeResetDescription
15-0TBPRDR/W0hTime Base Period Register

These bits determine the period of the time-base counter. This sets the PWM frequency. Shadowing of this register is enabled and disabled by the TBCTL[PRDLD] bit. By default this register is shadowed.
- If TBCTL[PRDLD] = 0, then the shadow is enabled and any write or read will automatically go to the shadow register. In this case, the active register will be loaded from the shadow register when the time-base counter equals zero.
- If TBCTL[PRDLD] = 1, then the shadow is disabled and any write or read will go directly to the active register, that is the register actively controlling the hardware.
- The active and shadow registers share the same memory map address.

Reset type: SYSRSn

17.17.2.39 CMPA Register (Offset = 6Ah) [Reset = 00000000h]

CMPA is shown in Figure 17-131 and described in Table 17-62.

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Counter Compare A Register

Figure 17-131 CMPA Register
313029282726252423222120191817161514131211109876543210
CMPACMPAHR
R/W-0hR/W-0h
Table 17-62 CMPA Register Field Descriptions
BitFieldTypeResetDescription
31-16CMPAR/W0hCompare A Register

The value in the active CMPA register is continuously compared to the time-base counter (TBCTR). When the values are equal, the counter-compare module generates a 'time-base counter equal to counter compare A' event. This event is sent to the action-qualifier where it is qualified and converted it into one or more actions. These actions can be applied to either the EPWMxA or the EPWMxB output depending on the configuration of the AQCTLA and AQCTLB registers. The actions that can be defined in the AQCTLA and AQCTLB registers include:

- Do nothing
the event is ignored.
- Clear: Pull the EPWMxA and/or EPWMxB signal low
- Set: Pull the EPWMxA and/or EPWMxB signal high
- Toggle the EPWMxA and/or EPWMxB signal

Shadowing of this register is enabled and disabled by the CMPCTL[SHDWAMODE] bit. By default this register is shadowed.
- If CMPCTL[SHDWAMODE] = 0, then the shadow is enabled and any write or read will automatically go to the shadow register. In this case, the CMPCTL[LOADAMODE] bit field determines which event will load the active register from the shadow register.
- Before a write, the CMPCTL[SHDWAFULL] bit can be read to determine if the shadow register is currently full.
- If CMPCTL[SHDWAMODE] = 1, then the shadow register is disabled and any write or read will go directly to the active register, that is the register actively controlling the hardware.
- In either mode, the active and shadow registers share the same memory map address.

Reset type: SYSRSn

15-0CMPAHRR/W0hCompare A HRPWM Extension Register

The UPPER 8-bits contain the high-resolution portion (most significant 8-bits) of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the CMPCTL[SHDWAMODE] bit as described for the CMPA register.

The lower 8 bits in this register are ignored

Reset type: SYSRSn

17.17.2.40 CMPB Register (Offset = 6Ch) [Reset = 00000000h]

CMPB is shown in Figure 17-132 and described in Table 17-63.

Return to the Summary Table.

Compare B Register

Figure 17-132 CMPB Register
313029282726252423222120191817161514131211109876543210
CMPBCMPBHR
R/W-0hR/W-0h
Table 17-63 CMPB Register Field Descriptions
BitFieldTypeResetDescription
31-16CMPBR/W0hCompare B Register

The value in the active CMPB register is continuously compared to the time-base counter (TBCTR). When the values are equal, the counter-compare module generates a 'time-base counter equal to counter compare B' event. This event is sent to the action-qualifier where it is qualified and converted it into one or more actions. These actions can be applied to either the EPWMxA or the EPWMxB output depending on the configuration of the AQCTLA and AQCTLB registers. The actions that can be defined in the AQCTLA and AQCTLB registers include:

- Do nothing
the event is ignored.
- Clear: Pull the EPWMxA and/or EPWMxB signal low
- Set: Pull the EPWMxA and/or EPWMxB signal high
- Toggle the EPWMxA and/or EPWMxB signal

Shadowing of this register is enabled and disabled by the CMPCTL[SHDWBMODE] bit. By default this register is shadowed.
- If CMPCTL[SHDWBMODE] = 0, then the shadow is enabled and any write or read will automatically go to the shadow register. In this case, the CMPCTL[LOADBMODE] bit field determines which event will load the active register from the shadow register.
- Before a write, the CMPCTL[SHDWBFULL] bit can be read to determine if the shadow register is currently full.
- If CMPCTL[SHDWBMODE] = 1, then the shadow register is disabled and any write or read will go directly to the active register, that is the register actively controlling the hardware.
- In either mode, the active and shadow registers share the same memory map address.

Reset type: SYSRSn

15-0CMPBHRR/W0hCompare B High Resolution Bits

The lower 8 bits in this register are ignored

Reset type: SYSRSn

17.17.2.41 CMPC Register (Offset = 6Fh) [Reset = 0000h]

CMPC is shown in Figure 17-133 and described in Table 17-64.

Return to the Summary Table.

Counter Compare C Register

LINK feature access should always be 16-bit

Figure 17-133 CMPC Register
15141312111098
CMPC
R/W-0h
76543210
CMPC
R/W-0h
Table 17-64 CMPC Register Field Descriptions
BitFieldTypeResetDescription
15-0CMPCR/W0hCompare C Register

The value in the active CMPC register is continuously compared to the time-base counter (TBCTR). When the values are equal, the counter-compare module generates a 'time-base counter equal to counter compare C' event.

Shadowing of this register is enabled and disabled by the CMPCTL2[SHDWCMODE] bit. By default this register is shadowed.
- If CMPCTL2[SHDWCMODE] = 0, then the shadow is enabled and any write or read will automatically go to the shadow register. In this case, the CMPCTL2[LOADCMODE] bit field determines which event will load the active register from the shadow register:
- If CMPCTL2[SHDWCMODE] = 1, then the shadow register is disabled and any write or read will go directly to the active register
that is, the register actively controlling the hardware.
- In either mode, the active and shadow registers share the same memory map address.

Reset type: SYSRSn

17.17.2.42 CMPD Register (Offset = 71h) [Reset = 0000h]

CMPD is shown in Figure 17-134 and described in Table 17-65.

Return to the Summary Table.

Counter Compare D Register

LINK feature access should always be 16-bit

Figure 17-134 CMPD Register
15141312111098
CMPD
R/W-0h
76543210
CMPD
R/W-0h
Table 17-65 CMPD Register Field Descriptions
BitFieldTypeResetDescription
15-0CMPDR/W0hCompare D Register

The value in the active CMPD register is continuously compared to the time-base counter (TBCTR). When the values are equal, the counter-compare module generates a 'time-base counter equal to counter compare D' event.

Shadowing of this register is enabled and disabled by the CMPCTL2[SHDWDMODE] bit. By default this register is shadowed.
- If CMPCTL2[SHDWDMODE] = 0, then the shadow is enabled and any write or read will automatically go to the shadow register. In this case, the CMPCTL2[LOADDMODE] bit field determines which event will load the active register from the shadow register:
- If CMPCTL2[SHDWDMODE] = 1, then the shadow register is disabled and any write or read will go directly to the active register
that is, the register actively controlling the hardware.
- In either mode, the active and shadow registers share the same memory map address.

Reset type: SYSRSn

17.17.2.43 GLDCTL2 Register (Offset = 74h) [Reset = 0000h]

GLDCTL2 is shown in Figure 17-135 and described in Table 17-66.

Return to the Summary Table.

Global PWM Load Control Register 2

Figure 17-135 GLDCTL2 Register
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDGFRCLDOSHTLD
R-0-0hR-0/W1S-0hR-0/W1S-0h
Table 17-66 GLDCTL2 Register Field Descriptions
BitFieldTypeResetDescription
15-2RESERVEDR-00hReserved
1GFRCLDR-0/W1S0hForce Load Event in One Shot Mode

0: Writing of 0 will be ignored. Always reads back a 0.
1: Force one load event at the input of the event pre-scale counter. This bit is intended to be used for testing and/or software force loading of the events in global load mode.

Reset type: SYSRSn

0OSHTLDR-0/W1S0hEnable Reload Event in One Shot Mode

0: Writing of 0 will be ignored. Always reads back a 0.
1: Turns the one shot latch condition ON. Upon occurrence of a chosen load strobe, one shadow to active reload occurs and the latch will be cleared. Hence writing 1 to this bit would allow one load strobe event to pass through and block further strobe events.

Reset type: SYSRSn

17.17.2.44 SWVDELVAL Register (Offset = 77h) [Reset = 0000h]

SWVDELVAL is shown in Figure 17-136 and described in Table 17-67.

Return to the Summary Table.

Software Valley Mode Delay Register

Figure 17-136 SWVDELVAL Register
15141312111098
SWVDELVAL
R/W-0h
76543210
SWVDELVAL
R/W-0h
Table 17-67 SWVDELVAL Register Field Descriptions
BitFieldTypeResetDescription
15-0SWVDELVALR/W0hSoftware Valley Delay Value Register

This register can be optionally used define offset value for the hardware calculated delay HWDELAYVAL as defined in VCAPCTL[VDELAYDIV] bits.

Reset type: SYSRSn

17.17.2.45 TZSEL Register (Offset = 80h) [Reset = 0000h]

TZSEL is shown in Figure 17-137 and described in Table 17-68.

Return to the Summary Table.

Trip Zone Select Register

Figure 17-137 TZSEL Register
15141312111098
DCBEVT1DCAEVT1OSHT6OSHT5OSHT4OSHT3OSHT2OSHT1
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
DCBEVT2DCAEVT2CBC6CBC5CBC4CBC3CBC2CBC1
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 17-68 TZSEL Register Field Descriptions
BitFieldTypeResetDescription
15DCBEVT1R/W0hDigital Compare Output B Event 1 Select

0: Disable DCBEVT1 as one-shot-trip source for this ePWM module.
1: Enable DCBEVT1 as one-shot-trip source for this ePWM module.

Reset type: SYSRSn

14DCAEVT1R/W0hDigital Compare Output A Event 1 Select

0: Disable DCAEVT1 as one-shot-trip source for this ePWM module.
1: Enable DCAEVT1 as one-shot-trip source for this ePWM module.

Reset type: SYSRSn

13OSHT6R/W0hTrip-zone 6 (TZ6) Select

0: Disable TZ6 as a one-shot trip source for this ePWM module
1: Enable TZ6 as a one-shot trip source for this ePWM module

Reset type: SYSRSn

12OSHT5R/W0hTrip-zone 5 (TZ5) Select

0: Disable TZ5 as a one-shot trip source for this ePWM module
1: Enable TZ5 as a one-shot trip source for this ePWM module

Reset type: SYSRSn

11OSHT4R/W0hTrip-zone 4 (TZ4) Select

0: Disable TZ4 as a one-shot trip source for this ePWM module
1: Enable TZ4 as a one-shot trip source for this ePWM module

Reset type: SYSRSn

10OSHT3R/W0hTrip-zone 3 (TZ3) Select

0: Disable TZ3 as a one-shot trip source for this ePWM module
1: Enable TZ3 as a one-shot trip source for this ePWM module

Reset type: SYSRSn

9OSHT2R/W0hTrip-zone 2 (TZ2) Select

0: Disable TZ2 as a one-shot trip source for this ePWM module
1: Enable TZ2 as a one-shot trip source for this ePWM module

Reset type: SYSRSn

8OSHT1R/W0hTrip-zone 1 (TZ1) Select

0: Disable TZ1 as a one-shot trip source for this ePWM module
1: Enable TZ1 as a one-shot trip source for this ePWM module

Reset type: SYSRSn

7DCBEVT2R/W0hDigital Compare Output B Event 2 Select

0: Disable DCBEVT2 as a CBC trip source for this ePWM module
1: Enable DCBEVT2 as a CBC trip source for this ePWM module

Reset type: SYSRSn

6DCAEVT2R/W0hDigital Compare Output A Event 2 Select

0: Disable DCAEVT2 as a CBC trip source for this ePWM module
1: Enable DCAEVT2 as a CBC trip source for this ePWM module

Reset type: SYSRSn

5CBC6R/W0hTrip-zone 6 (TZ6) Select

0: Disable TZ6 as a CBC trip source for this ePWM module
1: Enable TZ6 as a CBC trip source for this ePWM module

Reset type: SYSRSn

4CBC5R/W0hTrip-zone 5 (TZ5) Select

0: Disable TZ5 as a CBC trip source for this ePWM module
1: Enable TZ5 as a CBC trip source for this ePWM module

Reset type: SYSRSn

3CBC4R/W0hTrip-zone 4 (TZ4) Select

0: Disable TZ4 as a CBC trip source for this ePWM module
1: Enable TZ4 as a CBC trip source for this ePWM module

Reset type: SYSRSn

2CBC3R/W0hTrip-zone 3 (TZ3) Select

0: Disable TZ3 as a CBC trip source for this ePWM module
1: Enable TZ3 as a CBC trip source for this ePWM module

Reset type: SYSRSn

1CBC2R/W0hTrip-zone 2 (TZ2) Select

0: Disable TZ2 as a CBC trip source for this ePWM module
1: Enable TZ2 as a CBC trip source for this ePWM module

Reset type: SYSRSn

0CBC1R/W0hTrip-zone 1 (TZ1) Select

0: Disable TZ1 as a CBC trip source for this ePWM module
1: Enable TZ1 as a CBC trip source for this ePWM module

Reset type: SYSRSn

17.17.2.46 TZDCSEL Register (Offset = 82h) [Reset = 0000h]

TZDCSEL is shown in Figure 17-138 and described in Table 17-69.

Return to the Summary Table.

Trip Zone Digital Comparator Select Register

Figure 17-138 TZDCSEL Register
15141312111098
RESERVEDDCBEVT2DCBEVT1
R-0-0hR/W-0hR/W-0h
76543210
DCBEVT1DCAEVT2DCAEVT1
R/W-0hR/W-0hR/W-0h
Table 17-69 TZDCSEL Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR-00hReserved
11-9DCBEVT2R/W0hDigital Compare Output B Event 2 Selection

000: Event disabled
001: DCBH = low, DCBL = don't care
010: DCBH = high, DCBL = don't care
011: DCBL = low, DCBH = don't care
100: DCBL = high, DCBH = don't care
101: DCBL = high, DCBH = low
110: Reserved
111: Reserved

Reset type: SYSRSn

8-6DCBEVT1R/W0hDigital Compare Output B Event 1 Selection

000: Event disabled
001: DCBH = low, DCBL = don't care
010: DCBH = high, DCBL = don't care
011: DCBL = low, DCBH = don't care
100: DCBL = high, DCBH = don't care
101: DCBL = high, DCBH = low
110: Reserved
111: Reserved

Reset type: SYSRSn

5-3DCAEVT2R/W0hDigital Compare Output A Event 2 Selection

000: Event disabled
001: DCAH = low, DCAL = don't care
010: DCAH = high, DCAL = don't care
011: DCAL = low, DCAH = don't care
100: DCAL = high, DCAH = don't care
101: DCAL = high, DCAH = low
110: Reserved
111: Reserved

Reset type: SYSRSn

2-0DCAEVT1R/W0hDigital Compare Output A Event 1 Selection

000: Event disabled
001: DCAH = low, DCAL = don't care
010: DCAH = high, DCAL = don't care
011: DCAL = low, DCAH = don't care
100: DCAL = high, DCAH = don't care
101: DCAL = high, DCAH = low
110: Reserved
111: Reserved

Reset type: SYSRSn

17.17.2.47 TZCTL Register (Offset = 84h) [Reset = 0000h]

TZCTL is shown in Figure 17-139 and described in Table 17-70.

Return to the Summary Table.

Trip Zone Control Register

Figure 17-139 TZCTL Register
15141312111098
RESERVEDDCBEVT2DCBEVT1
R-0-0hR/W-0hR/W-0h
76543210
DCAEVT2DCAEVT1TZBTZA
R/W-0hR/W-0hR/W-0hR/W-0h
Table 17-70 TZCTL Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR-00hReserved
11-10DCBEVT2R/W0hDigital Compare Output B Event 2 Action On EPWMxB

00: High-impedance (EPWMxB = High-impedance state)
01: Force EPWMxB to a high state.
10: Force EPWMxB to a low state.
11: Do Nothing, trip action is disabled

Reset type: SYSRSn

9-8DCBEVT1R/W0hDigital Compare Output B Event 1 Action On EPWMxB

00: High-impedance (EPWMxB = High-impedance state)
01: Force EPWMxB to a high state.
10: Force EPWMxB to a low state.
11: Do Nothing, trip action is disabled

Reset type: SYSRSn

7-6DCAEVT2R/W0hDigital Compare Output A Event 2 Action On EPWMxA

00: High-impedance (EPWMxA = High-impedance state)
01: Force EPWMxA to a high state.
10: Force EPWMxA to a low state.
11: Do Nothing, trip action is disabled

Reset type: SYSRSn

5-4DCAEVT1R/W0hDigital Compare Output A Event 1 Action On EPWMxA

00: High-impedance (EPWMxA = High-impedance state)
01: Force EPWMxA to a high state.
10: Force EPWMxA to a low state.
11: Do Nothing, trip action is disabled

Reset type: SYSRSn

3-2TZBR/W0hTZ1 to TZ6, DCAEVT1/2, DCBEVT1/2Trip Action On EPWMxB

When a trip event occurs the following action is taken on output EPWMxB. Which trip-zone pins can cause an event is defined in the TZSEL register.

00: High-impedance (EPWMxB = High-impedance state)
01: Force EPWMxB to a high state
10: Force EPWMxB to a low state
11: Do nothing, no action is taken on EPWMxB.

Reset type: SYSRSn

1-0TZAR/W0hTZ1 to TZ6, DCAEVT1/2, DCBEVT1/2 Trip Action On EPWMxA

When a trip event occurs the following action is taken on output EPWMxA. Which trip-zone pins can cause an event is defined in the TZSEL register.

00: High-impedance (EPWMxA = High-impedance state)
01: Force EPWMxA to a high state
10: Force EPWMxA to a low state
11: Do nothing, no action is taken on EPWMxA.

Reset type: SYSRSn

17.17.2.48 TZCTL2 Register (Offset = 85h) [Reset = 0000h]

TZCTL2 is shown in Figure 17-140 and described in Table 17-71.

Return to the Summary Table.

Additional Trip Zone Control Register

Figure 17-140 TZCTL2 Register
15141312111098
ETZERESERVEDTZBDTZBU
R/W-0hR-0-0hR/W-0hR/W-0h
76543210
TZBUTZADTZAU
R/W-0hR/W-0hR/W-0h
Table 17-71 TZCTL2 Register Field Descriptions
BitFieldTypeResetDescription
15ETZER/W0hTZCTL2 Enable

0: Use trip action from TZCTL (legacy EPWM compatibility)
1: Use trip action defined in TZCTL2, TZCTLDCA and TZCTLDCB. Settings in TZCTL are ignored

Reset type: SYSRSn

14-12RESERVEDR-00hReserved
11-9TZBDR/W0hTZ1 to TZ6 Trip Action On EPWMxB while Count direction is DOWN

000: HiZ (EPWMxB = HiZ state)
001: Forced Hi (EPWMxB = High state)
010: Forced Lo (EPWMxB = Lo state)
011: Toggle (Low -> High, High -> Low)
100: Reserved
101: Reserved
110: Reserved
111: Do Nothing, trip action is disabled

Reset type: SYSRSn

8-6TZBUR/W0hTZ1 to TZ6, DCAEVT1/2, DCBEVT1/2 Trip Action On EPWMxB while Count direction is UP

000: HiZ (EPWMxB = HiZ state)
001: Forced Hi (EPWMxB = High state)
010: Forced Lo (EPWMxB = Lo state)
011: Toggle (Low -> High, High -> Low)
100: Reserved
101: Reserved
110: Reserved
111: Do Nothing, trip action is disabled

Reset type: SYSRSn

5-3TZADR/W0hTZ1 to TZ6, DCAEVT1/2, DCBEVT1/2 Trip Action On EPWMxA while Count direction is DOWN

000: HiZ (EPWMxA = HiZ state)
001: Forced Hi (EPWMxA = High state)
010: Forced Lo (EPWMxA = Lo state)
011: Toggle (Low -> High, High -> Low)
100: Reserved
101: Reserved
110: Reserved
111: Do Nothing, trip action is disabled

Reset type: SYSRSn

2-0TZAUR/W0hTZ1 to TZ6, DCAEVT1/2, DCBEVT1/2 Trip Action On EPWMxA while Count direction is UP

000: HiZ (EPWMxA = HiZ state)
001: Forced Hi (EPWMxA = High state)
010: Forced Lo (EPWMxA = Lo state)
011: Toggle (Low -> High, High -> Low)
100: Reserved
101: Reserved
110: Reserved
111: Do Nothing, trip action is disabled

Reset type: SYSRSn

17.17.2.49 TZCTLDCA Register (Offset = 86h) [Reset = 0000h]

TZCTLDCA is shown in Figure 17-141 and described in Table 17-72.

Return to the Summary Table.

Trip Zone Control Register Digital Compare A

Figure 17-141 TZCTLDCA Register
15141312111098
RESERVEDDCAEVT2DDCAEVT2U
R-0-0hR/W-0hR/W-0h
76543210
DCAEVT2UDCAEVT1DDCAEVT1U
R/W-0hR/W-0hR/W-0h
Table 17-72 TZCTLDCA Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR-00hReserved
11-9DCAEVT2DR/W0hDigital Compare Output A Event 2 Action On EPWMxA while Count direction is DOWN

000: HiZ (EPWMxA = HiZ state)
001: Forced Hi (EPWMxA = High state)
010: Forced Lo (EPWMxA = Lo state)
011: Toggle (Low -> High, High -> Low)
100: Reserved
101: Reserved
110: Reserved
111: Do Nothing, trip action is disabled

Reset type: SYSRSn

8-6DCAEVT2UR/W0hDigital Compare Output A Event 2 Action On EPWMxA while Count direction is UP

000: HiZ (EPWMxA = HiZ state)
001: Forced Hi (EPWMxA = High state)
010: Forced Lo (EPWMxA = Lo state)
011: Toggle (Low -> High, High -> Low)
100: Reserved
101: Reserved
110: Reserved
111: Do Nothing, trip action is disabled

Reset type: SYSRSn

5-3DCAEVT1DR/W0hDigital Compare Output A Event 1 Action On EPWMxA while Count direction is DOWN

000: HiZ (EPWMxA = HiZ state)
001: Forced Hi (EPWMxA = High state)
010: Forced Lo (EPWMxA = Lo state)
011: Toggle (Low -> High, High -> Low)
100: Reserved
101: Reserved
110: Reserved
111: Do Nothing, trip action is disabled

Reset type: SYSRSn

2-0DCAEVT1UR/W0hDigital Compare Output A Event 1 Action On EPWMxA while Count direction is UP

000: HiZ (EPWMxA = HiZ state)
001: Forced Hi (EPWMxA = High state)
010: Forced Lo (EPWMxA = Lo state)
011: Toggle (Low -> High, High -> Low)
100: Reserved
101: Reserved
110: Reserved
111: Do Nothing, trip action is disabled

Reset type: SYSRSn

17.17.2.50 TZCTLDCB Register (Offset = 87h) [Reset = 0000h]

TZCTLDCB is shown in Figure 17-142 and described in Table 17-73.

Return to the Summary Table.

Trip Zone Control Register Digital Compare B

Figure 17-142 TZCTLDCB Register
15141312111098
RESERVEDDCBEVT2DDCBEVT2U
R-0-0hR/W-0hR/W-0h
76543210
DCBEVT2UDCBEVT1DDCBEVT1U
R/W-0hR/W-0hR/W-0h
Table 17-73 TZCTLDCB Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR-00hReserved
11-9DCBEVT2DR/W0hDigital Compare Output B Event 2 Action On EPWMxB while Count direction is DOWN

000: HiZ (EPWMxB = HiZ state)
001: Forced Hi (EPWMxB = High state)
010: Forced Lo (EPWMxB = Lo state)
011: Toggle (Low -> High, High -> Low)
100: Reserved
101: Reserved
110: Reserved
111: Do Nothing, trip action is disabled

Reset type: SYSRSn

8-6DCBEVT2UR/W0hDigital Compare Output B Event 2 Action On EPWMxB while Count direction is UP

000: HiZ (EPWMxB = HiZ state)
001: Forced Hi (EPWMxB = High state)
010: Forced Lo (EPWMxB = Lo state)
011: Toggle (Low -> High, High -> Low)
100: Reserved
101: Reserved
110: Reserved
111: Do Nothing, trip action is disabled

Reset type: SYSRSn

5-3DCBEVT1DR/W0hDigital Compare Output B Event 1 Action On EPWMxB while Count direction is DOWN

000: HiZ (EPWMxB = HiZ state)
001: Forced Hi (EPWMxB = High state)
010: Forced Lo (EPWMxB = Lo state)
011: Toggle (Low -> High, High -> Low)
100: Reserved
101: Reserved
110: Reserved
111: Do Nothing, trip action is disabled

Reset type: SYSRSn

2-0DCBEVT1UR/W0hDigital Compare Output B Event 1 Action On EPWMxB while Count direction is UP

000: HiZ (EPWMxB = HiZ state)
001: Forced Hi (EPWMxB = High state)
010: Forced Lo (EPWMxB = Lo state)
011: Toggle (Low -> High, High -> Low)
100: Reserved
101: Reserved
110: Reserved
111: Do Nothing, trip action is disabled

Reset type: SYSRSn

17.17.2.51 TZEINT Register (Offset = 8Dh) [Reset = 0000h]

TZEINT is shown in Figure 17-143 and described in Table 17-74.

Return to the Summary Table.

Trip Zone Enable Interrupt Register

Figure 17-143 TZEINT Register
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDDCBEVT2DCBEVT1DCAEVT2DCAEVT1OSTCBCRESERVED
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR-0-0h
Table 17-74 TZEINT Register Field Descriptions
BitFieldTypeResetDescription
15-7RESERVEDR-00hReserved
6DCBEVT2R/W0hDigital Compare Output B Event 2 Interrupt Enable

0: Disabled
1: Enabled

Reset type: SYSRSn

5DCBEVT1R/W0hDigital Compare Output B Event 1 Interrupt Enable

0: Disabled
1: Enabled

Reset type: SYSRSn

4DCAEVT2R/W0hDigital Compare Output A Event 2 Interrupt Enable

0: Disabled
1: Enabled

Reset type: SYSRSn

3DCAEVT1R/W0hDigital Compare Output A Event 1 Interrupt Enable

0: Disabled
1: Enabled

Reset type: SYSRSn

2OSTR/W0hTrip-zone One-Shot Interrupt Enable

0: Disable one-shot interrupt generation
1: Enable Interrupt generation
a one-shot trip event will cause a EPWMx_TZINT PIE interrupt.

Reset type: SYSRSn

1CBCR/W0hTrip-zone Cycle-by-Cycle Interrupt Enable

0: Disable cycle-by-cycle interrupt generation.
1: Enable interrupt generation
a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt.

Reset type: SYSRSn

0RESERVEDR-00hReserved

17.17.2.52 TZFLG Register (Offset = 93h) [Reset = 0000h]

TZFLG is shown in Figure 17-144 and described in Table 17-75.

Return to the Summary Table.

Trip Zone Flag Register

Figure 17-144 TZFLG Register
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDDCBEVT2DCBEVT1DCAEVT2DCAEVT1OSTCBCINT
R-0-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 17-75 TZFLG Register Field Descriptions
BitFieldTypeResetDescription
15-7RESERVEDR-00hReserved
6DCBEVT2R0hLatched Status Flag for Digital Compare Output B Event 2

0: Indicates no trip event has occurred on DCBEVT2
1: Indicates a trip event has occurred for the event defined for DCBEVT2

Reset type: SYSRSn

5DCBEVT1R0hLatched Status Flag for Digital Compare Output B Event 1

0: Indicates no trip event has occurred on DCBEVT1
1: Indicates a trip event has occurred for the event defined for DCBEVT1

Reset type: SYSRSn

4DCAEVT2R0hLatched Status Flag for Digital Compare Output A Event 2

0: Indicates no trip event has occurred on DCAEVT2
1: Indicates a trip event has occurred for the event defined for DCAEVT2

Reset type: SYSRSn

3DCAEVT1R0hLatched Status Flag for Digital Compare Output A Event 1

0: Indicates no trip event has occurred on DCAEVT1
1: Indicates a trip event has occurred for the event defined for DCAEVT1

Reset type: SYSRSn

2OSTR0hLatched Status Flag for A One-Shot Trip Event

0: No one-shot trip event has occurred.
1: Indicates a trip event has occurred on a pin selected as a one-shot trip source.

This bit is cleared by writing the appropriate value to the TZCLR register.

Reset type: SYSRSn

1CBCR0hLatched Status Flag for Cycle-By-Cycle Trip Event

0: No cycle-by-cycle trip event has occurred.
1: Indicates a trip event has occurred on a signal selected as a cycle-by-cycle trip source. The

TZFLG[CBC] bit will remain set until it is manually cleared by the user. If the cycle-by-cycle trip event is still present when the CBC bit is cleared, then CBC will be immediately set again. The specified condition on the signal is automatically cleared when the ePWM time-base counter reaches zero (TBCTR = 0x00) if the trip condition is no longer present. The condition on the signal is only cleared when the TBCTR = 0x00 no matter where in the cycle the CBC flag is cleared.

This bit is cleared by writing the appropriate value to the TZCLR register.

Reset type: SYSRSn

0INTR0hLatched Trip Interrupt Status Flag

0: Indicates no interrupt has been generated.
1: Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition.

No further EPWMx_TZINT PIE interrupts will be generated until this flag is cleared. If the interrupt flag is cleared when either CBC or OST is set, then another interrupt pulse will be generated. Clearing all flag bits will prevent further interrupts. This bit is cleared by writing the appropriate value to the TZCLR register.

Reset type: SYSRSn

17.17.2.53 TZCBCFLG Register (Offset = 94h) [Reset = 0000h]

TZCBCFLG is shown in Figure 17-145 and described in Table 17-76.

Return to the Summary Table.

Trip Zone CBC Flag Register

Figure 17-145 TZCBCFLG Register
15141312111098
RESERVED
R-0-0h
76543210
DCBEVT2DCAEVT2CBC6CBC5CBC4CBC3CBC2CBC1
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 17-76 TZCBCFLG Register Field Descriptions
BitFieldTypeResetDescription
15-8RESERVEDR-00hReserved
7DCBEVT2R0hLatched Status Flag for Digital Compare B Output Event 2 Trip Latch

0: Reading a 0 indicates that no trip has occurred on DCBEVT2.
1: Reading a 1 indicates a trip has occured on the DCBEVT2 selected event.

Reset type: SYSRSn

6DCAEVT2R0hLatched Status Flag for Digital Compare A Output Event 2 Trip Latch

0: Reading a 0 indicates that no trip has occurred on DCAEVT2.
1: Reading a 1 indicates a trip has occured on the DCAEVT2 selected event.

Reset type: SYSRSn

5CBC6R0hLatched Status Flag for CBC6 Trip Latch

0: Reading a 0 indicates that no trip has occurred on CBC6.
1: Reading a 1 indicates a trip has occured on the CBC6 selected event.

Reset type: SYSRSn

4CBC5R0hLatched Status Flag for CBC5 Trip Latch

0: Reading a 0 indicates that no trip has occurred on CBC5.
1: Reading a 1 indicates a trip has occured on the CBC5 selected event.

Reset type: SYSRSn

3CBC4R0hLatched Status Flag for CBC4 Trip Latch

0: Reading a 0 indicates that no trip has occurred on CBC4.
1: Reading a 1 indicates a trip has occured on the CBC4 selected event.

Reset type: SYSRSn

2CBC3R0hLatched Status Flag for CBC3 Trip Latch

0: Reading a 0 indicates that no trip has occurred on CBC3.
1: Reading a 1 indicates a trip has occured on the CBC3 selected event.

Reset type: SYSRSn

1CBC2R0hLatched Status Flag for CBC2 Trip Latch

0: Reading a 0 indicates that no trip has occurred on CBC2.
1: Reading a 1 indicates a trip has occured on the CBC2 selected event.

Reset type: SYSRSn

0CBC1R0hLatched Status Flag for CBC1 Trip Latch

0: Reading a 0 indicates that no trip has occurred on CBC1.
1: Reading a 1 indicates a trip has occured on the CBC1 selected event.

Reset type: SYSRSn

17.17.2.54 TZOSTFLG Register (Offset = 95h) [Reset = 0000h]

TZOSTFLG is shown in Figure 17-146 and described in Table 17-77.

Return to the Summary Table.

Trip Zone OST Flag Register

Figure 17-146 TZOSTFLG Register
15141312111098
RESERVED
R-0-0h
76543210
DCBEVT1DCAEVT1OST6OST5OST4OST3OST2OST1
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 17-77 TZOSTFLG Register Field Descriptions
BitFieldTypeResetDescription
15-8RESERVEDR-00hReserved
7DCBEVT1R0hLatched Status Flag for Digital Compare B Output Event 1 Trip Latch

0: Reading a 0 indicates that no trip has occurred on DCBEVT1.
1: Reading a 1 indicates a trip has occured on the DCBEVT1 selected event.

Reset type: SYSRSn

6DCAEVT1R0hLatched Status Flag for Digital Compare A Output Event 1 Trip Latch

0: Reading a 0 indicates that no trip has occurred on DCAEVT1.
1: Reading a 1 indicates a trip has occured on the DCAEVT1 selected event.

Reset type: SYSRSn

5OST6R0hLatched Status Flag for OST6 Trip Latch

0: Reading a 0 indicates that no trip has occurred on OST6.
1: Reading a 1 indicates a trip has occured on the OST6 selected event.

Reset type: SYSRSn

4OST5R0hLatched Status Flag for OST5 Trip Latch

0: Reading a 0 indicates that no trip has occurred on OST5.
1: Reading a 1 indicates a trip has occured on the OST5 selected event.

Reset type: SYSRSn

3OST4R0hLatched Status Flag for OST4 Trip Latch

0: Reading a 0 indicates that no trip has occurred on OST4.
1: Reading a 1 indicates a trip has occured on the OST4 selected event.

Reset type: SYSRSn

2OST3R0hLatched Status Flag for OST3 Trip Latch

0: Reading a 0 indicates that no trip has occurred on OST3.
1: Reading a 1 indicates a trip has occured on the OST3 selected event.

Reset type: SYSRSn

1OST2R0hLatched Status Flag for OST2 Trip Latch

0: Reading a 0 indicates that no trip has occurred on OST2.
1: Reading a 1 indicates a trip has occured on the OST2 selected event.

Reset type: SYSRSn

0OST1R0hLatched Status Flag for OST1 Trip Latch

0: Reading a 0 indicates that no trip has occurred on OST1.
1: Reading a 1 indicates a trip has occured on the OST1 selected event.

Reset type: SYSRSn

17.17.2.55 TZCLR Register (Offset = 97h) [Reset = 0000h]

TZCLR is shown in Figure 17-147 and described in Table 17-78.

Return to the Summary Table.

Trip Zone Clear Register

Figure 17-147 TZCLR Register
15141312111098
CBCPULSERESERVED
R/W-0hR-0-0h
76543210
RESERVEDDCBEVT2DCBEVT1DCAEVT2DCAEVT1OSTCBCINT
R-0-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 17-78 TZCLR Register Field Descriptions
BitFieldTypeResetDescription
15-14CBCPULSER/W0hClear Pulse for Cycle-By-Cycle (CBC) Trip Latch

This bit field determines which pulse clears the CBC trip latch.

00: CTR = zero pulse clears CBC trip latch. (Same as legacy designs.)
01: CTR = PRD pulse clears CBC trip latch.
10: CTR = zero or CTR = PRD pulse clears CBC trip latch.
11: CBC trip latch is not cleared

Reset type: SYSRSn

13-7RESERVEDR-00hReserved
6DCBEVT2R-0/W1S0hClear Flag for Digital Compare Output B Event 2

0: Writing 0 has no effect. This bit always reads back 0.
1: Writing 1 clears the DCBEVT2 event trip condition.

Reset type: SYSRSn

5DCBEVT1R-0/W1S0hClear Flag for Digital Compare Output B Event 1

0: Writing 0 has no effect. This bit always reads back 0.
1: Writing 1 clears the DCBEVT1 event trip condition.

Reset type: SYSRSn

4DCAEVT2R-0/W1S0hClear Flag for Digital Compare Output A Event 2

0: Writing 0 has no effect. This bit always reads back 0.
1: Writing 1 clears the DCAEVT2 event trip condition.

Reset type: SYSRSn

3DCAEVT1R-0/W1S0hClear Flag for Digital Compare Output A Event 1

0: Writing 0 has no effect. This bit always reads back 0.
1: Writing 1 clears the DCAEVT1 event trip condition.

Reset type: SYSRSn

2OSTR-0/W1S0hClear Flag for One-Shot Trip (OST) Latch

0: Has no effect. Always reads back a 0.
1: Clears this Trip (set) condition.

Reset type: SYSRSn

1CBCR-0/W1S0hClear Flag for Cycle-By-Cycle (CBC) Trip Latch

0: Has no effect. Always reads back a 0.
1: Clears this Trip (set) condition.

Reset type: SYSRSn

0INTR-0/W1S0hGlobal Interrupt Clear Flag

0: Has no effect. Always reads back a 0.
1: Clears the trip-interrupt flag for this ePWM module (TZFLG[INT]).

NOTE: No further EPWMx_TZINT PIE interrupts will be generated until the flag is cleared. If the TZFLG[INT] bit is cleared and any of the other flag bits are set, then another interrupt pulse will be generated. Clearing all flag bits will prevent further interrupts.

Reset type: SYSRSn

17.17.2.56 TZCBCCLR Register (Offset = 98h) [Reset = 0000h]

TZCBCCLR is shown in Figure 17-148 and described in Table 17-79.

Return to the Summary Table.

Trip Zone CBC Clear Register

Figure 17-148 TZCBCCLR Register
15141312111098
RESERVED
R-0-0h
76543210
DCBEVT2DCAEVT2CBC6CBC5CBC4CBC3CBC2CBC1
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 17-79 TZCBCCLR Register Field Descriptions
BitFieldTypeResetDescription
15-8RESERVEDR-00hReserved
7DCBEVT2R-0/W1S0hClear Flag for Digital Compare Output B Event 2 selected for CBC

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit.

Reset type: SYSRSn

6DCAEVT2R-0/W1S0hClear Flag for Digital Compare Output A Event 2 selected for CBC

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit.

Reset type: SYSRSn

5CBC6R-0/W1S0hClear Flag for Cycle-By-Cycle (CBC6) Trip Latch

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCFLG[CBC6] bit.

Reset type: SYSRSn

4CBC5R-0/W1S0hClear Flag for Cycle-By-Cycle (CBC5) Trip Latch

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCFLG[CBC5] bit.

Reset type: SYSRSn

3CBC4R-0/W1S0hClear Flag for Cycle-By-Cycle (CBC4) Trip Latch

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCFLG[CBC4] bit.

Reset type: SYSRSn

2CBC3R-0/W1S0hClear Flag for Cycle-By-Cycle (CBC3) Trip Latch

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCFLG[CBC3] bit.

Reset type: SYSRSn

1CBC2R-0/W1S0hClear Flag for Cycle-By-Cycle (CBC2) Trip Latch

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCFLG[CBC2] bit.

Reset type: SYSRSn

0CBC1R-0/W1S0hClear Flag for Cycle-By-Cycle (CBC1) Trip Latch

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZCBCFLG[CBC1] bit.

Reset type: SYSRSn

17.17.2.57 TZOSTCLR Register (Offset = 99h) [Reset = 0000h]

TZOSTCLR is shown in Figure 17-149 and described in Table 17-80.

Return to the Summary Table.

Trip Zone OST Clear Register

Figure 17-149 TZOSTCLR Register
15141312111098
RESERVED
R-0-0h
76543210
DCBEVT1DCAEVT1OST6OST5OST4OST3OST2OST1
R-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0h
Table 17-80 TZOSTCLR Register Field Descriptions
BitFieldTypeResetDescription
15-8RESERVEDR-00hReserved
7DCBEVT1R-0/W1S0hClear Flag for Digital Compare Output B Event 1 selected for OST

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZOSTFLG[DCBEVT1] bit.

Reset type: SYSRSn

6DCAEVT1R-0/W1S0hClear Flag for Digital Compare Output A Event 1 selected for OST

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZOSTFLG[DCAEVT1] bit.

Reset type: SYSRSn

5OST6R-0/W1S0hClear Flag for Oneshot (OST6) Trip Latch

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZOSTFLG[OST6] bit.

Reset type: SYSRSn

4OST5R-0/W1S0hClear Flag for Oneshot (OST5) Trip Latch

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZOSTFLG[OST5] bit.

Reset type: SYSRSn

3OST4R-0/W1S0hClear Flag for Oneshot (OST4) Trip Latch

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZOSTFLG[OST4] bit.

Reset type: SYSRSn

2OST3R-0/W1S0hClear Flag for Oneshot (OST3) Trip Latch

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZOSTFLG[OST3] bit.

Reset type: SYSRSn

1OST2R-0/W1S0hClear Flag for Oneshot (OST2) Trip Latch

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZOSTFLG[OST2] bit.

Reset type: SYSRSn

0OST1R-0/W1S0hClear Flag for Oneshot (OST1) Trip Latch

0: Writing a 0 has no effect.
1: Writing a 1 will clear the TZOSTFLG[OST1] bit.

Reset type: SYSRSn

17.17.2.58 TZFRC Register (Offset = 9Bh) [Reset = 0000h]

TZFRC is shown in Figure 17-150 and described in Table 17-81.

Return to the Summary Table.

Trip Zone Force Register

Figure 17-150 TZFRC Register
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDDCBEVT2DCBEVT1DCAEVT2DCAEVT1OSTCBCRESERVED
R-0-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0-0h
Table 17-81 TZFRC Register Field Descriptions
BitFieldTypeResetDescription
15-7RESERVEDR-00hReserved
6DCBEVT2R-0/W1S0hForce Flag for Digital Compare Output B Event 2

0: Writing 0 has no effect. This bit always reads back 0.
1: Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit.

Reset type: SYSRSn

5DCBEVT1R-0/W1S0hForce Flag for Digital Compare Output B Event 1

0: Writing 0 has no effect. This bit always reads back 0.
1: Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit.

Reset type: SYSRSn

4DCAEVT2R-0/W1S0hForce Flag for Digital Compare Output A Event 2

0: Writing 0 has no effect. This bit always reads back 0.
1: Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit.

Reset type: SYSRSn

3DCAEVT1R-0/W1S0hForce Flag for Digital Compare Output A Event 1

0: Writing 0 has no effect. This bit always reads back 0
1: Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit.

Reset type: SYSRSn

2OSTR-0/W1S0hForce a One-Shot Trip Event via Software

0: Writing of 0 is ignored. Always reads back a 0.
1: Forces a one-shot trip event and sets the TZFLG[OST] bit.

Reset type: SYSRSn

1CBCR-0/W1S0hForce a Cycle-by-Cycle Trip Event via Software

0: Writing of 0 is ignored. Always reads back a 0.
1: Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit.

Reset type: SYSRSn

0RESERVEDR-00hReserved

17.17.2.59 ETSEL Register (Offset = A4h) [Reset = 0000h]

ETSEL is shown in Figure 17-151 and described in Table 17-82.

Return to the Summary Table.

Event Trigger Selection Register

Figure 17-151 ETSEL Register
15141312111098
SOCBENSOCBSELSOCAENSOCASEL
R/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDINTSELCMPSOCBSELCMPSOCASELCMPINTENINTSEL
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 17-82 ETSEL Register Field Descriptions
BitFieldTypeResetDescription
15SOCBENR/W0hEnable the ADC Start of Conversion B (EPWMxSOCB) Pulse

0: Disable EPWMxSOCB.
1: Enable EPWMxSOCB pulse.

Reset type: SYSRSn

14-12SOCBSELR/W0hEPWMxSOCB Selection Options

These bits determine when a EPWMxSOCB pulse will be generated.

000: Enable DCBEVT1.soc event
001: Enable event time-base counter equal to zero. (TBCTR = 0x00)
010: Enable event time-base counter equal to period (TBCTR = TBPRD)
011: Enable event time-base counter equal to zero or period (TBCTR = 0x00 or TBCTR = TBPRD). This mode is useful in up-down count mode.
100: Enable event time-base counter equal to CMPA when the timer is incrementing or CMPC when the timer is incrementing
101: Enable event time-base counter equal to CMPA when the timer is decrementing or CMPC when the timer is decrementing
110: Enable event: time-base counter equal to CMPB when the timer is incrementing or CMPD when the timer is incrementing
111: Enable event: time-base counter equal to CMPB when the timer is decrementing or CMPD when the timer is decrementing (*) Event selected is determined by SOCBSELCMP bit.

Reset type: SYSRSn

11SOCAENR/W0hEnable the ADC Start of Conversion A (EPWMxSOCA) Pulse

0: Disable EPWMxSOCA.
1: Enable EPWMxSOCA pulse.

Reset type: SYSRSn

10-8SOCASELR/W0hEPWMxSOCA Selection Options

These bits determine when a EPWMxSOCA pulse will be generated.

000: Enable DCAEVT1.soc event
001: Enable event time-base counter equal to zero. (TBCTR = 0x00)
010: Enable event time-base counter equal to period (TBCTR = TBPRD)
011: Enable event time-base counter equal to zero or period (TBCTR = 0x00 or TBCTR = TBPRD). This mode is useful in up-down count mode.
100: Enable event time-base counter equal to CMPA when the timer is incrementing or CMPC when the timer is incrementing
101: Enable event time-base counter equal to CMPA when the timer is decrementing or CMPC when the timer is decrementing
110: Enable event: time-base counter equal to CMPB when the timer is incrementing or CMPD when the timer is incrementing
111: Enable event: time-base counter equal to CMPB when the timer is decrementing or CMPD when the timer is decrementing (*) Event selected is determined by SOCASELCMP bit.

Reset type: SYSRSn

7RESERVEDR-00hReserved
6INTSELCMPR/W0hEPWMxINT Compare Register Selection Options

0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to CMPB when the timer is incrementing / Enable event: time-base counter equal to CMPB when the timer is decrementing to INTSEL selection mux.
1: Enable event time-base counter equal to CMPC when the timer is incrementing / Enable event time-base counter equal to CMPC when the timer is decrementing / Enable event: time-base counter equal to CMPD when the timer is incrementing / Enable event: time-base counter equal to CMPD when the timer is decrementing to INTSEL selection mux.

Reset type: SYSRSn

5SOCBSELCMPR/W0hEPWMxSOCB Compare Register Selection Options

0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to CMPB when the timer is incrementing / Enable event: time-base counter equal to CMPB when the timer is decrementing to SOCBSEL selection mux.
1: Enable event time-base counter equal to CMPC when the timer is incrementing / Enable event time-base counter equal to CMPC when the timer is decrementing / Enable event: time-base counter equal to CMPD when the timer is incrementing / Enable event: time-base counter equal to CMPD when the timer is decrementing to SOCBSEL selection mux.

Reset type: SYSRSn

4SOCASELCMPR/W0hEPWMxSOCA Compare Register Selection Options

0: Enable event time-base counter equal to CMPA when the timer is incrementing / Enable event time-base counter equal to CMPA when the timer is decrementing / Enable event: time-base counter equal to CMPB when the timer is incrementing / Enable event: time-base counter equal to CMPB when the timer is decrementing to SOCASEL selection mux.
1: Enable event time-base counter equal to CMPC when the timer is incrementing / Enable event time-base counter equal to CMPC when the timer is decrementing / Enable event: time-base counter equal to CMPD when the timer is incrementing / Enable event: time-base counter equal to CMPD when the timer is decrementing to SOCASEL selection mux.

Reset type: SYSRSn

3INTENR/W0hEnable ePWM Interrupt (EPWMx_INT) Generation

0: Disable EPWMx_INT generation
1: Enable EPWMx_INT generation

Reset type: SYSRSn

2-0INTSELR/W0hePWM Interrupt (EPWMx_INT) Selection Options

000: Reserved
001: Enable event time-base counter equal to zero. (TBCTR = 0x00)
010: Enable event time-base counter equal to period (TBCTR = TBPRD)
011: Enable event time-base counter equal to zero or period (TBCTR = 0x00 or TBCTR = TBPRD). This mode is useful in up-down count mode.
100: Enable event time-base counter equal to CMPA when the timer is incrementing or CMPC when the timer is incrementing
101: Enable event time-base counter equal to CMPA when the timer is decrementing or CMPC when the timer is decrementing
110: Enable event: time-base counter equal to CMPB when the timer is incrementing or CMPD when the timer is incrementing
111: Enable event: time-base counter equal to CMPB when the timer is decrementing or CMPD when the timer is decrementing (*) Event selected is determined by INTSELCMP bit.

Reset type: SYSRSn

17.17.2.60 ETPS Register (Offset = A6h) [Reset = 0000h]

ETPS is shown in Figure 17-152 and described in Table 17-83.

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Event Trigger Pre-Scale Register

Figure 17-152 ETPS Register
15141312111098
SOCBCNTSOCBPRDSOCACNTSOCAPRD
R-0hR/W-0hR-0hR/W-0h
76543210
RESERVEDSOCPSSELINTPSSELINTCNTINTPRD
R-0-0hR/W-0hR/W-0hR-0hR/W-0h
Table 17-83 ETPS Register Field Descriptions
BitFieldTypeResetDescription
15-14SOCBCNTR0hePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Counter Register

These bits indicate how many selected ETSEL[SOCBSEL] events have occurred:

00: No events have occurred.
01: 1 event has occurred.
10: 2 events have occurred.
11: 3 events have occurred.

Reset type: SYSRSn

13-12SOCBPRDR/W0hePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Period Select

These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an EPWMxSOCB pulse is generated. To be generated, the pulse must be enabled (ETSEL[SOCBEN] = 1). The SOCB pulse will be generated even if the status flag is set from a previous start of conversion (ETFLG[SOCB] = 1). Once the SOCB pulse is generated, the ETPS[SOCBCNT] bits will automatically be cleared.

00: Disable the SOCB event counter. No EPWMxSOCB pulse will be generated
01: Generate the EPWMxSOCB pulse on the first event: ETPS[SOCBCNT] = 0,1
10: Generate the EPWMxSOCB pulse on the second event: ETPS[SOCBCNT] = 1,0
11: Generate the EPWMxSOCB pulse on the third event: ETPS[SOCBCNT] = 1,1

Reset type: SYSRSn

11-10SOCACNTR0hePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Counter Register

These bits indicate how many selected ETSEL[SOCASEL] events have occurred:

00: No events have occurred.
01: 1 event has occurred.
10: 2 events have occurred.
11: 3 events have occurred.

Reset type: SYSRSn

9-8SOCAPRDR/W0hePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Period Select

These bits determine how many selected ETSEL[SOCASEL] events need to occur before an EPWMxSOCA pulse is generated. To be generated, the pulse must be enabled (ETSEL[SOCAEN] = 1). The SOCA pulse will be generated even if the status flag is set from a previous start of conversion (ETFLG[SOCA] = 1). Once the SOCA pulse is generated, the ETPS[SOCACNT] bits will automatically be cleared.

00: Disable the SOCA event counter. No EPWMxSOCA pulse will be generated
01: Generate the EPWMxSOCA pulse on the first event: ETPS[SOCACNT] = 0,1
10: Generate the EPWMxSOCA pulse on the second event: ETPS[SOCACNT] = 1,0
11: Generate the EPWMxSOCA pulse on the third event: ETPS[SOCACNT] = 1,1

Reset type: SYSRSn

7-6RESERVEDR-00hReserved
5SOCPSSELR/W0hEPWMxSOC A/B Pre-Scale Selection Bits

0: Selects ETPS [SOCACNT/SOCBCNT] and [SOCAPRD/SOCBPRD] registers to determine frequency of events (SOC pulse once every 0-3 events).
1: Selects ETSOCPS [SOCACNT2/SOCBCNT2] and [SOCAPRD2/SOCBPRD2] registers to determine frequency of events (SOC pulse once every 0-15 events).

Reset type: SYSRSn

4INTPSSELR/W0hEPWMxINTn Pre-Scale Selection Bits

0: Selects ETPS [INTCNT, and INTPRD] registers to determine frequency of events (interrupt once every 0-3 events).
1: Selects ETINTPS [ INTCNT2, and INTPRD2 ] registers to determine frequency of events (interrupt once every 0-15 events).

Reset type: SYSRSn

3-2INTCNTR0hePWM Interrupt Event (EPWMx_INT) Counter Register

These bits indicate how many selected ETSEL[INTSEL] events have occurred. These bits are automatically cleared when an interrupt pulse is generated. If interrupts are disabled, ETSEL[INT] = 0 or the interrupt flag is set, ETFLG[INT] = 1, the counter will stop counting events when it reaches the period value ETPS[INTCNT] = ETPS[INTPRD].

00: No events have occurred.
01: 1 event has occurred.
10: 2 events have occurred.
11: 3 events have occurred.

Reset type: SYSRSn

1-0INTPRDR/W0hePWM Interrupt (EPWMx_INT) Period Select

These bits determine how many selected ETSEL[INTSEL] events need to occur before an interrupt is generated. To be generated, the interrupt must be enabled (ETSEL[INT] = 1). If the interrupt status flag is set from a previous interrupt (ETFLG[INT] = 1) then no interrupt will be generated until the flag is cleared via the ETCLR[INT] bit. This allows for one interrupt to be pending while another is still being serviced. Once the interrupt is generated, the ETPS[INTCNT] bits will automatically be cleared.

Writing a INTPRD value that is the same as the current counter value will trigger an interrupt if it is enabled and the status flag is clear.

Writing a INTPRD value that is less than the current counter value will result in an undefined state. If a counter event occurs at the same instant as a new zero or non-zero INTPRD value is written, the counter is incremented.

00: Disable the interrupt event counter. No interrupt will be generated and ETFRC[INT] is ignored.
01: Generate an interrupt on the first event INTCNT = 01 (first event)
10: Generate interrupt on ETPS[INTCNT] = 1,0 (second event)
11: Generate interrupt on ETPS[INTCNT] = 1,1 (third event)

Reset type: SYSRSn

17.17.2.61 ETFLG Register (Offset = A8h) [Reset = 0000h]

ETFLG is shown in Figure 17-153 and described in Table 17-84.

Return to the Summary Table.

Event Trigger Flag Register

Figure 17-153 ETFLG Register
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDSOCBSOCARESERVEDINT
R-0-0hR-0hR-0hR-0-0hR-0h
Table 17-84 ETFLG Register Field Descriptions
BitFieldTypeResetDescription
15-4RESERVEDR-00hReserved
3SOCBR0hLatched ePWM ADC Start-of-Conversion A (EPWMxSOCB) Status Flag

Unlike the ETFLG[INT] flag, the EPWMxSOCB output will continue to pulse even if the flag bit is set.

0: Indicates no event occurred
1: Indicates that a start of conversion pulse was generated on EPWMxSOCB. The EPWMxSOCB output will continue to be generated even if the flag bit is set.

Reset type: SYSRSn

2SOCAR0hLatched ePWM ADC Start-of-Conversion A (EPWMxSOCA) Status Flag

Unlike the ETFLG[INT] flag, the EPWMxSOCA output will continue to pulse even if the flag bit is set.

0: Indicates no event occurred
1: Indicates that a start of conversion pulse was generated on EPWMxSOCA. The EPWMxSOCA output will continue to be generated even if the flag bit is set.

Reset type: SYSRSn

1RESERVEDR-00hReserved
0INTR0hLatched ePWM Interrupt (EPWMx_INT) Status Flag

0: Indicates no event occurred
1: Indicates that an ePWMx interrupt (EPWMx_INT) was generated. No further interrupts will be generated until the flag bit is cleared. Up to one interrupt can be pending while the ETFLG[INT] bit is still set. If an interrupt is pending, it will not be generated until after the ETFLG[INT] bit is cleared.

Reset type: SYSRSn

17.17.2.62 ETCLR Register (Offset = AAh) [Reset = 0000h]

ETCLR is shown in Figure 17-154 and described in Table 17-85.

Return to the Summary Table.

Event Trigger Clear Register

Figure 17-154 ETCLR Register
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDSOCBSOCARESERVEDINT
R-0-0hR-0/W1S-0hR-0/W1S-0hR-0-0hR-0/W1S-0h
Table 17-85 ETCLR Register Field Descriptions
BitFieldTypeResetDescription
15-4RESERVEDR-00hReserved
3SOCBR-0/W1S0hePWM ADC Start-of-Conversion A (EPWMxSOCB) Flag Clear Bit

0: Writing a 0 has no effect. Always reads back a 0
1: Clears the ETFLG[SOCB] flag bit

Reset type: SYSRSn

2SOCAR-0/W1S0hePWM ADC Start-of-Conversion A (EPWMxSOCA) Flag Clear Bit

0: Writing a 0 has no effect. Always reads back a 0
1: Clears the ETFLG[SOCA] flag bit

Reset type: SYSRSn

1RESERVEDR-00hReserved
0INTR-0/W1S0hePWM Interrupt (EPWMx_INT) Flag Clear Bit

0: Writing a 0 has no effect. Always reads back a 0
1: Clears the ETFLG[INT] flag bit and enable further interrupts pulses to be generated

Reset type: SYSRSn

17.17.2.63 ETFRC Register (Offset = ACh) [Reset = 0000h]

ETFRC is shown in Figure 17-155 and described in Table 17-86.

Return to the Summary Table.

Event Trigger Force Register

Figure 17-155 ETFRC Register
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDSOCBSOCARESERVEDINT
R-0-0hR-0/W1S-0hR-0/W1S-0hR-0-0hR-0/W1S-0h
Table 17-86 ETFRC Register Field Descriptions
BitFieldTypeResetDescription
15-4RESERVEDR-00hReserved
3SOCBR-0/W1S0hSOCB Force Bit

The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless.

0: Writing 0 to this bit will be ignored. Always reads back a 0.
1: Generates a pulse on EPWMxSOCB and set the SOCBFLG bit. This bit is used for test purposes.

Reset type: SYSRSn

2SOCAR-0/W1S0hSOCA Force Bit

The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless.

0: Writing 0 to this bit will be ignored. Always reads back a 0.
1: Generates a pulse on EPWMxSOCA and set the SOCAFLG bit. This bit is used for test purposes.

Reset type: SYSRSn

1RESERVEDR-00hReserved
0INTR-0/W1S0hINT Force Bit

The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless.

0: Writing 0 to this bit will be ignored. Always reads back a 0.
1: Generates an interrupt on EPWMxINT and set the INT flag bit. This bit is used for test purposes.

Reset type: SYSRSn

17.17.2.64 ETINTPS Register (Offset = AEh) [Reset = 0000h]

ETINTPS is shown in Figure 17-156 and described in Table 17-87.

Return to the Summary Table.

Event-Trigger Interrupt Pre-Scale Register

Figure 17-156 ETINTPS Register
15141312111098
RESERVED
R-0-0h
76543210
INTCNT2INTPRD2
R-0hR/W-0h
Table 17-87 ETINTPS Register Field Descriptions
BitFieldTypeResetDescription
15-8RESERVEDR-00hReserved
7-4INTCNT2R0hEPWMxINT Counter 2

When ETPS[INTPSSEL]=1, these bits indicate how many selected events have occurred:

0000: No events
0001: 1 event
0010: 2 events
0011: 3 events
0100: 4 events
...
1111: 15 events

Reset type: SYSRSn

3-0INTPRD2R/W0hEPWMxINT Period 2 Select

When ETPS[INTPSSEL] = 1, these bits select how many selected events need to occur before an interrupt is generated:

0000: Disable counter
0001: Generate interrupt on INTCNT = 1 (first event)
0010: Generate interrupt on INTCNT = 2 (second event)
0011: Generate interrupt on INTCNT = 3 (third event)
0100: Generate interrupt on INTCNT = 4 (fourth event)
...
1111: Generate interrupt on INTCNT = 15 (fifteenth event)

Reset type: SYSRSn

17.17.2.65 ETSOCPS Register (Offset = B0h) [Reset = 0000h]

ETSOCPS is shown in Figure 17-157 and described in Table 17-88.

Return to the Summary Table.

Event-Trigger SOC Pre-Scale Register

Figure 17-157 ETSOCPS Register
15141312111098
SOCBCNT2SOCBPRD2
R-0hR/W-0h
76543210
SOCACNT2SOCAPRD2
R-0hR/W-0h
Table 17-88 ETSOCPS Register Field Descriptions
BitFieldTypeResetDescription
15-12SOCBCNT2R0hEPWMxSOCB Counter 2

When ETPS[SOCPSSEL] = 1, these bits indicate how many selected events have occurred:

0000: No events
0001: 1 event
0010: 2 events
0011: 3 events
0100: 4 events
...
1111: 15 events

Reset type: SYSRSn

11-8SOCBPRD2R/W0hEPWMxSOCB Period 2 Select

When ETPS[SOCPSSEL] = 1, these bits select how many selected event need to occur before an SOCB pulse is generated:

0000: Disable counter
0001: Generate SOC pulse on SOCBCNT2 = 1 (first event)
0010: Generate SOC pulse on SOCBCNT2 = 2 (second event)
0011: Generate SOC pulse on SOCBCNT2 = 3 (third event)
0100: Generate SOC pulse on SOCBCNT2 = 4 (fourth event)
...
1111: Generate SOC pulse on SOCBCNT2 = 15 (fifteenth event)

Reset type: SYSRSn

7-4SOCACNT2R0hEPWMxSOCA Counter 2

When ETPS[SOCPSSEL] = 1, these bits indicate how many selected events have occurred:

0000: No events
0001: 1 event
0010: 2 events
0011: 3 events
0100: 4 events
...
1111: 15 events

Reset type: SYSRSn

3-0SOCAPRD2R/W0hEPWMxSOCA Period 2 Select

When ETPS[SOCPSSEL] = 1, these bits select how many selected event need to occur before an SOCA pulse is generated:

0000: Disable counter
0001: Generate SOC pulse on SOCACNT2 = 1 (first event)
0010: Generate SOC pulse on SOCACNT2 = 2 (second event)
0011: Generate SOC pulse on SOCACNT2 = 3 (third event)
0100: Generate SOC pulse on SOCACNT2 = 4 (fourth event)
...
1111: Generate SOC pulse on SOCACNT2 = 15 (fifteenth event)

Reset type: SYSRSn

17.17.2.66 ETCNTINITCTL Register (Offset = B2h) [Reset = 0000h]

ETCNTINITCTL is shown in Figure 17-158 and described in Table 17-89.

Return to the Summary Table.

Event-Trigger Counter Initialization Control Register

Figure 17-158 ETCNTINITCTL Register
15141312111098
SOCBINITENSOCAINITENINTINITENSOCBINITFRCSOCAINITFRCINTINITFRCRESERVED
R/W-0hR/W-0hR/W-0hR-0/W1S-0hR-0/W1S-0hR-0/W1S-0hR-0-0h
76543210
RESERVED
R-0-0h
Table 17-89 ETCNTINITCTL Register Field Descriptions
BitFieldTypeResetDescription
15SOCBINITENR/W0hEPWMxSOCB Counter 2 Initialization Enable

0: Has no effect.
1: Enable initialization of EPWMxSOCB counter with contents of ETCNTINIT[SOCBINIT] on a SYNC event or software force.

Reset type: SYSRSn

14SOCAINITENR/W0hEPWMxSOCA Counter 2 Initialization Enable

0: Has no effect.
1: Enable initialization of EPWMxSOCA counter with contents of ETCNTINIT[SOCAINIT] on a SYNC event or software force.

Reset type: SYSRSn

13INTINITENR/W0hEPWMxINT Counter 2 Initialization Enable

0: Has no effect.
1: Enable initialization of EPWMxINT counter 2 with contents of ETCNTINIT[INTINIT] on a SYNC event or software force.

Reset type: SYSRSn

12SOCBINITFRCR-0/W1S0hEPWMxSOCB Counter 2 Initialization Force

0: Has no effect.
1: This bit forces the ET EPWMxSOCB counter to be initialized with the contents of ETCNTINIT[SOCBINIT].

Reset type: SYSRSn

11SOCAINITFRCR-0/W1S0hEPWMxSOCA Counter 2 Initialization Force

0: Has no effect.
1: This bit forces the ET EPWMxSOCA counter to be initialized with the contents of ETCNTINIT[SOCAINIT].

Reset type: SYSRSn

10INTINITFRCR-0/W1S0hEPWMxINT Counter 2 Initialization Force

0: Has no effect.
1: This bit forces the ET EPWMxINT counter to be initialized with the contents of ETCNTINIT[INTINIT].

Reset type: SYSRSn

9-0RESERVEDR-00hReserved

17.17.2.67 ETCNTINIT Register (Offset = B4h) [Reset = 0000h]

ETCNTINIT is shown in Figure 17-159 and described in Table 17-90.

Return to the Summary Table.

Event-Trigger Counter Initialization Register

Figure 17-159 ETCNTINIT Register
15141312111098
RESERVEDSOCBINIT
R-0hR/W-0h
76543210
SOCAINITINTINIT
R/W-0hR/W-0h
Table 17-90 ETCNTINIT Register Field Descriptions
BitFieldTypeResetDescription
15-12RESERVEDR0hReserved
11-8SOCBINITR/W0hEPWMxSOCB Counter 2 Initialization Bits

The ET EPWMxSOCB counter is initialized with the contents of this register on an ePWM SYNC event or a software force.

Reset type: SYSRSn

7-4SOCAINITR/W0hEPWMxSOCA Counter 2 Initialization Bits

The ET EPWMxSOCA counter is initialized with the contents of this register on an ePWM SYNC event or a software force.

Reset type: SYSRSn

3-0INTINITR/W0hEPWMxINT Counter 2 Initialization Bits

The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force.

Reset type: SYSRSn

17.17.2.68 DCTRIPSEL Register (Offset = C0h) [Reset = 0000h]

DCTRIPSEL is shown in Figure 17-160 and described in Table 17-91.

Return to the Summary Table.

Digital Compare Trip Select Register

Figure 17-160 DCTRIPSEL Register
15141312111098
DCBLCOMPSELDCBHCOMPSEL
R/W-0hR/W-0h
76543210
DCALCOMPSELDCAHCOMPSEL
R/W-0hR/W-0h
Table 17-91 DCTRIPSEL Register Field Descriptions
BitFieldTypeResetDescription
15-12DCBLCOMPSELR/W0hDigital Compare B Low Input Select Bits

0000: TRIPIN1
0001: TRIPIN2
0010: TRIPIN3
0011: TRIPIN4
...
1011: TRIPIN12
1100: Reserved
1101: TRIPIN14
1110: TRIPIN15
1111: Trip combination input (all trip inputs selected by DCBLTRIPSEL register ORed together)

Reset type: SYSRSn

11-8DCBHCOMPSELR/W0hDigital Compare B High Input Select Bits

0000: TRIPIN1
0001: TRIPIN2
0010: TRIPIN3
0011: TRIPIN4
...
1011: TRIPIN12
1100: Reserved
1101: TRIPIN14
1110: TRIPIN15
1111: Trip combination input (all trip inputs selected by DCBHTRIPSEL register ORed together)

Reset type: SYSRSn

7-4DCALCOMPSELR/W0hDigital Compare A Low Input Select Bits

0000: TRIPIN1
0001: TRIPIN2
0010: TRIPIN3
0011: TRIPIN4
...
1011: TRIPIN12
1100: Reserved
1101: TRIPIN14
1110: TRIPIN15
1111: Trip combination input (all trip inputs selected by DCALTRIPSEL register ORed together)

Reset type: SYSRSn

3-0DCAHCOMPSELR/W0hDigital Compare A High Input Select Bits

0000: TRIPIN1
0001: TRIPIN2
0010: TRIPIN3
0011: TRIPIN4
...
1011: TRIPIN12
1100: Reserved
1101: TRIPIN14
1110: TRIPIN15
1111: Trip combination input (all trip inputs selected by DCAHTRIPSEL register ORed together)

Reset type: SYSRSn

17.17.2.69 DCACTL Register (Offset = C3h) [Reset = 0000h]

DCACTL is shown in Figure 17-161 and described in Table 17-92.

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Digital Compare A Control Register

Figure 17-161 DCACTL Register
15141312111098
EVT2LATEVT2LATCLRSELEVT2LATSELRESERVEDEVT2FRCSYNCSELEVT2SRCSEL
R-0hR/W-0hR/W-0hR-0-0hR/W-0hR/W-0h
76543210
EVT1LATEVT1LATCLRSELEVT1LATSELEVT1SYNCEEVT1SOCEEVT1FRCSYNCSELEVT1SRCSEL
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 17-92 DCACTL Register Field Descriptions
BitFieldTypeResetDescription
15EVT2LATR0hIndicates the status of DCAEVT2LAT signal.
0 : The DCAEVT2LAT latch is cleared.
1 : The DCAEVT2LAT latch is set.

Reset type: SYSRSn

14-13EVT2LATCLRSELR/W0hDCAEVT2 Latched clear source select:
00: CNT_ZERO event clears DCAEVT2 latch.
01: PRD_EQ event clears DCAEVT2 latch.
10: CNT_ZERO event or PRD_EQ event clears DCAEVT2 latch.
11: Reserved.

Reset type: SYSRSn

12EVT2LATSELR/W0hDCAEVT2 Latched signal select:
0: Does not select the DCAEVT2 latched signal as source of DCAEVT2.force.
1: Selects the DCAEVT2 latched signal as source of DCAEVT2.force.

Reset type: SYSRSn

11-10RESERVEDR-00hReserved
9EVT2FRCSYNCSELR/W0hDCAEVT2 Force Synchronization Signal Select

0: Source is synchronized with EPWMCLK
1: Source is passed through asynchronously

Reset type: SYSRSn

8EVT2SRCSELR/W0hDCAEVT2 Source Signal Select

0: Source Is DCAEVT2 Signal
1: Source Is DCEVTFILT Signal

Reset type: SYSRSn

7EVT1LATR0hIndicates the status of DCAEVT1LAT signal.
0 : The DCAEVT1LAT latch is cleared.
1 : The DCAEVT1LAT latch is set.

Reset type: SYSRSn

6-5EVT1LATCLRSELR/W0hDCAEVT1 Latched clear source select:
00: CNT_ZERO event clears DCAEVT1 latch.
01: PRD_EQ event clears DCAEVT1 latch.
10: CNT_ZERO event or PRD_EQ event clears DCAEVT1 latch.
11 : Reserved.

Reset type: SYSRSn

4EVT1LATSELR/W0hDCAEVT1 Latched signal select:
0: Does not select the DCAEVT1 latched signal as source of DCAEVT1.force.
1: Selects the DCAEVT1 latched signal as source of DCAEVT1.force.

Reset type: SYSRSn

3EVT1SYNCER/W0hDCAEVT1 SYNC, Enable/Disable

0: SYNC Generation Disabled
1: SYNC Generation Enabled

Reset type: SYSRSn

2EVT1SOCER/W0hDCAEVT1 SOC, Enable/Disable

0: SOC Generation Disabled
1: SOC Generation Enabled

Reset type: SYSRSn

1EVT1FRCSYNCSELR/W0hDCAEVT1 Force Synchronization Signal Select

0: Source is synchronized with EPWMCLK
1: Source is passed through asynchronously

Reset type: SYSRSn

0EVT1SRCSELR/W0hDCAEVT1 Source Signal Select

0: Source Is DCAEVT1 Signal
1: Source Is DCEVTFILT Signal

Reset type: SYSRSn

17.17.2.70 DCBCTL Register (Offset = C4h) [Reset = 0000h]

DCBCTL is shown in Figure 17-162 and described in Table 17-93.

Return to the Summary Table.

Digital Compare B Control Register

Figure 17-162 DCBCTL Register
15141312111098
EVT2LATEVT2LATCLRSELEVT2LATSELRESERVEDEVT2FRCSYNCSELEVT2SRCSEL
R-0hR/W-0hR/W-0hR-0-0hR/W-0hR/W-0h
76543210
EVT1LATEVT1LATCLRSELEVT1LATSELEVT1SYNCEEVT1SOCEEVT1FRCSYNCSELEVT1SRCSEL
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 17-93 DCBCTL Register Field Descriptions
BitFieldTypeResetDescription
15EVT2LATR0hIndicates the status of DCBEVT2LAT signal.
0 The DCBEVT2LAT latch is cleared.
1 The DCBEVT2LAT latch is set.

Reset type: SYSRSn

14-13EVT2LATCLRSELR/W0hDCBEVT2 Latched clear source select:
00 CNT_ZERO event clears DCBEVT2 latch.
01 PRD_EQ event clears DCBEVT2 latch.
10 CNT_ZERO event or PRD_EQ event clears DCBEVT2 latch.
11 Reserved.

Reset type: SYSRSn

12EVT2LATSELR/W0hDCBEVT2 Latched signal select:
0 Does not select the DCBEVT2 latched signal (Refer figure 'Modifications to DCBEVT1.force/DCBEVT2.force generation.') as source of DCBEVT2.force.
1 Selects the DCBEVT2 latched signal as source of DCBEVT2.force.

Reset type: SYSRSn

11-10RESERVEDR-00hReserved
9EVT2FRCSYNCSELR/W0hDCBEVT2 Force Synchronization Signal Select

0: Source is synchronized with EPWMCLK
1: Source is passed through asynchronously

Reset type: SYSRSn

8EVT2SRCSELR/W0hDCBEVT2 Source Signal Select

0: Source Is DCBEVT2 Signal
1: Source Is DCEVTFILT Signal

Reset type: SYSRSn

7EVT1LATR0hIndicates the status of DCBEVT1LAT signal.
0 The DCBEVT1LAT latch is cleared.
1 The DCBEVT1LAT latch is set.

Reset type: SYSRSn

6-5EVT1LATCLRSELR/W0hDCBEVT1 Latched clear source select:
00 CNT_ZERO event clears DCBEVT1 latch.
01 PRD_EQ event clears DCBEVT1 latch.
10 CNT_ZERO event or PRD_EQ event clears DCBEVT1 latch.
11 Reserved.

Reset type: SYSRSn

4EVT1LATSELR/W0hDCBEVT1 Latched signal select:
0 Does not select the DCBEVT1 latched signal (Refer figure 'Modifications to DCBEVT1.force/DCBEVT2.force generation.') as source of DCBEVT1.force.
1 Selects the DCBEVT1 latched signal as source of DCBEVT1.force.

Reset type: SYSRSn

3EVT1SYNCER/W0hDCBEVT1 SYNC, Enable/Disable

0: SYNC Generation Disabled
1: SYNC Generation Enabled

Reset type: SYSRSn

2EVT1SOCER/W0hDCBEVT1 SOC, Enable/Disable

0: SOC Generation Disabled
1: SOC Generation Enabled

Reset type: SYSRSn

1EVT1FRCSYNCSELR/W0hDCBEVT1 Force Synchronization Signal Select

0: Source is synchronized with EPWMCLK
1: Source is passed through asynchronously

Reset type: SYSRSn

0EVT1SRCSELR/W0hDCBEVT1 Source Signal Select

0: Source Is DCBEVT1 Signal
1: Source Is DCEVTFILT Signal

Reset type: SYSRSn

17.17.2.71 DCFCTL Register (Offset = C7h) [Reset = 0000h]

DCFCTL is shown in Figure 17-163 and described in Table 17-94.

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Digital Compare Filter Control Register

Figure 17-163 DCFCTL Register
15141312111098
EDGESTATUSEDGECOUNTEDGEMODE
R-0hR/W-0hR/W-0h
76543210
RESERVEDEDGEFILTSELPULSESELBLANKINVBLANKESRCSEL
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 17-94 DCFCTL Register Field Descriptions
BitFieldTypeResetDescription
15-13EDGESTATUSR0hEdge Status:
These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT, the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The edge counter can be reset by writing 000 to the EDGECOUNT value:

Reset type: SYSRSn

12-10EDGECOUNTR/W0hEdge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal:
000: no edges, reset current EDGESTATUS bits to 0,0,0
001: 1 edge
010: 2 edges
011: 3 edges
100: 4 edges
101: 5 edges
110: 6 edges
111: 7 edges

Reset type: SYSRSn

9-8EDGEMODER/W0hEdge Mode Select:
00: Low To High Edge
01: High To Low Edge
10: Both Edges
11: Reserved

Reset type: SYSRSn

7RESERVEDR-00hReserved
6EDGEFILTSELR/W0hEdge Filter Select:
0: Edge Filter Not Selected
1: Edge Filter Selected

Reset type: SYSRSn

5-4PULSESELR/W0hPulse Select For Blanking & Capture Alignment

00: Time-base counter equal to period (TBCTR = TBPRD)
01: Time-base counter equal to zero (TBCTR = 0x00)
10: Time-base counter equal to zero (TBCTR = 0x00) or period (TBCTR = TBPRD)
11: Reserved

Reset type: SYSRSn

3BLANKINVR/W0hBlanking Window Inversion

0: Blanking window not inverted
1: Blanking window inverted

Reset type: SYSRSn

2BLANKER/W0hBlanking Window Enable/Disable

0: Blanking window is disabled
1: Blanking window is enabled

Reset type: SYSRSn

1-0SRCSELR/W0hFilter Block Signal Source Select

00: Source Is DCAEVT1 Signal
01: Source Is DCAEVT2 Signal
10: Source Is DCBEVT1 Signal
11: Source Is DCBEVT2 Signal

Reset type: SYSRSn

17.17.2.72 DCCAPCTL Register (Offset = C8h) [Reset = 0000h]

DCCAPCTL is shown in Figure 17-164 and described in Table 17-95.

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Digital Compare Capture Control Register

Figure 17-164 DCCAPCTL Register
15141312111098
CAPMODECAPCLRCAPSTSRESERVED
R/W-0hR-0/W1S-0hR-0hR-0-0h
76543210
RESERVEDSHDWMODECAPE
R-0-0hR/W-0hR/W-0h
Table 17-95 DCCAPCTL Register Field Descriptions
BitFieldTypeResetDescription
15CAPMODER/W0hCounter Capture Mode

0: When a DCEVTFILT occurs and the counter capture is enabled, then the current TBCNT value is captured in the active register. When the respective trip event occurs, further trip (capture) events are ignored until the next PRD_eq or CNT_zero event (as selected by the PULSESEL bit in the DCFCTL register) re-triggers the capture mechanism.

If active mode is enabled, via SHDWMODE bit in DCCAPCTL register, CPU reads of this register will return the active register value.

If shadow mode is enabled, via SHDWMODE bit in DCCAPCTL register, the active register is copied to the shadow register on the PRD_eq or CNT_zero event (whichever is selected by PULSESEL bit in DCFCTL register). CPU reads of this register will return the shadow register value.

1: When a DCEVTFILT occurs and the counter capture is enabled, then the current TBCNT value is captured in the active register. When the respective trip event occurs - it will set the CAPSTS flag and further trip (capture) events are ignored until this bit is cleared. CAPSTS can be cleared by writing to CAPCLR bit in DCCAPCTL register and it re-triggers the capture mechanism.

If active mode is enabled, via SHDWMODE bit in DCCAPCTL register, CPU reads of this register will return the active register value.

If shadow mode is enabled, via SHDWMODE bit in DCCAPCTL register, the active register is copied to the shadow register on the PRD_eq or CNT_zero event (whichever is selected by PULSESEL bit in DCFCTL register). CPU reads of this register will return the shadow register value.

Reset type: SYSRSn

14CAPCLRR-0/W1S0hDC Capture Latched Status Clear Flag

0: Writing a 0 has no effect.
1: Writing a 1 will clear this CAPSTS (set) condition.

Reset type: SYSRSn

13CAPSTSR0hLatched Status Flag for Capture Event

0: No DC capture event occurred.
1: A DC capture event has occurred.

Reset type: SYSRSn

12-2RESERVEDR-00hReserved
1SHDWMODER/W0hTBCTR Counter Capture Shadow Select Mode

0: Enable shadow mode. The DCCAP active register is copied to shadow register on a TBCTR = TBPRD or TBCTR = zero event as defined by the DCFCTL[PULSESEL] bit. CPU reads of the DCCAP register will return the shadow register contents.
1: Active Mode. In this mode the shadow register is disabled. CPU reads from the DCCAP register will always return the active register contents.

Reset type: SYSRSn

0CAPER/W0hTBCTR Counter Capture Enable/Disable

0: Disable the time-base counter capture.
1: Enable the time-base counter capture.

Reset type: SYSRSn

17.17.2.73 DCFOFFSET Register (Offset = C9h) [Reset = 0000h]

DCFOFFSET is shown in Figure 17-165 and described in Table 17-96.

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Digital Compare Filter Offset Register

Figure 17-165 DCFOFFSET Register
15141312111098
DCFOFFSET
R/W-0h
76543210
DCFOFFSET
R/W-0h
Table 17-96 DCFOFFSET Register Field Descriptions
BitFieldTypeResetDescription
15-0DCFOFFSETR/W0hBlanking Window Offset

These 16-bits specify the number of TBCLK cycles from the blanking window reference to the point when the blanking window is applied. The blanking window reference is either period or zero as defined by the DCFCTL[PULSESEL] bit. This offset register is shadowed and the active register is loaded at the reference point defined by DCFCTL[PULSESEL]. The offset counter is also initialized and begins to count down when the active register is loaded. When the counter expires, the blanking window is applied. If the blanking window is currently active, then the blanking window counter is restarted.

Reset type: SYSRSn

17.17.2.74 DCFOFFSETCNT Register (Offset = CAh) [Reset = 0000h]

DCFOFFSETCNT is shown in Figure 17-166 and described in Table 17-97.

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Digital Compare Filter Offset Counter Register

Figure 17-166 DCFOFFSETCNT Register
15141312111098
DCFOFFSETCNT
R-0h
76543210
DCFOFFSETCNT
R-0h
Table 17-97 DCFOFFSETCNT Register Field Descriptions
BitFieldTypeResetDescription
15-0DCFOFFSETCNTR0hBlanking Offset Counter

These 16-bits are read only and indicate the current value of the offset counter. The counter counts down to zero and then stops until it is re-loaded on the next period or zero event as defined by the DCFCTL[PULSESEL] bit. The offset counter is not affected by the free/soft emulation bits. That is, it will always continue to count down if the device is halted by a emulation stop.

Reset type: SYSRSn

17.17.2.75 DCFWINDOW Register (Offset = CBh) [Reset = 0000h]

DCFWINDOW is shown in Figure 17-167 and described in Table 17-98.

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Digital Compare Filter Window Register

Figure 17-167 DCFWINDOW Register
15141312111098
DCFWINDOW
R/W-0h
76543210
DCFWINDOW
R/W-0h
Table 17-98 DCFWINDOW Register Field Descriptions
BitFieldTypeResetDescription
15-0DCFWINDOWR/W0hBlanking Window Width

00h: No blanking window is generated.
01-FFFFh: Specifies the width of the blanking window in TBCLK cycles. The blanking window begins when the offset counter expires. When this occurs, the window counter is loaded and begins to count down. If the blanking window is currently active and the offset counter expires, the blanking window counter is not restarted and the blanking window is cut short prematurely. Care should be taken to avoid this situation. The blanking window can cross a PWM period boundary.

Reset type: SYSRSn

17.17.2.76 DCFWINDOWCNT Register (Offset = CCh) [Reset = 0000h]

DCFWINDOWCNT is shown in Figure 17-168 and described in Table 17-99.

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Digital Compare Filter Window Counter Register

Figure 17-168 DCFWINDOWCNT Register
15141312111098
DCFWINDOWCNT
R-0h
76543210
DCFWINDOWCNT
R-0h
Table 17-99 DCFWINDOWCNT Register Field Descriptions
BitFieldTypeResetDescription
15-0DCFWINDOWCNTR0hBlanking Window Counter

These 16 bits are read only and indicate the current value of the window counter. The counter counts down to zero and then stops until it is re-loaded when the offset counter reaches zero again.

Reset type: SYSRSn

17.17.2.77 DCCAP Register (Offset = CFh) [Reset = 0000h]

DCCAP is shown in Figure 17-169 and described in Table 17-100.

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Digital Compare Counter Capture Register

Figure 17-169 DCCAP Register
15141312111098
DCCAP
R-0h
76543210
DCCAP
R-0h
Table 17-100 DCCAP Register Field Descriptions
BitFieldTypeResetDescription
15-0DCCAPR0hDigital Compare Time-Base Counter Capture

To enable time-base counter capture, set the DCCAPCLT[CAPE] bit to 1. If enabled, reflects the value of the time-base counter (TBCTR) on the low to high edge transition of a filtered (DCEVTFLT) event. Further capture events are ignored until the next period or zero as selected by the DCFCTL[PULSESEL] bit. Shadowing of DCCAP is enabled and disabled by the DCCAPCTL[SHDWMODE] bit. By default this register is shadowed.
- If DCCAPCTL[SHDWMODE] = 0, then the shadow is enabled. In this mode, the active register is copied to the shadow register on the TBCTR = TBPRD or TBCTR = zero as defined by the DCFCTL[PULSESEL] bit. CPU reads of this register will return the shadow register value.
- If DCCAPCTL[SHDWMODE] = 1, then the shadow register is disabled. In this mode, CPU reads will return the active register value. The active and shadow registers share the same memory map address.

Reset type: SYSRSn

17.17.2.78 DCAHTRIPSEL Register (Offset = D2h) [Reset = 0000h]

DCAHTRIPSEL is shown in Figure 17-170 and described in Table 17-101.

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Digital Compare AH Trip Select

Figure 17-170 DCAHTRIPSEL Register
15141312111098
RESERVEDTRIPINPUT15TRIPINPUT14RESERVEDTRIPINPUT12TRIPINPUT11TRIPINPUT10TRIPINPUT9
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
TRIPINPUT8TRIPINPUT7TRIPINPUT6TRIPINPUT5TRIPINPUT4TRIPINPUT3TRIPINPUT2TRIPINPUT1
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 17-101 DCAHTRIPSEL Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0hReserved
14TRIPINPUT15R/W0hTRIP Input 15

0: Trip Input 15 not selected as combinational ORed input
1: Trip Input 15 selected as combinational ORed input to DCAH mux

Reset type: SYSRSn

13TRIPINPUT14R/W0hTRIP Input 14

0: Trip Input 14 not selected as combinational ORed input
1: Trip Input 14 selected as combinational ORed input to DCAH mux

Reset type: SYSRSn

12RESERVEDR/W0hReserved
11TRIPINPUT12R/W0hTRIP Input 12

0: Trip Input 12 not selected as combinational ORed input
1: Trip Input 12 selected as combinational ORed input to DCAH mux

Reset type: SYSRSn

10TRIPINPUT11R/W0hTRIP Input 11

0: Trip Input 11 not selected as combinational ORed input
1: Trip Input 11 selected as combinational ORed input to DCAH mux

Reset type: SYSRSn

9TRIPINPUT10R/W0hTRIP Input 10

0: Trip Input 10 not selected as combinational ORed input
1: Trip Input 10 selected as combinational ORed input to DCAH mux

Reset type: SYSRSn

8TRIPINPUT9R/W0hTRIP Input 9

0: Trip Input 9 not selected as combinational ORed input
1: Trip Input 9 selected as combinational ORed input to DCAH mux

Reset type: SYSRSn

7TRIPINPUT8R/W0hTRIP Input 8

0: Trip Input 8 not selected as combinational ORed input
1: Trip Input 8 selected as combinational ORed input to DCAH mux

Reset type: SYSRSn

6TRIPINPUT7R/W0hTRIP Input 7

0: Trip Input 7 not selected as combinational ORed input
1: Trip Input 7 selected as combinational ORed input to DCAH mux

Reset type: SYSRSn

5TRIPINPUT6R/W0hTRIP Input 6

0: Trip Input 6 not selected as combinational ORed input
1: Trip Input 6 selected as combinational ORed input to DCAH mux

Reset type: SYSRSn

4TRIPINPUT5R/W0hTRIP Input 5

0: Trip Input 5 not selected as combinational ORed input
1: Trip Input 5 selected as combinational ORed input to DCAH mux

Reset type: SYSRSn

3TRIPINPUT4R/W0hTRIP Input 4

0: Trip Input 4 not selected as combinational ORed input
1: Trip Input 4 selected as combinational ORed input to DCAH mux

Reset type: SYSRSn

2TRIPINPUT3R/W0hTRIP Input 3

0: Trip Input 3 not selected as combinational ORed input
1: Trip Input 3 selected as combinational ORed input to DCAH mux

Reset type: SYSRSn

1TRIPINPUT2R/W0hTRIP Input 2

0: Trip Input 2 not selected as combinational ORed input
1: Trip Input 2 selected as combinational ORed input to DCAH mux

Reset type: SYSRSn

0TRIPINPUT1R/W0hTRIP Input 1

0: Trip Input 1 not selected as combinational ORed input
1: Trip Input 1 selected as combinational ORed input to DCAH mux

Reset type: SYSRSn

17.17.2.79 DCALTRIPSEL Register (Offset = D3h) [Reset = 0000h]

DCALTRIPSEL is shown in Figure 17-171 and described in Table 17-102.

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Digital Compare AL Trip Select

Figure 17-171 DCALTRIPSEL Register
15141312111098
RESERVEDTRIPINPUT15TRIPINPUT14RESERVEDTRIPINPUT12TRIPINPUT11TRIPINPUT10TRIPINPUT9
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
TRIPINPUT8TRIPINPUT7TRIPINPUT6TRIPINPUT5TRIPINPUT4TRIPINPUT3TRIPINPUT2TRIPINPUT1
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 17-102 DCALTRIPSEL Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0hReserved
14TRIPINPUT15R/W0hTRIP Input 15

0: Trip Input 15 not selected as combinational ORed input
1: Trip Input 15 selected as combinational ORed input to DCAL mux

Reset type: SYSRSn

13TRIPINPUT14R/W0hTRIP Input 14

0: Trip Input 14 not selected as combinational ORed input
1: Trip Input 14 selected as combinational ORed input to DCAL mux

Reset type: SYSRSn

12RESERVEDR/W0hReserved
11TRIPINPUT12R/W0hTRIP Input 12

0: Trip Input 12 not selected as combinational ORed input
1: Trip Input 12 selected as combinational ORed input to DCAL mux

Reset type: SYSRSn

10TRIPINPUT11R/W0hTRIP Input 11

0: Trip Input 11 not selected as combinational ORed input
1: Trip Input 11 selected as combinational ORed input to DCAL mux

Reset type: SYSRSn

9TRIPINPUT10R/W0hTRIP Input 10

0: Trip Input 10 not selected as combinational ORed input
1: Trip Input 10 selected as combinational ORed input to DCAL mux

Reset type: SYSRSn

8TRIPINPUT9R/W0hTRIP Input 9

0: Trip Input 9 not selected as combinational ORed input
1: Trip Input 9 selected as combinational ORed input to DCAL mux

Reset type: SYSRSn

7TRIPINPUT8R/W0hTRIP Input 8

0: Trip Input 8 not selected as combinational ORed input
1: Trip Input 8 selected as combinational ORed input to DCAL mux

Reset type: SYSRSn

6TRIPINPUT7R/W0hTRIP Input 7

0: Trip Input 7 not selected as combinational ORed input
1: Trip Input 7 selected as combinational ORed input to DCAL mux

Reset type: SYSRSn

5TRIPINPUT6R/W0hTRIP Input 6

0: Trip Input 6 not selected as combinational ORed input
1: Trip Input 6 selected as combinational ORed input to DCAL mux

Reset type: SYSRSn

4TRIPINPUT5R/W0hTRIP Input 5

0: Trip Input 5 not selected as combinational ORed input
1: Trip Input 5 selected as combinational ORed input to DCAL mux

Reset type: SYSRSn

3TRIPINPUT4R/W0hTRIP Input 4

0: Trip Input 4 not selected as combinational ORed input
1: Trip Input 4 selected as combinational ORed input to DCAL mux

Reset type: SYSRSn

2TRIPINPUT3R/W0hTRIP Input 3

0: Trip Input 3 not selected as combinational ORed input
1: Trip Input 3 selected as combinational ORed input to DCAL mux

Reset type: SYSRSn

1TRIPINPUT2R/W0hTRIP Input 2

0: Trip Input 2 not selected as combinational ORed input
1: Trip Input 2 selected as combinational ORed input to DCAL mux

Reset type: SYSRSn

0TRIPINPUT1R/W0hTRIP Input 1

0: Trip Input 1 not selected as combinational ORed input
1: Trip Input 1 selected as combinational ORed input to DCAL mux

Reset type: SYSRSn

17.17.2.80 DCBHTRIPSEL Register (Offset = D4h) [Reset = 0000h]

DCBHTRIPSEL is shown in Figure 17-172 and described in Table 17-103.

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Digital Compare BH Trip Select

Figure 17-172 DCBHTRIPSEL Register
15141312111098
RESERVEDTRIPINPUT15TRIPINPUT14RESERVEDTRIPINPUT12TRIPINPUT11TRIPINPUT10TRIPINPUT9
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
TRIPINPUT8TRIPINPUT7TRIPINPUT6TRIPINPUT5TRIPINPUT4TRIPINPUT3TRIPINPUT2TRIPINPUT1
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 17-103 DCBHTRIPSEL Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0hReserved
14TRIPINPUT15R/W0hTRIP Input 15

0: Trip Input 15 not selected as combinational ORed input
1: Trip Input 15 selected as combinational ORed input to DCBH mux

Reset type: SYSRSn

13TRIPINPUT14R/W0hTRIP Input 14

0: Trip Input 14 not selected as combinational ORed input
1: Trip Input 14 selected as combinational ORed input to DCBH mux

Reset type: SYSRSn

12RESERVEDR/W0hReserved
11TRIPINPUT12R/W0hTRIP Input 12

0: Trip Input 12 not selected as combinational ORed input
1: Trip Input 12 selected as combinational ORed input to DCBH mux

Reset type: SYSRSn

10TRIPINPUT11R/W0hTRIP Input 11

0: Trip Input 11 not selected as combinational ORed input
1: Trip Input 11 selected as combinational ORed input to DCBH mux

Reset type: SYSRSn

9TRIPINPUT10R/W0hTRIP Input 10

0: Trip Input 10 not selected as combinational ORed input
1: Trip Input 10 selected as combinational ORed input to DCBH mux

Reset type: SYSRSn

8TRIPINPUT9R/W0hTRIP Input 9

0: Trip Input 9 not selected as combinational ORed input
1: Trip Input 9 selected as combinational ORed input to DCBH mux

Reset type: SYSRSn

7TRIPINPUT8R/W0hTRIP Input 8

0: Trip Input 8 not selected as combinational ORed input
1: Trip Input 8 selected as combinational ORed input to DCBH mux

Reset type: SYSRSn

6TRIPINPUT7R/W0hTRIP Input 7

0: Trip Input 7 not selected as combinational ORed input
1: Trip Input 7 selected as combinational ORed input to DCBH mux

Reset type: SYSRSn

5TRIPINPUT6R/W0hTRIP Input 6

0: Trip Input 6 not selected as combinational ORed input
1: Trip Input 6 selected as combinational ORed input to DCBH mux

Reset type: SYSRSn

4TRIPINPUT5R/W0hTRIP Input 5

0: Trip Input 5 not selected as combinational ORed input
1: Trip Input 5 selected as combinational ORed input to DCBH mux

Reset type: SYSRSn

3TRIPINPUT4R/W0hTRIP Input 4

0: Trip Input 4 not selected as combinational ORed input
1: Trip Input 4 selected as combinational ORed input to DCBH mux

Reset type: SYSRSn

2TRIPINPUT3R/W0hTRIP Input 3

0: Trip Input 3 not selected as combinational ORed input
1: Trip Input 3 selected as combinational ORed input to DCBH mux

Reset type: SYSRSn

1TRIPINPUT2R/W0hTRIP Input 2

0: Trip Input 2 not selected as combinational ORed input
1: Trip Input 2 selected as combinational ORed input to DCBH mux

Reset type: SYSRSn

0TRIPINPUT1R/W0hTRIP Input 1

0: Trip Input 1 not selected as combinational ORed input
1: Trip Input 1 selected as combinational ORed input to DCBH mux

Reset type: SYSRSn

17.17.2.81 DCBLTRIPSEL Register (Offset = D5h) [Reset = 0000h]

DCBLTRIPSEL is shown in Figure 17-173 and described in Table 17-104.

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Digital Compare BL Trip Select

Figure 17-173 DCBLTRIPSEL Register
15141312111098
RESERVEDTRIPINPUT15TRIPINPUT14RESERVEDTRIPINPUT12TRIPINPUT11TRIPINPUT10TRIPINPUT9
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
TRIPINPUT8TRIPINPUT7TRIPINPUT6TRIPINPUT5TRIPINPUT4TRIPINPUT3TRIPINPUT2TRIPINPUT1
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 17-104 DCBLTRIPSEL Register Field Descriptions
BitFieldTypeResetDescription
15RESERVEDR0hReserved
14TRIPINPUT15R/W0hTRIP Input 15

0: Trip Input 15 not selected as combinational ORed input
1: Trip Input 15 selected as combinational ORed input to DCAL mux

Reset type: SYSRSn

13TRIPINPUT14R/W0hTRIP Input 14

0: Trip Input 14 not selected as combinational ORed input
1: Trip Input 14 selected as combinational ORed input to DCAL mux

Reset type: SYSRSn

12RESERVEDR/W0hReserved
11TRIPINPUT12R/W0hTRIP Input 12

0: Trip Input 12 not selected as combinational ORed input
1: Trip Input 12 selected as combinational ORed input to DCAL mux

Reset type: SYSRSn

10TRIPINPUT11R/W0hTRIP Input 11

0: Trip Input 11 not selected as combinational ORed input
1: Trip Input 11 selected as combinational ORed input to DCAL mux

Reset type: SYSRSn

9TRIPINPUT10R/W0hTRIP Input 10

0: Trip Input 10 not selected as combinational ORed input
1: Trip Input 10 selected as combinational ORed input to DCAL mux

Reset type: SYSRSn

8TRIPINPUT9R/W0hTRIP Input 9

0: Trip Input 9 not selected as combinational ORed input
1: Trip Input 9 selected as combinational ORed input to DCAL mux

Reset type: SYSRSn

7TRIPINPUT8R/W0hTRIP Input 8

0: Trip Input 8 not selected as combinational ORed input
1: Trip Input 8 selected as combinational ORed input to DCAL mux

Reset type: SYSRSn

6TRIPINPUT7R/W0hTRIP Input 7

0: Trip Input 7 not selected as combinational ORed input
1: Trip Input 7 selected as combinational ORed input to DCAL mux

Reset type: SYSRSn

5TRIPINPUT6R/W0hTRIP Input 6

0: Trip Input 6 not selected as combinational ORed input
1: Trip Input 6 selected as combinational ORed input to DCAL mux

Reset type: SYSRSn

4TRIPINPUT5R/W0hTRIP Input 5

0: Trip Input 5 not selected as combinational ORed input
1: Trip Input 5 selected as combinational ORed input to DCAL mux

Reset type: SYSRSn

3TRIPINPUT4R/W0hTRIP Input 4

0: Trip Input 4 not selected as combinational ORed input
1: Trip Input 4 selected as combinational ORed input to DCAL mux

Reset type: SYSRSn

2TRIPINPUT3R/W0hTRIP Input 3

0: Trip Input 3 not selected as combinational ORed input
1: Trip Input 3 selected as combinational ORed input to DCAL mux

Reset type: SYSRSn

1TRIPINPUT2R/W0hTRIP Input 2

0: Trip Input 2 not selected as combinational ORed input
1: Trip Input 2 selected as combinational ORed input to DCAL mux

Reset type: SYSRSn

0TRIPINPUT1R/W0hTRIP Input 1

0: Trip Input 1 not selected as combinational ORed input
1: Trip Input 1 selected as combinational ORed input to DCAL mux

Reset type: SYSRSn

17.17.2.82 EPWMLOCK Register (Offset = FAh) [Reset = 00000000h]

EPWMLOCK is shown in Figure 17-174 and described in Table 17-105.

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EPWM Lock Register

Figure 17-174 EPWMLOCK Register
3130292827262524
KEY
R-0/W-0h
2322212019181716
KEY
R-0/W-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDDCLOCKTZCLRLOCKTZCFGLOCKGLLOCKHRLOCK
R-0hR/WOnce-0hR/WOnce-0hR/WOnce-0hR/WOnce-0hR/WOnce-0h
Table 17-105 EPWMLOCK Register Field Descriptions
BitFieldTypeResetDescription
31-16KEYR-0/W0hWrite to this register succeeds only if this field is written with a value of 0xa5a5

Note:
[1] Due to this KEY, only 32-bit writes will succeed (provided the KEY matches). 16-bit writes to the upper or lower half of this register will be ignored

Reset type: SYSRSn

15-5RESERVEDR0hReserved
4DCLOCKR/WOnce0h0:Digital Compare registers from 0xC0 to 0xD9 offsets are protected by EALLOW.
1: Digital Compare registers from 0xC0 to 0xD9 offsets are locked and not writable.

Reset type: SYSRSn

3TZCLRLOCKR/WOnce0h0:Trip Zone registers from 0x97 to 0x9B offsets are protected by EALLOW.
1: Trip Zone registers from 0x97 to 0x9B offsets are locked and not writable.

Reset type: SYSRSn

2TZCFGLOCKR/WOnce0h0:TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are protected by EALLOW.
1: TripZone registers from 0x80 to 0x8D and TZTRIPOUTSEL at 0x9D offsets are locked and not writable.

Reset type: SYSRSn

1GLLOCKR/WOnce0h0:Global Load registers from 0x34 to 0x35 offsets are protected by EALLOW.
1: Global Load registers from 0x34 to 0x35 offsets are locked and not writable

Reset type: SYSRSn

0HRLOCKR/WOnce0h0: HRPWM registers from 0x20 to 0x2D offsets are protected by EALLOW
1: HRPWM registers from 0x20 and 0x2D offsets are locked and not writable.

Reset type: SYSRSn

17.17.2.83 HWVDELVAL Register (Offset = FDh) [Reset = 0000h]

HWVDELVAL is shown in Figure 17-175 and described in Table 17-106.

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Hardware Valley Mode Delay Register

Figure 17-175 HWVDELVAL Register
15141312111098
HWVDELVAL
R-0h
76543210
HWVDELVAL
R-0h
Table 17-106 HWVDELVAL Register Field Descriptions
BitFieldTypeResetDescription
15-0HWVDELVALR0hHardware Valley Delay Value Register

This read only register reflects the hardware delay value calculated by the equations defined in VCAPCTL[VDELAYDIV]. This reflects the latest value from the hardware calculations and can change every time valley capture sequence is triggered and VCAP1 and VCAP2 values are updated.

Reset type: SYSRSn

17.17.2.84 VCNTVAL Register (Offset = FEh) [Reset = 0000h]

VCNTVAL is shown in Figure 17-176 and described in Table 17-107.

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Hardware Valley Counter Register

Figure 17-176 VCNTVAL Register
15141312111098
VCNTVAL
R-0h
76543210
VCNTVAL
R-0h
Table 17-107 VCNTVAL Register Field Descriptions
BitFieldTypeResetDescription
15-0VCNTVALR0hValley Time Base Counter Register

This register reflects the captured VCNT value upon occurrence of STOPEDGE selected in VCNTCFG register.

Reset type: SYSRSn