SPRUIN7C March 2020 – March 2024 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1
Table 14-6 lists the memory-mapped registers for the ANALOG_SUBSYS_REGS registers. All register offset addresses not listed in Table 14-6 should be considered as reserved locations and the register contents should not be modified.
Offset | Acronym | Register Name | Write Protection | Section |
---|---|---|---|---|
60h | TSNSCTL | Temperature Sensor Control Register | EALLOW | Go |
68h | ANAREFCTL | Analog Reference Control Register | EALLOW | Go |
70h | VMONCTL | Voltage Monitor Control Register | EALLOW | Go |
82h | CMPHPMXSEL | Bits to select one of the many sources on CopmHP inputs. Refer to Pimux diagram for details. | EALLOW | Go |
84h | CMPLPMXSEL | Bits to select one of the many sources on CopmLP inputs. Refer to Pimux diagram for details. | EALLOW | Go |
86h | CMPHNMXSEL | Bits to select one of the many sources on CopmHN inputs. Refer to Pimux diagram for details. | EALLOW | Go |
87h | CMPLNMXSEL | Bits to select one of the many sources on CopmLN inputs. Refer to Pimux diagram for details. | EALLOW | Go |
88h | ADCDACLOOPBACK | Enabble loopback from DAC to ADCs | Go | |
8Eh | LOCK | Lock Register | EALLOW | Go |
Complex bit access types are encoded to fit into small table cells. Table 14-7 shows the codes that are used for access types in this section.
Access Type | Code | Description |
---|---|---|
Read Type | ||
R | R | Read |
R-0 | R -0 | Read Returns 0s |
Write Type | ||
W | W | Write |
W1S | W 1S | Write 1 to set |
WOnce | W Once | Write Write once |
WSonce | W Sonce | Write Set once |
Reset or Default Value | ||
-n | Value after reset or the default value | |
Register Array Variables | ||
i,j,k,l,m,n | When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula. | |
y | When this variable is used in a register name, an offset, or an address it refers to the value of a register array. |
TSNSCTL is shown in Figure 14-4 and described in Table 14-8.
Return to the Summary Table.
Temperature Sensor Control Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ENABLE | ||||||
R-0-0h | R/W-0h | ||||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-1 | RESERVED | R-0 | 0h | Reserved |
0 | ENABLE | R/W | 0h | Temperature Sensor Enable. This bit enables the temperature sensor output to the ADC. 0 Disabled 1 Enabled Reset type: SYSRSn |
ANAREFCTL is shown in Figure 14-5 and described in Table 14-9.
Return to the Summary Table.
Analog Reference Control Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | ANAREFC2P5SEL | RESERVED | ANAREFA2P5SEL | ||||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ANAREFCSEL | RESERVED | ANAREFASEL | ||||
R-0-1h | R/W-1h | R/W-1h | R/W-1h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-11 | RESERVED | R-0 | 0h | Reserved |
10 | ANAREFC2P5SEL | R/W | 0h | Analog referenc C 2.5V source select. In internal reference mode, this bit selects which voltage the internal reference buffer drives onto the VREFHI pin. The buffer can drive either 1.65V onto the pin, resulting in a reference range of 0 to 3.3V, or the buffer can drive 2.5V onto the pin, resulting in a reference range of 0 to 2.5V. If switching between these two modes, the user must allow adequate time for the external capacitor to charge to the new voltage before using the ADC or buffered DAC. If multiple VREFHI pins are ganged together (for lower pin-count packages), then the reference voltage select for the ganged pins should always be configured to the same setting. 0 Internal 1.65V reference mode (3.3V reference range) 1 Internal 2.5V reference mode (2.5V reference range) Reset type: XRSn |
9 | RESERVED | R/W | 0h | Reserved |
8 | ANAREFA2P5SEL | R/W | 0h | Analog referenc A 2.5V source select. In internal reference mode, this bit selects which voltage the internal reference buffer drives onto the VREFHI pin. The buffer can drive either 1.65V onto the pin, resulting in a reference range of 0 to 3.3V, or the buffer can drive 2.5V onto the pin, resulting in a reference range of 0 to 2.5V. If switching between these two modes, the user must allow adequate time for the external capacitor to charge to the new voltage before using the ADC or buffered DAC. If multiple VREFHI pins are ganged together (for lower pin-count packages), then the reference voltage select for the ganged pins should always be configured to the same setting. 0 Internal 1.65V reference mode (3.3V reference range) 1 Internal 2.5V reference mode (2.5V reference range) Reset type: XRSn |
7-3 | RESERVED | R-0 | 1h | Reserved |
2 | ANAREFCSEL | R/W | 1h | Analog reference C mode select. This bit selects whether the VREFHIC pin uses internal reference mode (the device drives a voltage onto the VREFHI pin) or external reference mode (the system is expected to drive a voltage into the VREFHI pin). If multiple VREFHI pins are ganged together (for lower pin-count packages), then the mode select for the ganged pins should always be configured to the same setting 0 Internal reference mode 1 External reference mode Reset type: XRSn |
1 | RESERVED | R/W | 1h | Reserved |
0 | ANAREFASEL | R/W | 1h | Analog reference A mode select. This bit selects whether the VREFHIA pin uses internal reference mode (the device drives a voltage onto the VREFHI pin) or external reference mode (the system is expected to drive a voltage into the VREFHI pin). If multiple VREFHI pins are ganged together (for lower pin-count packages), then the mode select for the ganged pins should always be configured to the same setting 0 Internal reference mode 1 External reference mode Reset type: XRSn |
VMONCTL is shown in Figure 14-6 and described in Table 14-10.
Return to the Summary Table.
Voltage Monitor Control Register
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | BORLVMONDIS | ||||||
R-0-0h | R/W-0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | |||||
R-0-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-9 | RESERVED | R-0 | 0h | Reserved |
8 | BORLVMONDIS | R/W | 0h | BORL disable on VDDIO. 0 BORL is enabled on VDDIO, i.e BOR circuit will be triggered if VDDIO goes lower than the lower BOR threshold of VDDIO. 1 BORL is disabled on VDDIO, i.e BOR circuit will not be triggered if VDDIO goes lower than the lower BOR threshold of VDDIO. Reset type: SYSRSn |
7-2 | RESERVED | R-0 | 0h | Reserved |
1 | RESERVED | R/W | 0h | Reserved |
0 | RESERVED | R/W | 0h | Reserved |
CMPHPMXSEL is shown in Figure 14-7 and described in Table 14-11.
Return to the Summary Table.
Bits to select one of the many sources on CopmHP inputs. Refer to Pimux diagram for details.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | |||||
R-0-0h | R/W-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | CMP4HPMXSEL | CMP3HPMXSEL | ||||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CMP3HPMXSEL | CMP2HPMXSEL | CMP1HPMXSEL | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-22 | RESERVED | R-0 | 0h | Reserved |
21-19 | RESERVED | R/W | 0h | Reserved |
18-16 | RESERVED | R/W | 0h | Reserved |
15 | RESERVED | R-0 | 0h | Reserved |
14-12 | RESERVED | R/W | 0h | Reserved |
11-9 | CMP4HPMXSEL | R/W | 0h | CMP4HPMXSEL bits, Refer to the Analog Subsystem chapter. Note: Only values 0 to 4 are valid, rest are reserved Reset type: XRSn |
8-6 | CMP3HPMXSEL | R/W | 0h | CMP3HPMXSEL bits, Refer to the Analog Subsystem chapter. Note: Only values 0 to 4 are valid, rest are reserved Reset type: XRSn |
5-3 | CMP2HPMXSEL | R/W | 0h | CMP2HPMXSEL bits, Refer to the Analog Subsystem chapter. Note: Only values 0 to 4 are valid, rest are reserved Reset type: XRSn |
2-0 | CMP1HPMXSEL | R/W | 0h | CMP1HPMXSEL bits, Refer to the Analog Subsystem chapter. Note: Only values 0 to 4 are valid, rest are reserved Reset type: XRSn |
CMPLPMXSEL is shown in Figure 14-8 and described in Table 14-12.
Return to the Summary Table.
Bits to select one of the many sources on CopmLP inputs. Refer to Pimux diagram for details.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | RESERVED | RESERVED | |||||
R-0-0h | R/W-0h | R/W-0h | |||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | RESERVED | CMP4LPMXSEL | CMP3LPMXSEL | ||||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | ||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CMP3LPMXSEL | CMP2LPMXSEL | CMP1LPMXSEL | |||||
R/W-0h | R/W-0h | R/W-0h | |||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-22 | RESERVED | R-0 | 0h | Reserved |
21-19 | RESERVED | R/W | 0h | Reserved |
18-16 | RESERVED | R/W | 0h | Reserved |
15 | RESERVED | R-0 | 0h | Reserved |
14-12 | RESERVED | R/W | 0h | Reserved |
11-9 | CMP4LPMXSEL | R/W | 0h | CMP4LPMXSEL bits, Refer to the Analog Subsystem chapter. Note: Only values 0 to 4 are valid, rest are reserved Reset type: XRSn |
8-6 | CMP3LPMXSEL | R/W | 0h | CMP3LPMXSEL bits, Refer to the Analog Subsystem chapter. Note: Only values 0 to 4 are valid, rest are reserved Reset type: XRSn |
5-3 | CMP2LPMXSEL | R/W | 0h | CMP2LPMXSEL bits, Refer to the Analog Subsystem chapter. Note: Only values 0 to 4 are valid, rest are reserved Reset type: XRSn |
2-0 | CMP1LPMXSEL | R/W | 0h | CMP1LPMXSEL bits, Refer to the Analog Subsystem chapter. Note: Only values 0 to 4 are valid, rest are reserved Reset type: XRSn |
CMPHNMXSEL is shown in Figure 14-9 and described in Table 14-13.
Return to the Summary Table.
Bits to select one of the many sources on CopmHN inputs. Refer to Pimux diagram for details.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | CMP4HNMXSEL | CMP3HNMXSEL | CMP2HNMXSEL | CMP1HNMXSEL |
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-7 | RESERVED | R-0 | 0h | Reserved |
6 | RESERVED | R/W | 0h | Reserved |
5 | RESERVED | R/W | 0h | Reserved |
4 | RESERVED | R/W | 0h | Reserved |
3 | CMP4HNMXSEL | R/W | 0h | CMP4HNMXSEL bits, Refer to the Analog Subsystem chapter. Reset type: XRSn |
2 | CMP3HNMXSEL | R/W | 0h | CMP3HNMXSEL bits, Refer to the Analog Subsystem chapter. Reset type: XRSn |
1 | CMP2HNMXSEL | R/W | 0h | CMP2HNMXSEL bits, Refer to the Analog Subsystem chapter. Reset type: XRSn |
0 | CMP1HNMXSEL | R/W | 0h | CMP1HNMXSEL bits, Refer to the Analog Subsystem chapter. Reset type: XRSn |
CMPLNMXSEL is shown in Figure 14-10 and described in Table 14-14.
Return to the Summary Table.
Bits to select one of the many sources on CopmLN inputs. Refer to Pimux diagram for details.
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RESERVED | RESERVED | RESERVED | CMP4LNMXSEL | CMP3LNMXSEL | CMP2LNMXSEL | CMP1LNMXSEL |
R-0-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15-7 | RESERVED | R-0 | 0h | Reserved |
6 | RESERVED | R/W | 0h | Reserved |
5 | RESERVED | R/W | 0h | Reserved |
4 | RESERVED | R/W | 0h | Reserved |
3 | CMP4LNMXSEL | R/W | 0h | CMP4LNMXSEL bits, Refer to the Analog Subsystem chapter. Reset type: XRSn |
2 | CMP3LNMXSEL | R/W | 0h | CMP3LNMXSEL bits, Refer to the Analog Subsystem chapter. Reset type: XRSn |
1 | CMP2LNMXSEL | R/W | 0h | CMP2LNMXSEL bits, Refer to the Analog Subsystem chapter. Reset type: XRSn |
0 | CMP1LNMXSEL | R/W | 0h | CMP1LNMXSEL bits, Refer to the Analog Subsystem chapter. Reset type: XRSn |
ADCDACLOOPBACK is shown in Figure 14-11 and described in Table 14-15.
Return to the Summary Table.
Enabble loopback from DAC to ADCs
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
KEY | |||||||
R-0/W-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
KEY | |||||||
R-0/W-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0-0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ENLB2ADCC | RESERVED | ENLB2ADCA | ||||
R-0-0h | R/W-0h | R/W-0h | R/W-0h | ||||
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-16 | KEY | R-0/W | 0h | Write Key. Writes to this register must include the value 0xA5A5 in the KEY bit field to take effect. Otherwise the register will remain as it was prior to the write attempt. Reads will return a 0. Reset type: XRSn |
15-3 | RESERVED | R-0 | 0h | Reserved |
2 | ENLB2ADCC | R/W | 0h | 1 Loops back CMPSS1 DACL output to ADCC. 0 Loop back is broken. Note: Setting this bit to 1, will override the CHSEL specification for the ADC. ADC would sample CMPSS1 DACL output irrespective of the value of CHSEL. Reset type: XRSn |
1 | RESERVED | R/W | 0h | Reserved |
0 | ENLB2ADCA | R/W | 0h | 1 Loops back CMPSS1 DACL output to ADCA. 0 Loop back is broken. Note: Setting this bit to 1, will override the CHSEL specification for the ADC. ADC would sample CMPSS1 DACL output irrespective of the value of CHSEL. Reset type: XRSn |
LOCK is shown in Figure 14-12 and described in Table 14-16.
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Lock Register
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0-0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0-0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | VREGCTL | CMPLNMXSEL | |||||
R-0-0h | R/WSonce-0h | R/WSonce-0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CMPHNMXSEL | CMPLPMXSEL | CMPHPMXSEL | RESERVED | RESERVED | VMONCTL | ANAREFCTL | TSNSCTL |
R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h | R/WSonce-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31-10 | RESERVED | R-0 | 0h | Reserved |
9 | VREGCTL | R/WSonce | 0h | VREGCTL Register Lock. Setting this bit will disable any future write to the respective register. This bit can only be cleared by a reset. Reset type: SYSRSn |
8 | CMPLNMXSEL | R/WSonce | 0h | CMPLNMXSEL Register Lock. Setting this bit will disable any future write to the respective register. This bit can only be cleared by a reset. Reset type: SYSRSn |
7 | CMPHNMXSEL | R/WSonce | 0h | CMPHNMXSEL Register Lock. Setting this bit will disable any future write to the respective register. This bit can only be cleared by a reset. Reset type: SYSRSn |
6 | CMPLPMXSEL | R/WSonce | 0h | CMPLPMXSEL Register Lock. Setting this bit will disable any future write to the respective register. This bit can only be cleared by a reset. Reset type: SYSRSn |
5 | CMPHPMXSEL | R/WSonce | 0h | CMPHPMXSEL Register Lock. Setting this bit will disable any future write to the respective register. This bit can only be cleared by a reset. Reset type: SYSRSn |
4 | RESERVED | R/WSonce | 0h | Reserved |
3 | RESERVED | R/WSonce | 0h | Reserved |
2 | VMONCTL | R/WSonce | 0h | VMONCTL Register Lock. Setting this bit will disable any future write to the respective register. This bit can only be cleared by a reset. Reset type: SYSRSn |
1 | ANAREFCTL | R/WSonce | 0h | ANAREFCTL Register Lock. Setting this bit will disable any future write to the respective register. This bit can only be cleared by a reset. Reset type: SYSRSn |
0 | TSNSCTL | R/WSonce | 0h | TSNSCTL Register Lock. Setting this bit will disable any future write to the respective register. This bit can only be cleared by a reset. Reset type: SYSRSn |