SPRUIN7C March 2020 – March 2024 TMS320F280021 , TMS320F280021-Q1 , TMS320F280023 , TMS320F280023-Q1 , TMS320F280023C , TMS320F280025 , TMS320F280025-Q1 , TMS320F280025C , TMS320F280025C-Q1
The user can simulate a CPU reset (SYSRS) in software. This can be done by setting the CPU1RSn bit to 1 in the SIMRESET register by CPU1 software. This toggles the CPU1.SYSRS signals and resets the CPU (just like the debugger reset).
After this reset, the SIMRESET_CPU1RSn bit in the RESC register is set. Software can read this bit to know the cause of the reset and clear the status by writing a 1 into the corresponding bit in the RESCCLR register.