SPRUJ28C november 2021 – june 2023 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
The DDR controller has a BIST engine that supports MOVI3N and limited MOVI algorithms, a self-refresh retention test, an idle retention test and a memory initialization test for detecting the following faults:
The DDR controller also supports BIST on ECC lanes for out-of-band ECC configuration. The following are the BIST related registers: