SPRUJ28C november 2021 – june 2023 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
The CTRL_MMR0 memory space is divided into the partitions shown in Table 5-1.
Partition(1) | Description | Proxy0 Offset Range | Proxy1 Offset Range |
---|---|---|---|
Partition 0 | General configuration and IPC regs | 0000h to 1FFFh | 2000h to 3FFFh |
Partition 1 | IP control/status regs | 4000h to 5FFFh | 6000h to 7FFFh |
Partition 2 | Clock control/status regs | 8000h to 9FFFh | A000h to BFFFh |
Partition 3 | BIST control/status regs | C000h to DFFFh | E000h to FFFFh |
Partition 5 | DDR frequency Control | 1 4000h to 1 5FFFh | 1 6000h to 1 7FFFh |
Partition 7 | MAIN I/O Pad Configuration regs | 1 C000h to 1 DFFFh | 1 E000h to 1 FFFFh |
The MCU_CTRL_MMR0 memory space is divided into the partitions shown in Table 5-2.
Partition(1) | Description | Proxy0 Offset Range | Proxy1 Offset Range |
---|---|---|---|
Partition 0 | General configuration and IPC regs | 0000h to 1FFFh | 2000h to 3FFFh |
Partition 1 | IP control/status regs | 4000h to 5FFFh | 6000h to 7FFFh |
Partition 2 | Clock control/status regs | 8000h to 9FFFh | A000h to BFFFh |
Partition 3 | BIST control/status regs | C000h to DFFFh | E000h to FFFFh |
The WKUP_CTRL_MMR0 memory space is divided into the partitions shown in Table 5-3.
Partition(1) | Description | Proxy0 Offset Range | Proxy1 Offset Range |
---|---|---|---|
Partition 0 | General configuration and IPC regs | 0000h to 1FFFh | 2000h to 3FFFh |
Partition 1 | IP control/status regs | 4000h to 5FFFh | 6000h to 7FFFh |
Partition 2 | Clock control/status regs | 8000h to 9FFFh | A000h to BFFFh |
Partition 3 | BIST control/status regs | C000h to DFFFh | E000h to FFFFh |
Partition 5 | Power Management regs | 1 4000h to 1 5FFFh | 1 6000h to 1 7FFFh |
Partition 6 | Power and reset control and status | 1 8000h to 1 9000h | 1 A000h to 1 B000h |
Partition 7 | WKUP I/O Pad Configuration regs | 1 C000h to 1 DFFFh | 1 E000h to 1 FFFFh |