SPRUJ28C november 2021 – june 2023 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
As shown in Figure 6-1 the COMPUTE_CLUSTER0 consists of different modules, several interconnects and ECC aggregators. The memories (internal data buffers, command buffers, queue buffers, other FIFOs, configuration registers, etc.) associated with these blocks are ECC protected to increase functional reliability.
There are three ECC aggregators in the A72SS0, one in GIC0, and three ECC aggregators in MSMC_WRAP. Table 6-3 through Table 6-5 show the mapping between the end points, their memories protected by ECC and the RAM IDs. The mapping for the ECC aggregators in A72SS0 is shown in Section 6.2.2.9A72SS ECC Aggregators. The debug components are not ECC protected.
The RAM ID is written to the ECC_VECTOR[10-0] ECC_VECTOR field. For information about the ECC aggregator functionality, see Section 12.10.4ECC Aggregator.
End Point | RAM ID | ECC Protected RAM |
---|---|---|
MSMC | 0 | msmc_mmr_busecc |
MSMC | 1 | postarb_pipe_cfg_busecc |
MSMC | 2 | emif0_slv_pipe_busecc |
MSMC | 3 | emif0_mst_pipe_busecc |
MSMC | 4 | emif1_slv_pipe_busecc |
MSMC | 5 | emif1_mst_pipe_busecc |
MSMC | 6 | cpu0_slv_local_arb_busecc |
MSMC | 7 | cpu0_mst_local_arb_busecc |
MSMC | 8 | cpu1_slv_local_arb_busecc |
MSMC | 9 | cpu1_mst_local_arb_busecc |
MSMC | 10 | cpu4_slv_local_arb_busecc |
MSMC | 11 | cpu4_mst_local_arb_busecc |
MSMC | 12 | cpu5_slv_local_arb_busecc |
MSMC | 13 | cpu5_mst_local_arb_busecc |
MSMC | 14 | cpu8_slv_local_arb_busecc |
MSMC | 15 | cpu8_mst_local_arb_busecc |
MSMC | 16 | cpu9_slv_local_arb_busecc |
MSMC | 17 | cpu9_mst_local_arb_busecc |
AXI2VBUSMC0 | 18 | en_msmc_p0_busecc_data |
AXI2VBUSMC0 | 19 | en_msmc_p0_busecc |
AXI2VBUSMC1 | 20 | en_msmc_p1_busecc_data |
AXI2VBUSMC1 | 21 | en_msmc_p1_busecc |
MSMC - Cache Controller | 22 | rmw0_busecc |
MSMC - Cache Controller | 23 | rmw0_cache_tag_pipe_busecc |
MSMC - Cache Controller | 24 | rmw0_queue_busecc_0 |
MSMC - Cache Controller | 25 | rmw0_queue_busecc_1 |
MSMC - Cache Controller | 26 | rmw0_queue_busecc_2 |
MSMC - Cache Controller | 27 | rmw0_rmw_tag_update_busecc |
MSMC - Cache Controller | 28 | rmw0_sram_sf_pipe_busecc |
MSMC - Cache Controller | 29 | sram0_busecc |
MSMC - Data ram | 30 | dataram_bank0_busecc |
MSMC - Cache Controller | 31 | rmw1_busecc |
MSMC - Cache Controller | 32 | rmw1_cache_tag_pipe_busecc |
MSMC - Cache Controller | 33 | rmw1_queue_busecc_0 |
MSMC - Cache Controller | 34 | rmw1_queue_busecc_1 |
MSMC - Cache Controller | 35 | rmw1_queue_busecc_2 |
MSMC - Cache Controller | 36 | rmw1_rmw_tag_update_busecc |
MSMC - Cache Controller | 37 | rmw1_sram_sf_pipe_busecc |
MSMC - Cache Controller | 38 | sram1_busecc |
MSMC - Data ram | 39 | dataram_bank1_busecc |
MSMC - Cache Controller | 40 | rmw2_busecc |
MSMC - Cache Controller | 41 | rmw2_cache_tag_pipe_busecc |
MSMC - Cache Controller | 42 | rmw2_queue_busecc_0 |
MSMC - Cache Controller | 43 | rmw2_queue_busecc_1 |
MSMC - Cache Controller | 44 | rmw2_queue_busecc_2 |
MSMC - Cache Controller | 45 | rmw2_rmw_tag_update_busecc |
MSMC - Cache Controller | 46 | rmw2_sram_sf_pipe_busecc |
MSMC - Cache Controller | 47 | sram2_busecc |
MSMC - Data ram | 48 | dataram_bank2_busecc |
MSMC - Cache Controller | 49 | rmw3_busecc |
MSMC - Cache Controller | 50 | rmw3_cache_tag_pipe_busecc |
MSMC - Cache Controller | 51 | rmw3_queue_busecc_0 |
MSMC - Cache Controller | 52 | rmw3_queue_busecc_1 |
MSMC - Cache Controller | 53 | rmw3_queue_busecc_2 |
MSMC - Cache Controller | 54 | rmw3_rmw_tag_update_busecc |
MSMC - Cache Controller | 55 | rmw3_sram_sf_pipe_busecc |
MSMC - Cache Controller | 56 | sram3_busecc |
MSMC - Data ram | 57 | dataram_bank3_busecc |
MSMC - Cache Controller | 58 | rmw4_busecc |
MSMC - Cache Controller | 59 | rmw4_cache_tag_pipe_busecc |
MSMC - Cache Controller | 60 | rmw4_queue_busecc_0 |
MSMC - Cache Controller | 61 | rmw4_queue_busecc_1 |
MSMC - Cache Controller | 62 | rmw4_queue_busecc_2 |
MSMC - Cache Controller | 63 | rmw4_rmw_tag_update_busecc |
MSMC - Cache Controller | 64 | rmw4_sram_sf_pipe_busecc |
MSMC - Cache Controller | 65 | sram4_busecc |
MSMC - Data ram | 66 | dataram_bank4_busecc |
CLEC | 67 | clec_sram_ramecc |
DSP4 CFG P2P | 68 | msmc_cfg_wrap_cbass_msmc_cfg_wrap_cbass_vbusp4_cfg_dsp4_p2p_bridge_vbusp4_cfg_dsp4_bridge_dst_busecc |
DSP5 CFG P2P | 69 | msmc_cfg_wrap_cbass_msmc_cfg_wrap_cbass_vbusp4_cfg_dsp5_p2p_bridge_vbusp4_cfg_dsp4_bridge_dst_busecc |
DSP5 CFG P2P | 70 | msmc_cfg_wrap_cbass_msmc_cfg_wrap_cbass_vbusp4_cfg_dsp5_p2p_bridge_vbusp4_cfg_dsp4_bridge_dst_busecc |
DDRSS0 - VDC | 71 | emif_0_vsafe_si |
DDRSS1- VDC | 72 | emif_1_vsafe_si |
CLEC EDC Control | 73 | clec_clec_edc_ctrl_busecc |
AXI2VBUSMC0 FW | 74 | en_msmc_p0_mmr_fw_edc_ctl |
MSMC WRAP - DMSC WRAP | 75 | vbusp_dmsc_cbass_cpac0_fw_bridge_dst_busecc |
AXI2VBUSMC0 | 76 | en_msmc_p0_busecc_rack_cid_queue_strb |
AXI2VBUSMC0 | 77 | en_msmc_p0_busecc_rd_barrier_queue_strb |
AXI2VBUSMC0 | 78 | en_msmc_p0_busecc_snoop_cmd_id_queue_strb |
AXI2VBUSMC0 | 79 | en_msmc_p0_busecc_snp_data_buf_strb |
AXI2VBUSMC0 | 80 | en_msmc_p0_busecc_snp_resp_buf_strb |
AXI2VBUSMC0 | 81 | en_msmc_p0_busecc_wack_cid_queue_strb |
AXI2VBUSMC0 | 82 | en_msmc_p0_busecc_wr_barrier_queue_strb |
AXI2VBUSMC0 | 83 | en_msmc_p0_busecc_write_resp_strb |
AXI2VBUSMC0 | 84 | en_msmc_p0_busecc_1_strb |
AXI2VBUSMC0 | 85 | en_msmc_p0_busecc_msmc_cmd_buffer_strb |
AXI2VBUSMC1 FW | 86 | en_msmc_p1_mmr_fw_edc_ctl_strb |
MSMC WRAP - DMSC WRAP | 87 | vbusp_dmsc_cbass_cpac1_fw_bridge_dst_busecc_strb |
AXI2VBUSMC1 | 88 | en_msmc_p1_busecc_rack_cid_queue_strb |
AXI2VBUSMC1 | 89 | en_msmc_p1_busecc_rd_barrier_queue_strb |
AXI2VBUSMC1 | 90 | en_msmc_p1_busecc_snoop_cmd_id_queue_strb |
AXI2VBUSMC1 | 91 | en_msmc_p1_busecc_snp_data_buf_strb |
AXI2VBUSMC1 | 92 | en_msmc_p1_busecc_snp_resp_buf_strb |
AXI2VBUSMC1 | 93 | en_msmc_p1_busecc_wack_cid_queue_strb |
AXI2VBUSMC1 | 94 | en_msmc_p1_busecc_wr_barrier_queue_strb |
AXI2VBUSMC1 | 95 | en_msmc_p1_busecc_write_resp_strb |
AXI2VBUSMC1 | 96 | en_msmc_p1_busecc_1_strb |
AXI2VBUSMC1 | 97 | en_msmc_p1_busecc_msmc_cmd_buffer_strb |
End Point | RAM ID | ECC Protected RAM |
---|---|---|
MSMC WRAP - DMSC WRAP | 0 | vbusp_dmsc_cbass_cbass_scr_scr_edc_busecc_0 |
MSMC WRAP - DMSC WRAP | 1 | dmsc_mmr_boot_edc_ctrl_busecc_busecc |
MSMC WRAP - DMSC WRAP | 2 | dmsc_mmr_emulation_edc_ctrl_busecc_busecc |
MSMC WRAP - DMSC WRAP | 3 | dmsc_mmr_privid_edc_ctrl_busecc_busecc |
MSMC WRAP - CFG WRAP | 4 | msmc_cfg_wrap_cbass_msmc_cfg_wrap_cbass_clk4_clk_edc_ctrl_cbass_int_clk4_busecc |
MSMC WRAP - CFG WRAP | 5 | msmc_cfg_wrap_cbass_msmc_cfg_wrap_cbass_clk4_clk_edc_ctrl_cbass_int_clk4_busecc |
MSMC WRAP - CFG WRAP | 6 | msmc_cfg_wrap_cbass_msmc_cfg_wrap_cbass_clk4_clk_edc_ctrl_cbass_int_clk4_busecc |
MSMC WRAP - CFG WRAP | 7 | msmc_cfg_wrap_cbass_msmc_cfg_wrap_cbass_clk4_clk_edc_ctrl_cbass_int_clk4_busecc |
MSMC WRAP - DMSC WRAP | 8 | msmc_cfg_wrap_cbass_msmc_cfg_wrap_cbass_clk4_clk_edc_ctrl_cbass_int_clk4_busecc |
AXI2VBUSMC0 - VDC | 9 | en_msmc_p0_vbusp_cfg_src_p2m_dst_busecc |
AXI2VBUSMC0 - VDC | 10 | en_msmc_p0_vbusp_cfg_src_p2m_src_busecc |
AXI2VBUSMC0 - VDC | 11 | en_msmc_p0_vbusp_cfg_src_m2m_src_busecc |
AXI2VBUSMC1 - VDC | 12 | en_msmc_p1_vbusp_cfg_src_p2m_dst_busecc |
AXI2VBUSMC1 - VDC | 13 | en_msmc_p1_vbusp_cfg_src_p2m_src_busecc |
AXI2VBUSMC1 - VDC | 14 | en_msmc_p1_vbusp_cfg_src_m2m_src_busecc |
AXI2VBUSMC0 - VDC | 15 | en_msmc_p0_vbusp_cfg_src_p2m_reassembly_busecc |
AXI2VBUSMC1 - VDC | 16 | en_msmc_p1_vbusp_cfg_src_p2m_reassembly_busecc |
MSMC WRAP - CFG WRAP | 17 | msmc_cfg_wrap_cbass_msmc_cfg_wrap_cbass_vbusp_gicss_p2m_bridge_vbusp_gicss_bridge_busecc |
MSMC WRAP - CFG WRAP | 18 | msmc_cfg_wrap_cbass_msmc_cfg_wrap_cbass_vbusp_gicss_p2m_bridge_vbusp_gicss_bridge_reassembly_busecc |
MSMC WRAP - CFG WRAP | 19 | msmc_cfg_wrap_cbass_msmc_cfg_wrap_cbass_vbusp_ddrss0_bridge_busecc |
MSMC WRAP - CFG WRAP | 20 | msmc_cfg_wrap_cbass_msmc_cfg_wrap_cbass_vbusp_ddrss1_bridge_busecc |
DDRSS0 -VBUSP VDC | 21 | ddrss0_m2m_src_vbuss |
DDRSS0 - VBUSP VDC | 22 | ddrss0_src_p2m_busecc |
DDRSS0 - VBUSP VDC | 23 | ddrss0_src_p2m_reassembly_busecc |
DDRSS1 -VBUSP VDC | 24 | ddrss1_m2m_src_vbuss |
DDRSS1 - VBUSP VDC | 25 | ddrss1_src_p2m_busecc |
DDRSS1 - VBUSP VDC | 26 | ddrss1_src_p2m_reassembly_busecc |
GIC m2m | 27 | msmc_gicss_m2m_bridge_src_edc_ctrl_busecc_strb |
GIC m2m | 28 | msmc_gicss_m2m_bridge_dst_edc_ctrl_busecc_strb |
MSMC WRAP - CFG WRAP | 29 | msmc_cfg_wrap_cbass_msmc_cfg_wrap_cbass_vbusp4_cfg_dsp4_p2p_bridge_vbusp4_cfg_dsp4_bridge_src_busecc_strb |
MSMC WRAP - CFG WRAP | 30 | msmc_cfg_wrap_cbass_msmc_cfg_wrap_cbass_vbusp4_cfg_dsp4_p2p_bridge_vbusp4_cfg_dsp5_bridge_src_busecc_strb |
MSMC WRAP - CFG WRAP | 31 | msmc_cfg_wrap_cbass_msmc_cfg_wrap_cbass_vbusp4_cfg_clec_p2p_bridge_vbusp4_cfg_clec_bridge_src_busecc_strb |
ECC AGGR2 - P2P bridge | 32 | vbusp_cfg_ecc_aggr2_p2p_src_busecc |
MSMC WRAP - CFG WRAP | 33 | msmc_cfg_wrap_cbass_msmc_cfg_wrap_cbass_vbusp_msmc_ecc_aggr2_p2p_bridge_vbusp_msmc_ecc_aggr2_bridge_busecc_strb |
ECC AGGR3 - P2P bridge | 34 | vbusp_cfg_ecc_aggr3_p2p_src_busecc |
MSMC WRAP - CFG WRAP | 35 | msmc_cfg_wrap_cbass_msmc_cfg_wrap_cbass_vbusp_msmc_ecc_aggr3_p2p_bridge_vbusp_msmc_ecc_aggr2_bridge_busecc_strb |
MSMC WRAP - CFG WRAP | 36 | msmc_cfg_wrap_cbass_msmc_cfg_wrap_cbass_gicss_vbusm_gasket_cfg_p2p_bridge_gicss_vbusm_gasket_cfg_bridge_busecc_strb |
MSMC_WRAP | 37 | gicss_vbusm_gasket_wr_ramecc |
MSMC_WRAP | 38 | gicss_vbusm_gasket_rd_ramecc |
End Point | RAM ID | ECC Protected RAM |
---|---|---|
DDRSS - VDC | 0 | ddrss0_asafe_si |
ECC AGGR2 - P2P bridge | 1 | vbusp_cfg_ecc_aggr2_p2p_dst_busecc |
MSMC_WRAP | 2 | edc_ctrl_eccaggr2 |