SPRUJ28C november 2021 – june 2023 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
The DISPC includes two types of input video pipelines:
The video pipeline (VID) consists of:
The video lite pipeline (VIDL) is identical to the video pipeline (VID), except for:
Each pipeline processing block can be independently bypassed.
The DISPC input video pipelines, VID and VID1L, will be commonly refered to as video pipeline (VID) in the following sections. Any differences in their functionality will be highlighted.
The input of the VID pipeline is connected to the video DMA buffer controller. The pixel output of the VID pipeline is connected to the overlay managers. The VID pipeline configuration supports various BITMAP, RGB (ARGB and RGBA), and YUV formats, as listed in Table 12-340, DISPC Pixel Data Formats.
The 256-entry CLUT is either used to convert BITMAP (1, 2, 4, or 8-bit indexed formats) into RGB format, or for RGB to RGB inverse gamma correction. For a BITMAP format data, scaling is not supported. Scaling and color look-up table features are mutually exclusive. If the color look-up feature is enabled, then the video pipeline scaler has to be disabled.
For chroma sub-sampled YUV formats (YUV422 and YUV420-NV12/NV21):
For ARGB source data with less than/equal to 10-bit component data size the replication logic (ARGB expansion) converts the data to ARGB48 by replicating the MSBs into the LSBs:
There are limitations on using the inverse gamma (InvGamma) operation along with scaling. If the scaler is enabled, the InvGamma operation must always take place after the scaler in the data-path (as shown in Figure 12-311). This position of the InvGamma operation is controllable through the DSS0_VID_ATTRIBUTES2[29] GAMMAINVERSIONPOS register field.
All the memories (line buffers attached to the scaler, LUT and chroma upsamplers) are sized to support 10-bit per color component. This allows full 10-bit support inside the video pipeline.
The VID pipeline can be enabled by setting the DSS0_VID_ATTRIBUTES[0] ENABLE register bit. If the video pipeline is disabled, the video window does not exist on the screen and the whole video pipeline and its DMA are inactive. Prior to enabling the video layer a valid configuration has to be set by the user.