SPRUJ28C november 2021 – june 2023 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
In default (non-DSC enabled) modes, the EDP performs the matching pixel data clock selection (MuxA - MuxE) based only on the VIF input source selection (EDP_DTPX_SRC_CFG[7-4] VIF_n_SEL register fields) settings.
For VIF0_CLK, the source selection in non-DSC enabled mode comes from the output of MuxA (EDP_DPI_0_2x_CLK or EDP_DPI_2_2x_CLK). These clocks are full pixel data frequency clocks.
When DSC is enabled, the DSC_ENC0_CLK and DSC_ENC1_CLK clocks are sourced (MuxF) from:
VIF0_CLK and VIF1_CLK selection goes through additional muxing (MuxG/MuxH) to match the DSC encoder clocks.