SPRUJ28C november 2021 – june 2023 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
The HWA2 scheduler in HTS is used for LDC, the HWA4 is used for MSC0, and HWA6 is used for NF. The HTS programming is as follows:
// HWA2/LDC Scheduler Programming (keep default programing for rest of parameters)
HTS->HWA2_wdtimer->wdtimer_en = 1; //Activate WD
HTS->HWA2_scheduler_control->pipeline_num = 2; // Belongs to pipeline 2
// HWA2/LDC Producer control
HTS->HWA2_prod0_control->prod_en = 1; // Enable Producer socket
HTS->HWA2_prod0_buf_control->depth = 120; // (FW/OBW)*2; ping-pong buffer for 2 rows of 32x32 blocks
HTS->HWA2_prod0_control->cons_select = 0; // Fixed to DMA
HTS->HWA2_prod0_buf_control->threshold = 1; // threshold value
HTS->HWA2_prod0_count-> count_postload=0;
HTS->HWA2_prod0_count-> count_preload=0;
HTS->HWA2_pa0_control-> pa_ps_maxcount = 32; // OBH
HTS->HWA2_pa0_control-> pa_cs_maxcount = 60; // (FW/OBW)
HTS->HWA2_pa0_control-> pa_buf_cntl = ‘0’; //
HTS->HWA2_pa0_control-> pa_enable = ‘1’ ;
// HWA2/LDC Producer control
HTS->HWA2_prod1_control->prod_en = 1; // Enable Producer socket
HTS->HWA2_prod1_buf_control->depth = 2; // ping-pong buffer for chroma blocks
HTS->HWA2_prod1_control->cons_select = 0; // Fixed to DMA
HTS->HWA2_prod1_buf_control->threshold = 1; // threshold value
HTS->HWA2_prod1_count-> count_postload=0;
HTS->HWA2_prod1_count-> count_preload=0;
HTS->HWA2_pa1_control-> pa_enable = ‘0’; // No pattern adaptation for Chroma
// HWA2/LDC Producer control
HTS->HWA2_prod4_control->prod_en = 1; // Enable Producer socket
HTS->HWA2_prod4_buf_control->depth = 120; // (FW/OBW)*2; ping-pong buffer for 2 rows of 32x32 blocks
HTS->HWA2_prod4_control->cons_select = 33; // Select MSC0-IN
HTS->HWA2_prod4_buf_control->threshold = 5; // threshold value
HTS->HWA2_prod4_count-> count_postload=2;
HTS->HWA2_prod4_count-> count_preload=2;
HTS->HWA2_pa4_control-> pa_ps_maxcount = 32; // OBH
HTS->HWA2_pa4_control-> pa_cs_maxcount = 60; // (FW/OBW)
HTS->HWA2_pa4_control-> pa_buf_cntl = ‘1’; // Apply threshold/pos/preload on PA output
HTS->HWA2_pa4_control-> pa_enable = ‘1’;
// HWA2/LDC Producer control
HTS->HWA2_prod6_control->prod_en = 1; // Enable Producer socket
HTS->HWA2_prod6_buf_control->depth = 120; // (FW/OBW)*2; ping-pong buffer for 2 rows of 32x32 blocks
HTS->HWA2_prod6_control->cons_select = 49; // Select NF-IN
HTS->HWA2_prod6_buf_control->threshold = 5; // threshold value
HTS->HWA2_prod6_count-> count_postload=2;
HTS->HWA2_prod6_count-> count_preload=2;
HTS->HWA2_pa6_control-> pa_ps_maxcount = 32; // OBH
HTS->HWA2_pa6_control-> pa_cs_maxcount = 60; // (FW/OBW)
HTS->HWA2_pa6_control-> pa_buf_cntl = ‘1’; // Apply threshold/pos/preload on PA output
HTS->HWA2_pa6_control-> pa_enable = ‘1’ ;
// configure MSC0 (10 output)
HTS->HWA4_scheduler_control->pipeline_num = 2; // Belongs to pipeline 2
HTS->HWA4_cons_control->cons0_en = 1; // MSC in
HTS->HWA4_cons_control->prod0_select = 37; // connect to LDC-MSC producer
HTS->HWA4_prod0_control->prod_en = 1; // Enable Producer socket
HTS->HWA4_prod0_buf_control->depth = 2; // ping-pong buffer
HTS->HWA4_prod0_control->cons_select = 0; // Fixed to DMA
HTS->HWA4_prod1_control->prod_en = 1; // Enable Producer socket
HTS->HWA4_prod1_buf_control->depth = 2; // ping-pong buffer
HTS->HWA4_prod1_control->cons_select = 0; // Fixed to UDMA
HTS->HWA4_prod2_control->prod_en = 1; // Enable Producer socket
HTS->HWA4_prod2_buf_control->depth = 2; // ping-pong buffer
HTS->HWA4_prod2_control->cons_select = 0; // Fixed to DMA
HTS->HWA4_prod3_control->prod_en = 1; // Enable Producer socket
HTS->HWA4_prod3_buf_control->depth = 2; // ping-pong buffer
HTS->HWA4_prod3_control->cons_select = 0; // Fixed to DMA
HTS->HWA4_prod4_control->prod_en = 1; // Enable Producer socket
HTS->HWA4_prod4_buf_control->depth = 2; // ping-pong buffer
HTS->HWA4_prod4_control->cons_select = 0; // Fixed to DMA
HTS->HWA4_prod5_control->prod_en = 1; // Enable Producer socket
HTS->HWA4_prod5_buf_control->depth = 2; // ping-pong buffer
HTS->HWA4_prod5_control->cons_select = 0; // Fixed to DMA
HTS->HWA4_prod6_control->prod_en = 1; // Enable Producer socket
HTS->HWA4_prod6_buf_control->depth = 2; // ping-pong buffer
HTS->HWA4_prod6_control->cons_select = 0; // Fixed to DMA
HTS->HWA4_prod7_control->prod_en = 1; // Enable Producer socket
HTS->HWA4_prod7_buf_control->depth = 2; // ping-pong buffer
HTS->HWA4_prod7_control->cons_select = 0; // Fixed to DMA
HTS->HWA4_prod8_control->prod_en = 1; // Enable Producer socket
HTS->HWA4_prod8_buf_control->depth = 2; // ping-pong buffer
HTS->HWA4_prod8_control->cons_select = 0; // Fixed to DMA
HTS->HWA4_prod9_control->prod_en = 1; // Enable Producer socket
HTS->HWA4_prod9_buf_control->depth = 2; // ping-pong buffer
HTS->HWA4_prod9_control->cons_select = 0; // Fixed to DMA
// configure NF
HTS->HWA6_scheduler_control->pipeline_num = 2; // Belongs to pipeline 2
HTS->HWA6_cons_control->cons0_en = 1; // NF in
HTS->HWA6_cons_control->prod_select = 39; // connect to LDC-NF producer
HTS->HWA6_prod0_control->prod_en = 1; // Enable Producer socket
HTS->HWA6_prod0_buf_control->depth = 2; // ping-pong buffer
HTS->HWA6_prod0_control->cons_select = 0; // Fixed to DMA
// configure DMA
HTS->DMA304_scheduler_control->pipeline_num = 2; // Belongs to pipeline 0
HTS->DMA304_scheduler_control->dma_channel_no = 0x12; // Assign appropriate DMA channel
HTS->DMA304_cons0_control->cons_en = 1; // Enable consumer socket
HTS->DMA305_scheduler_control->pipeline_num = 2; // Belongs to pipeline 0
HTS->DMA305_scheduler_control->dma_channel_no = 0x13; // Assign appropriate DMA channel
HTS->DMA305_cons0_control->cons_en = 1; // Enable consumer socket
HTS->DMA306_scheduler_control->pipeline_num = 2; // Belongs to pipeline 0
HTS->DMA306_scheduler_control->dma_channel_no = 0x14; // Assign appropriate DMA channel
HTS->DMA306_cons0_control->cons_en = 1; // Enable consumer socket
HTS->DMA307_scheduler_control->pipeline_num = 2; // Belongs to pipeline 0
HTS->DMA307_scheduler_control->dma_channel_no = 0x15; // Assign appropriate DMA channel
HTS->DMA307_cons0_control->cons_en = 1; // Enable consumer socket
HTS->DMA308_scheduler_control->pipeline_num = 2; // Belongs to pipeline 0
HTS->DMA308_scheduler_control->dma_channel_no = 0x16; // Assign appropriate DMA channel
HTS->DMA308_cons0_control->cons_en = 1; // Enable consumer socket
HTS->DMA309_scheduler_control->pipeline_num = 2; // Belongs to pipeline 0
HTS->DMA309_scheduler_control->dma_channel_no = 0x17; // Assign appropriate DMA channel
HTS->DMA309_cons0_control->cons_en = 1; // Enable consumer socket
HTS->DMA310_scheduler_control->pipeline_num = 2; // Belongs to pipeline 0
HTS->DMA310_scheduler_control->dma_channel_no = 0x18; // Assign appropriate DMA channel
HTS->DMA310_cons0_control->cons_en = 1; // Enable consumer socket
HTS->DMA311_scheduler_control->pipeline_num = 2; // Belongs to pipeline 0
HTS->DMA311_scheduler_control->dma_channel_no = 0x19; // Assign appropriate DMA channel
HTS->DMA311_cons0_control->cons_en = 1; // Enable consumer socket
HTS->DMA312_scheduler_control->pipeline_num = 2; // Belongs to pipeline 0
HTS->DMA312_scheduler_control->dma_channel_no = 0x1A; // Assign appropriate DMA channel
HTS->DMA312_cons0_control->cons_en = 1; // Enable consumer socket
HTS->DMA313_scheduler_control->pipeline_num = 2; // Belongs to pipeline 0
HTS->DMA313_scheduler_control->dma_channel_no = 0x1B; // Assign appropriate DMA channel
HTS->DMA313_cons0_control->cons_en = 1; // Enable consumer socket
HTS->DMA336_scheduler_control->pipeline_num = 2; // Belongs to pipeline 0
HTS->DMA336_scheduler_control->dma_channel_no = 0x1C; // Assign appropriate DMA channel
HTS->DMA336_cons0_control->cons_en = 1; // Enable consumer socket
HTS->DMA272_scheduler_control->pipeline_num = 2; // Belongs to pipeline 0
HTS->DMA272_scheduler_control->dma_channel_no = 0x1D; // Assign appropriate DMA channel
HTS->DMA272_cons0_control->cons_en = 1; // Enable consumer socket
HTS->DMA273_scheduler_control->pipeline_num = 2; // Belongs to pipeline 0
HTS->DMA273_scheduler_control->dma_channel_no = 0x1E; // Assign appropriate DMA channel
HTS->DMA273_cons0_control->cons_en = 1; // Enable consumer socket
// Enable Required Schedulers
HTS->HWA2_scheduler_control->sch_en = 1; //LDC0 Scheduler Enable
HTS->HWA4_scheduler_control->sch_en = 1; //MSC0 Scheduler Enable
HTS->HWA6_scheduler_control->sch_en = 1; //NF Scheduler Enable
HTS->DMA272_scheduler_control->sch_en = 1; //Cons DMA for LDC Y12 Enable
HTS->DMA273_scheduler_control->sch_en = 1; //Cons DMA for LDC UV12 Enable
HTS->DMA304_scheduler_control->sch_en = 1; //Cons DMA for MSC0-O0 Enable
HTS->DMA305_scheduler_control->sch_en = 1; //Cons DMA for MSC0-O1 Enable
HTS->DMA306_scheduler_control->sch_en = 1; //Cons DMA for MSC0-O2 Enable
HTS->DMA307_scheduler_control->sch_en = 1; //Cons DMA for MSC0-O3 Enable
HTS->DMA308_scheduler_control->sch_en = 1; //Cons DMA for MSC0-O4 Enable
HTS->DMA309_scheduler_control->sch_en = 1; //Cons DMA for MSC0-O5 Enable
HTS->DMA310_scheduler_control->sch_en = 1; //Cons DMA for MSC0-O6 Enable
HTS->DMA311_scheduler_control->sch_en = 1; //Cons DMA for MSC0-O7 Enable
HTS->DMA312_scheduler_control->sch_en = 1; //Cons DMA for MSC0-O8 Enable
HTS->DMA313_scheduler_control->sch_en = 1; //Cons DMA for MSC0-O9 Enable
HTS->DMA336_scheduler_control->sch_en = 1; //Cons DMA for NF Output Enable
// Enable Pipeline
HTS->HTS_control->pipe_en2 = 1; // Enable LDC-MSC-NF pipeline# 2