SPRUJ28C november 2021 – june 2023 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
The DISPC register regions in memory are partitioned such that each DISPC sub-component has its own region as shown in Table 12-356. This allows the SoC infrastructure to firewall the register memory regions in such a way that a particular processor host or virtual machine can only access the sub-component(s) allocated to it.
Region Name | Description | Byte Offset |
---|---|---|
DISPC_0_COMMON_M | COMMON Region for Master Host (Control Processor) | 0x0 |
DISPC_0_COMMON_S0 | COMMON Region for Slave Host-0 | 0x10000 |
VIDL1 | Video Lite 1 Pipeline | 0x20000 |
VIDL2 | Video Lite 2 Pipeline | 0x30000 |
VID1 | Video 1 Pipeline | 0x50000 |
VID2 | Video 2 Pipeline | 0x60000 |
OVR1 | Overlay 1 | 0x70000 |
VP1 | Video Port 1 | 0x80000 |
OVR2 | Overlay 2 | 0x90000 |
VP2 | Video Port 2 | 0xA0000 |
OVR3 | Overlay 3 | 0xB0000 |
VP3 | Video Port 3 | 0xC0000 |
OVR4 | Overlay 4 | 0xD0000 |
VP4 | Video Port 4 | 0xE0000 |
WB | Write-Back Pipeline | 0xF0000 |
DISPC_0_COMMON_S1 | COMMON Region for Slave Host-1 | 0x100000 |
DISPC_0_COMMON_S2 | COMMON Region for Slave Host-2 | 0x110000 |