Scheduling of data transfer in the SL2 interface is controlled by the HTS controller integrated at the VPAC top level. A dedicated HTS is integrated per processing thread to manage start and done flow control signals and to issue DMA service events to trigger DDR from/to SL2 transfers and SL2 from/to HWA.
The following flow control scheme is used:
/* initialization */
- @ Frame Start up: (HTS) INIT —> Frame Initialization
/* First two line processing */
Note: 'N' is input
kernel height.
- @ N-2 input lines available
and output buffer line available: (HTS) START —> Starts filter Line
processing (initial line) tasks
- @ Input Line Consumed and all
output Done: (PixCntlFSM) DONE —> Indicates completion of the line
processing task
- @ N-1 input lines available
and output buffer line available: (HTS) START —> Starts filter Line
processing (initial line) tasks
- @ Input Line Consumed and
output Done: (PixCntlFSM) DONE —> Indicates completion of the line
processing task
/* Middle Lines processing */
- @ N-1 input lines available and output buffer line available: (HTS) START —> Starts filter Line processing (initial line) tasks
- @ Input Line Consumed and output Done: (PixCntlFSM) DONE —> Indicates completion of the line processing task
- Repeat (6) and (7) until Frame_H-3 lines
/* Last two line processing */
- @ N-1 input lines available and output buffer line available: (HTS) START —> Starts filter Line processing (initial line) tasks
- @ Input Line Consumed and output Done: (PixCntlFSM) DONE —> Indicates completion of the line processing task
- @ N-2 input lines available and output buffer line available: (HTS) START —> Starts filter Line processing (initial line) tasks
- @ Input Line Consumed and all output Done: (PixCntlFSM) DONE —> Indicates completion of the line processing task
- @EOP: (PixCntlFSM) EOP