SPRUJ28C november 2021 – june 2023 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1
The VISS HWA in a non-streaming mode (memory to memory mode) needs a maximum of 3 input buffers to be loaded by UTC before it can start its processing. The 6 VISS HWA outputs produced need to be stored by UTC into DDR. Refer to chapter Data Routing Unit (DRU), about configuring the UTC for data load and store for VISS processing.
The 3 UTC channels needs to be set up for input data fetch:
The 6 VISS outputs iare mapped to independent UDMA channels, as follows:
The UTC channel configuration assumes different channels for each input and output data. SL2 storage needs to allocate minimum ping-pong buffer for each input/output data. Buffer depth is configurable. For each UTC trigger, single line of data is either loaded from DDR or stored into DDR. The HTS module manages start of UTC channels.