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SPRUIL1D May 2019 – December 2024 DRA829J , DRA829J-Q1 , DRA829V , DRA829V-Q1 , TDA4VM , TDA4VM-Q1

5.2.2.1.4 Power Glitch Detect (PGD) Modules

A Power Glitch Detect (PGD) circuit is used to detect short duration “glitches” on the core and MPU power supplies. The PGD provides a low output when no glitch is detected and a high output when a glitch is detected.

Table 5-45 shows PGD modules allocation within device domains.

Table 5-45 PGD Modules Allocation within Device Domains

Module Instance	Domain
Module Instance	WKUP	MCU	MAIN
MCU_PGD0	-	✓	-
MCU_PGD1	-	✓	-
PGD0	-	-	✓
PGD1	-	-	✓
PGD2	-	-	✓
PGD3	-	-	✓

Figure 5-18 shows the PGD block diagram.

Figure 5-18 PGD Block Diagram

Table 5-46 summarize the PGD integration.

Table 5-46 PGD Integration Summary

Module Instance	Monitored Voltage	PGD Control Register	PGD Status Register
MCU_PGD0	VDD_MCU	CTRLMMR_WKUP_VDD_MCU_GLDTC_CTRL⁽¹⁾	CTRLMMR_WKUP_VDD_MCU_GLDTC_STAT⁽¹⁾
MCU_PGD1	VDDR_MCU (SRAM)	CTRLMMR_WKUP_VDDR_MCU_GLDTC_CTRL⁽¹⁾	CTRLMMR_WKUP_VDDR_MCU_GLDTC_STAT⁽¹⁾
PGD0	VDD_CPU	CTRLMMR_WKUP_VDD_CPU_GLDTC_CTRL⁽¹⁾	CTRLMMR_WKUP_VDD_CPU_GLDTC_STAT⁽¹⁾
PGD1	VDD_CORE	CTRLMMR_WKUP_VDD_CORE_GLDTC_CTRL⁽¹⁾	CTRLMMR_WKUP_VDD_CORE_GLDTC_STAT⁽¹⁾
PGD2	VDDR_CPU (SRAM)	CTRLMMR_WKUP_VDDR_CPU_GLDTC_CTRL⁽¹⁾	CTRLMMR_WKUP_VDDR_CPU_GLDTC_STAT⁽¹⁾
PGD3	VDDR_CORE (SRAM)	CTRLMMR_WKUP_VDDR_CORE_GLDTC_CTRL⁽¹⁾	CTRLMMR_WKUP_VDDR_CORE_GLDTC_STAT⁽¹⁾

(1) For more information about control registers, see Control Module (CTRL_MMR).

Table 5-47 PGD Hardware Requests

Interrupt Requests
Module Instance	Module Interrupt Signal	Destination Interrupt Input	Destination	Description	Type
MCU_PGD0	VDD_MCU_GLDTC_STAT_THRESH_HI_FLAG⁽¹⁾	WKUP_ESM_LVL_EVT_IN_21	WKUP_ESM0	MCU_PGD0 Threshold High Flag level interrupt	Level
	VDD_MCU_GLDTC_STAT_THRESH_LOW_FLAG⁽¹⁾	WKUP_ESM_LVL_EVT_IN_20	WKUP_ESM0	MCU_PGD0 Threshold Low Flag level interrupt	Level
MCU_PGD1	VDDR_MCU_GLDTC_STAT_THRESH_HI_FLAG⁽¹⁾	WKUP_ESM_LVL_EVT_IN_23	WKUP_ESM0	MCU_PGD1 Threshold High Flag level interrupt	Level
	VDDR_MCU_GLDTC_STAT_THRESH_LOW_FLAG⁽¹⁾	WKUP_ESM_LVL_EVT_IN_22	WKUP_ESM0	MCU_PGD1 Threshold Low Flag level interrupt	Level
PGD0	VDD_CORE_GLDTC_STAT_THRESH_HI_FLAG⁽¹⁾	WKUP_ESM_LVL_EVT_IN_25	WKUP_ESM0	PGD0 Threshold High Flag level interrupt	Level
	VDD_CORE_GLDTC_STAT_THRESH_LOW_FLAG⁽¹⁾	WKUP_ESM_LVL_EVT_IN_24	WKUP_ESM0	PGD0 Threshold Low Flag level interrupt	Level
PGD1	VDD_CPU_GLDTC_STAT_THRESH_HI_FLAG⁽¹⁾	WKUP_ESM_LVL_EVT_IN_29	WKUP_ESM0	PGD1 Threshold High Flag level interrupt	Level
	VDD_CPU_GLDTC_STAT_THRESH_LOW_FLAG⁽¹⁾	WKUP_ESM_LVL_EVT_IN_28	WKUP_ESM0	PGD1 Threshold Low Flag level interrupt	Level
PGD2	VDDR_CORE_GLDTC_STAT_THRESH_HI_FLAG⁽¹⁾	WKUP_ESM_LVL_EVT_IN_27	WKUP_ESM0	PGD2 Threshold High Flag level interrupt	Level
	VDDR_CORE_GLDTC_STAT_THRESH_LOW_FLAG⁽¹⁾	WKUP_ESM_LVL_EVT_IN_26	WKUP_ESM0	PGD2 Threshold Low Flag level interrupt	Level
PGD3	VDDR_CPU_GLDTC_STAT_THRESH_HI_FLAG⁽¹⁾	WKUP_ESM_LVL_EVT_IN_31	WKUP_ESM0	PGD3 Threshold High Flag level interrupt	Level
	VDDR_CPU_GLDTC_STAT_THRESH_LOW_FLAG⁽¹⁾	WKUP_ESM_LVL_EVT_IN_30	WKUP_ESM0	PGD3 Threshold Low Flag level interrupt	Level

(1) The interrupt flag is mapped also to the corresponding status register, shown in Table 5-47.

Note:

A flag status bit in corresponding STAT register is cleared by clearing the [30] RSTB bit in the corresponding CTRL register, see for STAT and CTRL registers for a certain PGD module.