ADC32RF82
- 14-Bit, Dual-Channel, 2457.6-MSPS ADC
- Noise Floor: –154.1 dBFS/Hz
- RF Input Supports Up to 4.0 GHz
- Aperture Jitter: 90 fS
- Channel Isolation: 95 dB at fIN = 1.8 GHz
- Spectral Performance
(fIN = 900 MHz, –2 dBFS):
- SNR: 61.2 dBFS
- SFDR: 67-dBc HD2, HD3
- SFDR: 81-dBc Worst Spur
- Spectral Performance (fIN = 1.85
GHz, –2 dBFS):
- SNR: 58.7 dBFS
- SFDR: 71-dBc HD2, HD3
- SFDR: 76-dBc Worst Spur
- On-Chip Digital Down-Converters:
- Up to 4 DDCs (Dual-Band Mode)
- Up to 3 Independent NCOs per DDC
- On-Chip Input Clamp for Overvoltage Protection
- Programmable On-Chip Power Detectors with Alarm Pins for AGC Support
- On-Chip Dither
- On-Chip Input Termination
- Input Full-Scale: 1.35 VPP
- Support for Multi-Chip Synchronization
- JESD204B Interface:
- Subclass 1-Based Deterministic Latency
- 4 Lanes Per Channel at 12.5 Gbps
- Power Dissipation: 3.0 W/Ch at 2457.6 MSPS
- 72-Pin VQFN Package (10 mm × 10 mm)
The ADC32RF82 is a 14-bit, 2457.6-MSPS, dual-channel telecom receiver and feedback device family that supports RF sampling with input frequencies up to 4 GHz and beyond. Designed for high signal-to-noise ratio (SNR), the ADC32RF82 delivers a noise spectral density of –154.1 dBFS/Hz as well as dynamic range and channel isolation over a large input frequency range. The buffered analog input with on-chip termination provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy.
Each channel can be connected to a dual-band, digital down-converter (DDC) with up to three independent, 16-bit numerically-controlled oscillators (NCOs) per DDC for phase-coherent frequency hopping. Additionally, the ADC is equipped with front-end peak and RMS power detectors and alarm functions to support external automatic gain control (AGC) algorithms.
The ADC32RF82 supports the JESD204B serial interface with subclass 1-based deterministic latency using data rates up to 12.5 Gbps with up to four lanes per ADC. The device is offered in a 72-pin VQFN package (10 mm × 10 mm) and supports the industrial temperature range (–40°C to +85°C).
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | ADC32RF82 Dual-Channel, 2457.6-MSPS Telecom Receiver and Feedback Device datasheet | PDF | HTML | 2017/9/19 | ||
| 應用說明 | Configuration Files for ADC32RF45, ADC32RF83, and ADC32RF80 (Rev. B) | 2017/9/5 |
設計與開發
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在概念階段，頻率規劃工具能夠精確調整 ADC 取樣率和輸入頻率位置，以在阻塞事件期間最佳化無雜散動態範圍 (SFDR)。某些設計在這兩方面都具有靈活性；而其他一些設計，例如 L 波段接收器或無線基礎設施基地台，則處理固定頻帶，僅提供取樣率調整功能。
外部 RF 濾波器回應高度依賴於系統 SFDR 目標與 ADC 本身的 SFDR 性能；類比濾波器工具可在設計階段提供協助。
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| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| VQFNP (RMP) | 72 | Ultra Librarian |