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30.7.4.2.2 PRUSS_UART Register Description

Table 30-230 PRUSS_UART_RBR_THR_REGISTERS

Address Offset	0x0000 0000
Physical Address	0x4B22 8000 0x4B2A 8000	Instance	PRUSS1_UART PRUSS2_UART
Description	In the non-FIFO mode, when a character is placed in Receiver buffer register and the receiver data-ready interrupt is enabled (DR = 1 in Interrupt identification register), an interrupt is generated. This interrupt is cleared when the character is read from Receiver buffer register. In the FIFO mode, the interrupt is generated when the FIFO is filled to the trigger level selected in the FIFO control register, and it is cleared when the FIFO contents drop below the trigger level. In the non-FIFO mode, if Transmitter holding register is empty and the THR empty (THRE) interrupt is enabled (ETBEI = 1 in Interrupt enable register), an interrupt is generated. This interrupt is cleared when a character is loaded into Transmitter holding register or the Interrupt identification register is read. In the FIFO mode, the interrupt is generated when the transmitter FIFO is empty, and it is cleared when at least one byte is loaded into the FIFO or Interrupt identification register is read.
Type	RW

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								DATA

Bits	Field Name	Description	Type	Reset
31:8	RESERVED	Reserved	R	0x0
7:0	DATA	Read: Read Receive Buffer Register	RW	0x0
7:0	DATA	Write: Write Transmitter Holding Register	RW	0x0

Table 30-231 PRUSS_UART_INTERRUPT_ENABLE_REGISTER

Address Offset	0x0000 0004
Physical Address	0x4B22 8004 0x4B2A 8004	Instance	PRUSS1_UART PRUSS2_UART
Description	The Interrupt enable register is used to individually enable or disable each type of interrupt request that can be generated by the UART. Each interrupt request that is enabled in Interrupt enable register is forwarded to the CPU.
Type	RW

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																												EDSSI	ELSI	ETBEI	ERBI

Bits	Field Name	Description	Type	Reset
31:4	RESERVED	Reserved	R	0x0
3	EDSSI	Enable Modem Status Interrupt	RW	0x0
2	ELSI	Receiver line status interrupt enable.	RW	0x0
		0x0: Receiver line status interrupt is disabled.
		0x1: Receiver line status interrupt is enabled.
1	ETBEI	Transmitter holding register empty interrupt enable.	RW	0x0
		0x0: Transmitter holding register empty interrupt is disabled.
		0x1: Transmitter holding register empty interrupt is enabled.
0	ERBI	Receiver data available interrupt and character timeout indication interrupt enable.	RW	0x0
		0x0: Receiver data available interrupt and character timeout indication interrupt is disabled.
		0x1: Receiver data available interrupt and character timeout indication interrupt is enabled.

Table 30-232 PRUSS_UART_INTERRUPT_IDENTIFICATION_REGISTER_FIFO_CONTROL_REGISTER

Address Offset	0x0000 0008
Physical Address	0x4B22 8008 0x4B2A 8008	Instance	PRUSS1_UART PRUSS2_UART
Description	The Interrupt identification register is a read-only register at the same address as the FIFO control register, which is a write-only register. When an interrupt is generated and enabled in the Interrupt enable register, Interrupt identification register indicates that an interrupt is pending in the IPEND bit and encodes the type of interrupt in the INTID bits. Reading Interrupt identification register clears any THR empty (THRE) interrupts that are pending. The FIFOEN bit in Interrupt identification register can be checked to determine whether the UART is in the FIFO mode or the non-FIFO mode. Use FIFO control register to enable and clear the FIFOs and to select the receiver FIFO trigger level. The FIFOEN bit in FIFO control register must be set to 1 before other FIFO control register bits are written to or the FIFO control register bits are not programmed.
Type	RW

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								FIFOEN_RXFIFTL		RESERVED		INTID			IPEND_FIFOEN

Bits	Field Name	Description	Type	Reset
31:8	RESERVED	Reserved	R	0x0
7:6	FIFOEN_RXFIFTL	Read: FIFOs enabled.	RW	0x0
		0x0: Non-FIFO mode
		0x1-0x2: Reserved
		0x3: FIFOs are enabled. FIFOEN bit in the FIFO control register (FCR) is set to 1.
		Write: Receiver FIFO trigger level. RXFIFTL sets the trigger level for the receiver FIFO. When the trigger level is reached, a receiver data-ready interrupt is generated (if the interrupt request is enabled). Once the FIFO drops below the trigger level, the interrupt is cleared.
		0x0: 1 byte
		0x1: 4 bytes
		0x2: 8 bytes
		0x3: 14 bytes
5:4	RESERVED	Reserved	R	0x0
3:1	INTID	Read: Interrupt type. See Table 30-225.	RW	0x0
		0x0: Reserved
		0x1: Transmitter holding register empty (priority 3)
		0x2: Receiver data available (priority 2)
		0x3: Receiver line status (priority 1, highest)
		0x4-0x5: Reserved
		0x6: Character timeout indication (priority 2)
		0x7: Reserved
		Write:
		Bit 3: DMAMODE1: DMA MODE1 enable if FIFOs are enabled. Always write 1 to DMAMODE1. After a hardware reset, change DMAMODE1 from 0 to 1. DMAMODE1 = 1 is a requirement for proper communication between the UART and the EDMA controller.
		0x0: DMA MODE1 is disabled.
		0x1: DMA MODE1 is enabled.
		Bit 2: TXCLR: Transmitter FIFO clear. Write a 1 to TXCLR to clear the bit.
		0x0: No effect.
		0x1: Clears transmitter FIFO and resets the transmitter FIFO counter. The shift register is not cleared.
		Bit 1: RXCLR: Receiver FIFO clear. Write a 1 to RXCLR to clear the bit.
		0x0: No effect.
		0x1: Clears receiver FIFO and resets the receiver FIFO counter. The shift register is not cleared.
0	IPEND_FIFOEN	Read: Interrupt pending. When any UART interrupt is generated and is enabled in IER, IPEND is forced to 0. IPEND remains 0 until all pending interrupts are cleared or until a hardware reset occurs. If no interrupts are enabled, IPEND is never forced to 0.	RW	0x1
		0x0: Interrupts pending.
		0x1: No interrupts pending.
		Write: Transmitter and receiver FIFOs mode enable. FIFOEN must be set before other FCR bits are written to or the FCR bits are not programmed. Clearing this bit clears the FIFO counters.
		0x0: Non-FIFO mode. The transmitter and receiver FIFOs are disabled, and the FIFO pointers are cleared.
		0x1: FIFO mode. The transmitter and receiver FIFOs are enabled.

Table 30-233 PRUSS_UART_LINE_CONTROL_REGISTER

Address Offset	0x0000 000C
Physical Address	0x4B22 800C 0x4B2A 800C	Instance	PRUSS1_UART PRUSS2_UART
Description	The system programmer controls the format of the asynchronous data communication exchange by using Line control register. In addition, the programmer can retrieve, inspect, and modify the content of line control register; this eliminates the need for separate storage of the line characteristics in system memory.
Type	RW

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								DLAB	BC	SP	EPS	PEN	STB	WLS1	WLS0

Bits	Field Name	Description	Type	Reset
31:8	RESERVED	Reserved	R	0x0
7	DLAB	Divisor latch access bit. The divisor latch registers (DLL and DLH) can be accessed at dedicated addresses or at addresses shared by RBR, THR, and IER. Using the shared addresses requires toggling DLAB to change which registers are selected. If the dedicated addresses are used, keep DLAB = 0.	RW	0x0
		0x0: Allows access to the receiver buffer register (RBR), the transmitter holding register (THR), and the interrupt enable register (IER) selected. At the address shared by RBR, THR, and DLL, the CPU can read from RBR and write to THR. At the address shared by IER and DLH, the CPU can read from and write to IER.
		0x1: Allows access to the divisor latches of the baud generator during a read or write operation (DLL and DLH). At the address shared by RBR, THR, and DLL, the CPU can read from and write to DLL. At the address shared by IER and DLH, the CPU can read from and write to DLH.
6	BC	Break control.	RW	0x0
		0x0: Break condition is disabled.
		0x1: Break condition is transmitted to the receiving UART. A break condition is a condition where the UARTn_TXD signal is forced to the spacing (cleared) state.
5	SP	Stick parity. The SP bit works in conjunction with the EPS and PEN bits. The relationship between the SP, EPS, and PEN bits is summarized in Table 30-220.	RW	0x0
		0x0: Stick parity is disabled.
		0x1: Stick parity is enabled. When odd parity is selected (EPS = 0), the PARITY bit is transmitted and checked as set. When even parity is selected (EPS = 1), the PARITY bit is transmitted and checked as cleared.
4	EPS	Even parity select. Selects the parity when parity is enabled (PEN = 1). The EPS bit works in conjunction with the SP and PEN bits. The relationship between the SP, EPS, and PEN bits is summarized in Table 30-220.	RW	0x0
		0x0: Odd parity is selected (an odd number of logic 1s is transmitted or checked in the data and PARITY bits).
		0x1: Even parity is selected (an even number of logic 1s is transmitted or checked in the data and PARITY bits).
3	PEN	Parity enable. The PEN bit works in conjunction with the SP and EPS bits. The relationship between the SP, EPS, and PEN bits is summarized in Table 30-220.	RW	0x0
		0x0: No PARITY bit is transmitted or checked.
		0x1: Parity bit is generated in transmitted data and is checked in received data between the last data word bit and the first STOP bit.
2	STB	Number of STOP bits generated. STB specifies 1, 1.5, or 2 STOP bits in each transmitted character. When STB = 1, the WLS bit determines the number of STOP bits. The receiver clocks only the first STOP bit, regardless of the number of STOP bits selected. The number of STOP bits generated is summarized in Table 30-221.	RW	0x0
		0x0: 1 STOP bit is generated.
		0x1: WLS bit determines the number of STOP bits: When WLS = 0, 1.5 STOP bits are generated. When WLS = 1h, 2h, or 3h, 2 STOP bits are generated.
1-0	WLS	Word length select. Number of bits in each transmitted or received serial character. When STB = 1, the WLS bit determines the number of STOP bits.	RW	0x0
		0x0: 5 bits
		0x1: 6 bits
		0x2: 7 bits
		0x3: 8 bits

Table 30-234 PRUSS_UART_MODEM_CONTROL_REGISTER

Address Offset	0x0000 0010
Physical Address	0x4B22 8010 0x4B2A 8010	Instance	PRUSS1_UART PRUSS2_UART
Description	The Modem control register provides the ability to enable/disable the autoflow functions, and enable/disable the loopback function for diagnostic purposes.
Type	RW

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																										AFE	LOOP	OUT2	OUT1	RTS	RESERVED

Bits	Field Name	Description	Type	Reset
31:6	RESERVED	Reserved	R	0x0
5	AFE	Autoflow control enable. Autoflow control allows the UARTn_RTS and UARTn_CTS signals to provide handshaking between UARTs during data transfer. When AFE = 1, the RTS bit determines the autoflow control enabled. Note that all UARTs do not support this feature, see the device-specific data manual for supported features. If this feature is not available, this bit is reserved in this device and should be cleared to 0.	RW	0x0
		0x0: Autoflow control is disabled.
		0x1:Autoflow control is enabled: When RTS = 0, UARTn_CTS is only enabled. When RTS = 1, UARTn_RTS and UARTn_CTS are enabled.
4	LOOP	Loop back mode enable. LOOP is used for the diagnostic testing using the loop back feature.	RW	0x0
		0x0: Loop back mode is disabled.
		0x1: Loop back mode is enabled. When LOOP is set, the following occur: The UARTn_TXD signal is set high. The UARTn_RXD pin is disconnected. The output of the transmitter shift register (TSR) is lopped back in to the receiver shift register (RSR) input.
3	OUT2	OUT2 Control Bit	RW	0x0
2	OUT1	OUT1 Control Bit	RW	0x0
1	RTS	RTS control. When AFE = 1, the RTS bit determines the autoflow control enabled. Note that all UARTs do not support this feature, see the device-specific data manual for supported features. If this feature is not available, this bit is reserved in this device and should be cleared to 0.	RW	0x0
		0x0: UARTn_RTS is disabled, UARTn_CTS is only enabled.
		0x1: UARTn_RTS and UARTn_CTS are enabled.
0	RESERVED	Reserved	R	0

Table 30-235 PRUSS_UART_LINE_STATUS_REGISTER

Address Offset	0x0000 0014
Physical Address	0x4B22 8014 0x4B2A 8014	Instance	PRUSS1_UART PRUSS2_UART
Description	The Line status register provides information to the CPU concerning the status of data transfers. Line status register is intended for read operations only; do not write to this register. Bits 1 through 4 record the error conditions that produce a receiver line status interrupt.
Type	R

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								RXFIFOE	TEMT	THRE	BI	FE	PE	OE	DR

Bits	Field Name	Description	Type	Reset
31:8	RESERVED	Reserved	R	0x0
7	RXFIFOE	Receiver FIFO error. In non-FIFO mode:	R	0x0
		0x0: There has been no error, or RXFIFOE was cleared because the CPU read the erroneous character from the receiver buffer register (RBR).
		0x1: There is a parity error, framing error, or break indicator in the receiver buffer register (RBR).
		In FIFO mode:
		0x0: There has been no error, or RXFIFOE was cleared because the CPU read the erroneous character from the receiver FIFO and there are no more errors in the receiver FIFO.
		0x1: At least one parity error, framing error, or break indicator in the receiver FIFO.
6	TEMT	Transmitter empty (TEMT) indicator. In non-FIFO mode:	R	0x1
		0x0: Either the transmitter holding register (THR) or the transmitter shift register (TSR) contains a data character.
		0x1: Both the transmitter holding register (THR) and the transmitter shift register (TSR) are empty.
		In FIFO mode:
		0x0: Either the transmitter FIFO or the transmitter shift register (TSR) contains a data character.
		0x1: Both the transmitter FIFO and the transmitter shift register (TSR) are empty.
5	THRE	Transmitter holding register empty (THRE) indicator. If the THRE bit is set and the corresponding interrupt enable bit is set (ETBEI = 1 in IER), an interrupt request is generated. In non-FIFO mode:	R	0x1
		0x0: Transmitter holding register (THR) is not empty. THR has been loaded by the CPU.
		0x1: Transmitter holding register (THR) is empty (ready to accept a new character). The content of THR has been transferred to the transmitter shift register (TSR).
		In FIFO mode:
		0x0: Transmitter FIFO is not empty. At least one character has been written to the transmitter FIFO. If the transmitter FIFO is not full a write can be done.
		0x1: Transmitter FIFO is empty. The last character in the FIFO has been transferred to the transmitter shift register (TSR).
4	BI	Break indicator. The BI bit is set whenever the receive data input (UARTn_RXD) was held low for longer than a full-word transmission time. A full-word transmission time is defined as the total time to transmit the START, data, PARITY, and STOP bits. If the BI bit is set and the corresponding interrupt enable bit is set (ELSI = 1 in IER), an interrupt request is generated. In non-FIFO mode:	R	0x0
		0x0: No break has been detected, or the BI bit was cleared because the CPU read the erroneous character from the receiver buffer register (RBR).
		0x1: A break has been detected with the character in the receiver buffer register (RBR).
		In FIFO mode:
		0x0: No break has been detected, or the BI bit was cleared because the CPU read the erroneous character from the receiver FIFO and the next character to be read from the FIFO has no break indicator.
		0x1: A break has been detected with the character at the top of the receiver FIFO.
3	FE	Framing error (FE) indicator. A framing error occurs when the received character does not have a valid STOP bit. In response to a framing error, the UART sets the FE bit and waits until the signal on the RX pin goes high. Once the RX signal goes high, the receiver is ready to detect a new START bit and receive new data. If the FE bit is set and the corresponding interrupt enable bit is set (ELSI = 1 in IER), an interrupt request is generated. In non-FIFO mode:	R	0x0
		0x0: No framing error has been detected, or the FE bit was cleared because the CPU read the erroneous data from the receiver buffer register (RBR).
		0x1: A framing error has been detected with the character in the receiver buffer register (RBR).
		In FIFO mode:
		0x0: No framing error has been detected, or the FE bit was cleared because the CPU read the erroneous data from the receiver FIFO and the next character to be read from the FIFO has no framing error.
		0x1: A framing error has been detected with the character at the top of the receiver FIFO.
2	PE	Parity error (PE) indicator. A parity error occurs when the parity of the received character does not match the parity selected with the EPS bit in the line control register (LCR). If the PE bit is set and the corresponding interrupt enable bit is set (ELSI = 1 in IER), an interrupt request is generated. In non-FIFO mode:	R	0x0
		0x0: No parity error has been detected, or the PE bit was cleared because the CPU read the erroneous data from the receiver buffer register (RBR).
		0x1: A parity error has been detected with the character in the receiver buffer register (RBR).
		In FIFO mode:
		0x0: No parity error has been detected, or the PE bit was cleared because the CPU read the erroneous data from the receiver FIFO and the next character to be read from the FIFO has no parity error.
		0x1: A parity error has been detected with the character at the top of the receiver FIFO.
1	OE	Overrun error (OE) indicator. An overrun error in the non-FIFO mode is different from an overrun error in the FIFO mode. If the OE bit is set and the corresponding interrupt enable bit is set (ELSI = 1 in IER), an interrupt request is generated. In non-FIFO mode:	R	0x0
		0x0: No overrun error has been detected, or the OE bit was cleared because the CPU read the content of the line status register (LSR).
		0x1: Overrun error has been detected. Before the character in the receiver buffer register (RBR) could be read, it was overwritten by the next character arriving in RBR.
		In FIFO mode:
		0x0: No overrun error has been detected, or the OE bit was cleared because the CPU read the content of the line status register (LSR).
		0x1: Overrun error has been detected. If data continues to fill the FIFO beyond the trigger level, an overrun error occurs only after the FIFO is full and the next character has been completely received in the shift register. An overrun error is indicated to the CPU as soon as it happens. The new character overwrites the character in the shift register, but it is not transferred to the FIFO.
0	DR	Data-ready (DR) indicator for the receiver. If the DR bit is set and the corresponding interrupt enable bit is set (ERBI = 1 in IER), an interrupt request is generated. In non-FIFO mode:	R	0x0
		0x0: Data is not ready, or the DR bit was cleared because the character was read from the receiver buffer register (RBR).
		0x1: Data is ready. A complete incoming character has been received and transferred into the receiver buffer register (RBR).
		In FIFO mode:
		0x0: Data is not ready, or the DR bit was cleared because all of the characters in the receiver FIFO have been read.
		0x1: Data is ready. There is at least one unread character in the receiver FIFO. If the FIFO is empty, the DR bit is set as soon as a complete incoming character has been received and transferred into the FIFO. The DR bit remains set until the FIFO is empty again.

Table 30-236 PRUSS_UART_MODEM_STATUS_REGISTER

Address Offset	0x0000 0018
Physical Address	0x4B22 8018 0x4B2A 8018	Instance	PRUSS1_UART PRUSS2_UART
Description	The Modem status register provides information to the CPU concerning the status of modem control signals. Modem status register is intended for read operations only; do not write to this register.
Type	R

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								CD	RI	DSR	CTS	DCD	TERI	DDSR	DCTS

Bits	Field Name	Description	Type	Reset
31:8	RESERVED	Reserved	R	0x0
7	CD	Complement of the Carrier Detect input. When the UART is in the diagnostic test mode (loopback mode MCR[4] = 1), this bit is equal to the MCR bit 3 (OUT2).	R	0x0
6	RI	Complement of the Ring Indicator input. When the UART is in the diagnostic test mode (loopback mode MCR[4] = 1), this bit is equal to the MCR bit 2 (OUT1).	R	0x0
5	DSR	Complement of the Data Set Ready input. When the UART is in the diagnostic test mode (loopback mode MCR[4] = 1), this bit is equal to the MCR bit 0 (DTR).	R	0x0
4	CTS	Complement of the Clear To Send input. When the UART is in the diagnostic test mode (loopback mode MCR[4] = 1), this bit is equal to the MCR bit 1 (RTS).	R	0x0
3	DCD	Change in DCD indicator bit. DCD indicates that the DCD input has changed state since the last time it was read by the CPU. When DCD is set and the modem status interrupt is enabled, a modem status interrupt is generated.	R	0x0
2	TERI	Trailing edge of RI (TERI) indicator bit. TERI indicates that the RI input has changed from a low to a high. When TERI is set and the modem status interrupt is enabled, a modem status interrupt is generated.	R	0x0
1	DDSR	Change in DSR indicator bit. DDSR indicates that the DSR input has changed state since the last time it was read by the CPU. When DDSR is set and the modem status interrupt is enabled, a modem status interrupt is generated.	R	0x0
0	DCTS	Change in CTS indicator bit. DCTS indicates that the CTS input has changed state since the last time it was read by the CPU. When DCTS is set (autoflow control is not enabled and the modem status interrupt is enabled), a modem status interrupt is generated. When autoflow control is enabled, no interrupt is generated.	R	0x0

Table 30-237 PRUSS_UART_SCRATCH_REGISTER

Address Offset	0x0000 001C
Physical Address	0x4B22 801C 0x4B2A 801C	Instance	PRUSS1_UART PRUSS2_UART
Description	The Scratch Pad register is intended for programmer's use as a scratch pad. It temporarily holds the programmer's data without affecting UART operation.
Type	R

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								SCR

Bits	Field Name	Description	Type	Reset
31:8	RESERVED	Reserved	R	0x0
7:0	SCR	These bits are intended for the programmer's use as a scratch pad in the sense that it temporarily holds the programmer's data without affecting any other UART operation.	R	0x0

Table 30-238 PRUSS_UART_DIVISOR_REGISTER_LSB_

Address Offset	0x0000 0020
Physical Address	0x4B22 8020 0x4B2A 8020	Instance	PRUSS1_UART PRUSS2_UART
Description	Two 8-bit register fields (DLL and DLH), called divisor latches, store the 16-bit divisor for generation of the baud clock in the baud generator. DLH holds the most-significant bits of the divisor, and DLL holds the least-significant bits of the divisor. These divisor latches must be loaded during initialization of the UART in order to ensure desired operation of the baud generator. Writing to the divisor latches results in two wait states being inserted during the write access while the baud generator is loaded with the new value.
Type	RW

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								DLL

Bits	Field Name	Description	Type	Reset
31:8	RESERVED	Reserved	R	0x0
7:0	DLL	The 8 least-significant bits (LSBs) of the 16-bit divisor for generation of the baud clock in the baud rate generator.	RW	0x0

Table 30-239 PRUSS_UART_DIVISOR_REGISTER_MSB_

Address Offset	0x0000 0024
Physical Address	0x4B22 8024 0x4B2A 8024	Instance	PRUSS1_UART PRUSS2_UART
Description	Two 8-bit register fields (DLL and DLH), called divisor latches, store the 16-bit divisor for generation of the baud clock in the baud generator. DLH holds the most-significant bits of the divisor, and DLL holds the least-significant bits of the divisor. These divisor latches must be loaded during initialization of the UART in order to ensure desired operation of the baud generator. Writing to the divisor latches results in two wait states being inserted during the write access while the baud generator is loaded with the new value.
Type	RW

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																								DLH

Bits	Field Name	Description	Type	Reset
31:8	RESERVED	Reserved	R	0x0
7:0	DLH	The 8 most-significant bits (MSBs) of the 16-bit divisor for generation of the baud clock in the baud rate generator.	RW	0x0

Table 30-240 PRUSS_UART_PERIPHERAL_ID_REGISTER

Address Offset	0x0000 0028
Physical Address	0x4B22 8028 0x4B2A 8028	Instance	PRUSS1_UART PRUSS2_UART
Description	Peripheral Identification register
Type	R

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
PID

Bits	Field Name	Description	Type	Reset
31:0	PID		R	0x44141102

Table 30-241 PRUSS_UART_POWERMANAGEMENT_AND_EMULATION_REGISTER

Address Offset	0x0000 0030
Physical Address	0x4B22 8030 0x4B2A 8030	Instance	PRUSS1_UART PRUSS2_UART
Description	Power and emulation management register
Type	RW

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																RESERVED	UTRST	URRST	RESERVED												FREE

Bits	Field Name	Description	Type	Reset
31:16	RESERVED	Reserved	R	0x0000
15	RESERVED	Reserved. This bit must always be written with a 0.	RW	0x0
14	UTRST	UART transmitter reset. Resets and enables the transmitter.	RW	0x0
		0x0: Transmitter is disabled and in reset state.
		0x1: Transmitter is enabled.
13	URRST	UART receiver reset. Resets and enables the receiver.	RW	0x0
		0x0: Receiver is disabled and in reset state.
		0x1: Receiver is enabled.
12:1	RESERVED	Reserved	R	0x000
0	FREE	Free-running enable mode bit. This bit determines the emulation mode functionality of the UART. When halted, the UART can handle register read/write requests, but does not generate any transmission/reception, interrupts or events.	RW	0x0
		0x0: If a transmission is not in progress, the UART halts immediately. If a transmission is in progress, the UART halts after completion of the one-word transmission.
		0x1: Free-running mode is enabled; UART continues to run normally.

Table 30-242 PRUSS_UART_MODE_DEFINITION_REGISTER

Address Offset	0x0000 0034
Physical Address	0x4B22 8034 0x4B2A 8034	Instance	PRUSS1_UART PRUSS2_UART
Description	The Mode definition register determines the over-sampling mode for the UART.
Type	RW

31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
RESERVED																															OSM_SEL

Bits	Field Name	Description	Type	Reset
31:1	RESERVED	Reserved	R	0x0
0	OSM_SEL	Over-Sampling Mode Select.	RW	0x0
		0x0: 16× over-sampling.
		0x1: 13× over-sampling.