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DSP 1 C64x DSP MHz (Max) 850, 1000, 1200 CPU 32-/64-bit Operating system DSP/BIOS Ethernet MAC 10/100/1000 Rating Catalog Operating temperature range (C) 0 to 100, 0 to 95
DSP 1 C64x DSP MHz (Max) 850, 1000, 1200 CPU 32-/64-bit Operating system DSP/BIOS Ethernet MAC 10/100/1000 Rating Catalog Operating temperature range (C) 0 to 100, 0 to 95
  • High-Performance Fixed-Point DSP (C6457)
    • 1.18-ns, 1-ns, and 0.83-ns Instruction Cycle Time/li>
    • 850-MHz, 1-GHz, and 1.2-GHz Clock Rate
    • Eight 32-Bit Instructions/Cycle
    • 8000 and 9600 MIPS/MMACS (16-Bits)
    • Case Temperature
      • Commercial:
        • 0°C to 100°C (850 MHz)
        • 0°C to 100°C (1 GHz)
        • 0°C to 95°C (1.2 GHz)
      • Extended:
        • -40°C to 100°C (1 GHz)
        • -40°C to 95°C (1.2 GHz)
  • TMS320C64x+™ DSP Core
    • Dedicated SPLOOP Instruction
    • Compact Instructions (16-Bit)
    • Instruction Set Enhancements
    • Exception Handling
  • TMS320C64x+ Megamodule L1/L2 Memory Architecture:
    • 256K-Bit (32K-Byte) L1P Program Cache [Direct Mapped]
    • 256K-Bit (32K-Byte) L1D Data Cache [2-Way Set-Associative]
    • 16M-Bit (2048K-Byte) L2 Unified Mapped Ram/Cache [Flexible Allocation]
      • Configurable up to 1MB of L2 Cache
    • 512K-Bit (64K-Byte) L3 ROM
    • Time Stamp Counter
  • Enhanced VCP2
    • Supports Over 694 7.95-Kbps AMR
    • Programmable Code Parameters
  • Two Enhanced Turbo Decoder Coprocessors (TCP2_A and TCP2_B)
    • Each TCP2 Supports up to Eight 2-Mbps 3GPP (6 Iterations)
    • Programmable Turbo Code and Decoding Parameters
  • Endianess: Little Endian, Big Endian
  • 64-Bit External Memory Interface (EMIFA)
    • Glueless Interface to Asynchronous Memories (SRAM, Flash, and EEPROM) and Synchronous Memories (SBSRAM, ZBT SRAM)
    • Supports Interface to Standard Sync Devices and Custom Logic (FPGA, CPLD, ASICs, etc.)
    • 32M-Byte Total Addressable External Memory Space
  • 32-Bit DDR2 Memory Controller (DDR2-667 SDRAM)
  • Four 1× Serial RapidIO® Links (or One 4×), v1.3 Compliant
    • 1.25-, 2.5-, 3.125-Gbps Link Rates
    • Message Passing, DirectIO Support, Error Mgmt Extensions, Congestion Control
    • IEEE 1149.6 Compliant I/Os
  • EDMA3 Controller (64 Independent Channels)
  • 32-/16-Bit Host-Port Interface (HPI)
  • Two 1.8-V McBSPs
  • 10/100/1000 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Supports SGMII, v1.8 Compliant
    • 8 Independent Transmit (TX) and 8 Independent Receive (RX) Channels
  • Two 64-Bit General-Purpose Timers
    • Configurable as Four 32-Bit Timers
    • Configurable in a Watchdog Timer Mode
  • UTOPIA
    • UTOPIA Level 2 Slave ATM Controller
    • 8-Bit Transmit and Receive Operations up to 50 MHz per Direction
    • User-Defined Cell Format up to 64 Bytes
  • One 1.8-V Inter-Integrated Circuit (I2C) Bus
  • 16 General-Purpose I/O (GPIO) Pins
  • System PLL and PLL Controller
  • DDR PLL, Dedicated to DDR2 Memory Controller
  • Advanced Event Triggering (AET) Compatible
  • Trace-Enabled Device
  • Supports IP Security
  • IEEE-1149.1 and IEEE-1149.6 (JTAG™) Boundary-Scan-Compatible
  • 688-Pin Ball Grid Array (BGA) Package (CMH or GMH Suffix), 0.8-mm Ball Pitch
  • 0.065-µm/7-Level Cu Metal Process (CMOS)
  • 3.3-V, 1.8-V, 1.1-V I/Os, 1.1-V and 1.2-V Internal

All trademarks are the property of their respective owners.

  • High-Performance Fixed-Point DSP (C6457)
    • 1.18-ns, 1-ns, and 0.83-ns Instruction Cycle Time/li>
    • 850-MHz, 1-GHz, and 1.2-GHz Clock Rate
    • Eight 32-Bit Instructions/Cycle
    • 8000 and 9600 MIPS/MMACS (16-Bits)
    • Case Temperature
      • Commercial:
        • 0°C to 100°C (850 MHz)
        • 0°C to 100°C (1 GHz)
        • 0°C to 95°C (1.2 GHz)
      • Extended:
        • -40°C to 100°C (1 GHz)
        • -40°C to 95°C (1.2 GHz)
  • TMS320C64x+™ DSP Core
    • Dedicated SPLOOP Instruction
    • Compact Instructions (16-Bit)
    • Instruction Set Enhancements
    • Exception Handling
  • TMS320C64x+ Megamodule L1/L2 Memory Architecture:
    • 256K-Bit (32K-Byte) L1P Program Cache [Direct Mapped]
    • 256K-Bit (32K-Byte) L1D Data Cache [2-Way Set-Associative]
    • 16M-Bit (2048K-Byte) L2 Unified Mapped Ram/Cache [Flexible Allocation]
      • Configurable up to 1MB of L2 Cache
    • 512K-Bit (64K-Byte) L3 ROM
    • Time Stamp Counter
  • Enhanced VCP2
    • Supports Over 694 7.95-Kbps AMR
    • Programmable Code Parameters
  • Two Enhanced Turbo Decoder Coprocessors (TCP2_A and TCP2_B)
    • Each TCP2 Supports up to Eight 2-Mbps 3GPP (6 Iterations)
    • Programmable Turbo Code and Decoding Parameters
  • Endianess: Little Endian, Big Endian
  • 64-Bit External Memory Interface (EMIFA)
    • Glueless Interface to Asynchronous Memories (SRAM, Flash, and EEPROM) and Synchronous Memories (SBSRAM, ZBT SRAM)
    • Supports Interface to Standard Sync Devices and Custom Logic (FPGA, CPLD, ASICs, etc.)
    • 32M-Byte Total Addressable External Memory Space
  • 32-Bit DDR2 Memory Controller (DDR2-667 SDRAM)
  • Four 1× Serial RapidIO® Links (or One 4×), v1.3 Compliant
    • 1.25-, 2.5-, 3.125-Gbps Link Rates
    • Message Passing, DirectIO Support, Error Mgmt Extensions, Congestion Control
    • IEEE 1149.6 Compliant I/Os
  • EDMA3 Controller (64 Independent Channels)
  • 32-/16-Bit Host-Port Interface (HPI)
  • Two 1.8-V McBSPs
  • 10/100/1000 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Supports SGMII, v1.8 Compliant
    • 8 Independent Transmit (TX) and 8 Independent Receive (RX) Channels
  • Two 64-Bit General-Purpose Timers
    • Configurable as Four 32-Bit Timers
    • Configurable in a Watchdog Timer Mode
  • UTOPIA
    • UTOPIA Level 2 Slave ATM Controller
    • 8-Bit Transmit and Receive Operations up to 50 MHz per Direction
    • User-Defined Cell Format up to 64 Bytes
  • One 1.8-V Inter-Integrated Circuit (I2C) Bus
  • 16 General-Purpose I/O (GPIO) Pins
  • System PLL and PLL Controller
  • DDR PLL, Dedicated to DDR2 Memory Controller
  • Advanced Event Triggering (AET) Compatible
  • Trace-Enabled Device
  • Supports IP Security
  • IEEE-1149.1 and IEEE-1149.6 (JTAG™) Boundary-Scan-Compatible
  • 688-Pin Ball Grid Array (BGA) Package (CMH or GMH Suffix), 0.8-mm Ball Pitch
  • 0.065-µm/7-Level Cu Metal Process (CMOS)
  • 3.3-V, 1.8-V, 1.1-V I/Os, 1.1-V and 1.2-V Internal

All trademarks are the property of their respective owners.

The TMS320C64x+™ DSPs (including the TMS320C6457 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The C6457 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for applications including video and telecom infrastructure, imaging/medical, and wireless infrastructure (WI). The C64x+ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform.

Based on 65-nm process technology and with performance of up to 9600 million instructions per second (MIPS) [or 9600 16-bit MMACs per cycle] at a 1.2-GHz clock rate, the C6457 device offers cost-effective solutions to high-performance DSP programming challenges. The C6457 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors.

The C64x+ DSP core employs eight functional units, two register files, and two data paths. Like the earlier C6000 devices, two of these eight functional units are multipliers or .M units. Each C64x+ .M unit doubles the multiply throughput versus the C64x core by performing four 16-bit × 16-bit multiply-accumulates (MACs) every clock cycle. Thus, eight 16-bit × 16-bit MACs can be executed every cycle on the C64x+ core. At a 1.2-GHz clock rate, this means 9600 16-bit MMACs can occur every second. Moreover, each multiplier on the C64x+ core can compute one 32-bit × 32-bit MAC or four 8-bit × 8-bit MACs every clock cycle.

The C6457 device includes Serial RapidIO®. This high-bandwidth peripheral dramatically improves system performance and reduces system cost for applications that include multiple DSPs on a board, such as video and telecom infrastructures and medical/imaging.

The C6457 DSP integrates a large amount of on-chip memory organized as a two-level memory system. The level-1 (L1) program and data memories on the C6457 device are 32KB each. This memory can be configured as mapped RAM, cache, or some combination of the two. When configured as cache, L1 program (L1P) is a direct mapped cache whereas L1 data (L1D) is a two-way set associative cache. The level 2 (L2) memory is shared between program and data space and is 2048KB in size. L2 memory can also be configured as mapped RAM, cache, or some combination of the two. L2 is configurable up to 1MB of cache. The C64x+ Megamodule also has a 32-bit peripheral configuration (CFG) port, an internal DMA (IDMA) controller, a system component with reset/boot control, interrupt/exception control, a power-down control, and a free-running 32-bit timer for time stamp.

The peripheral set includes: an inter-integrated circuit bus module (I2C); two multichannel buffered serial ports (McBSPs); an 8-bit Universal Test and Operations PHY Interface for Asynchronous Transfer Mode (ATM) Slave [UTOPIA Slave] port; two 64-bit general-purpose timers (also configurable as four 32-bit timers); a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a 16-pin general-purpose input/output port (GPIO) with programmable interrupt/event generation modes; an 10/100/1000 Ethernet media access controller (EMAC), which provides an efficient interface between the C6457 DSP core processor and the network; a management data input/output (MDIO) module (also part of the EMAC) that continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system; a glueless external memory interface (64-bit EMIFA), which is capable of interfacing to synchronous and asynchronous peripherals; and a 32-bit DDR2 SDRAM interface.

The C6457 device has three high-performance embedded coprocessors [one enhanced Viterbi Decoder Coprocessor (VCP2) and two enhanced Turbo Decoder Coprocessors (TCP2_A and TCP2_B)] that significantly speed up channel-decoding operations on-chip. The VCP2 operating at CPU clock ÷ 3 can decode more than 694 7.95-Kbps adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels. The VCP2 supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 3/4, 1/2, 1/3, 1/4, and 1/5, and flexible polynomials, while generating hard decisions or soft decisions. Each TCP2 operating at CPU clock ÷ 3 can decode up to fifty 384-Kbps or eight 2-Mbps turbo encoded channels (assuming 6 iterations). The TCP2 implements the max*log-map algorithm and is designed to support all polynomials and rates required by Third-Generation Partnership Projects (3GPP and 3GPP2), with fully programmable frame length and turbo interleaver. Decoding parameters such as the number of iterations and stopping criteria are also programmable. Communications between the VCP2/TCP2s and the CPU are carried out through the EDMA3 controller.

The C6457 device has a complete set of development tools, which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

The TMS320C64x+™ DSPs (including the TMS320C6457 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The C6457 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for applications including video and telecom infrastructure, imaging/medical, and wireless infrastructure (WI). The C64x+ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform.

Based on 65-nm process technology and with performance of up to 9600 million instructions per second (MIPS) [or 9600 16-bit MMACs per cycle] at a 1.2-GHz clock rate, the C6457 device offers cost-effective solutions to high-performance DSP programming challenges. The C6457 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors.

The C64x+ DSP core employs eight functional units, two register files, and two data paths. Like the earlier C6000 devices, two of these eight functional units are multipliers or .M units. Each C64x+ .M unit doubles the multiply throughput versus the C64x core by performing four 16-bit × 16-bit multiply-accumulates (MACs) every clock cycle. Thus, eight 16-bit × 16-bit MACs can be executed every cycle on the C64x+ core. At a 1.2-GHz clock rate, this means 9600 16-bit MMACs can occur every second. Moreover, each multiplier on the C64x+ core can compute one 32-bit × 32-bit MAC or four 8-bit × 8-bit MACs every clock cycle.

The C6457 device includes Serial RapidIO®. This high-bandwidth peripheral dramatically improves system performance and reduces system cost for applications that include multiple DSPs on a board, such as video and telecom infrastructures and medical/imaging.

The C6457 DSP integrates a large amount of on-chip memory organized as a two-level memory system. The level-1 (L1) program and data memories on the C6457 device are 32KB each. This memory can be configured as mapped RAM, cache, or some combination of the two. When configured as cache, L1 program (L1P) is a direct mapped cache whereas L1 data (L1D) is a two-way set associative cache. The level 2 (L2) memory is shared between program and data space and is 2048KB in size. L2 memory can also be configured as mapped RAM, cache, or some combination of the two. L2 is configurable up to 1MB of cache. The C64x+ Megamodule also has a 32-bit peripheral configuration (CFG) port, an internal DMA (IDMA) controller, a system component with reset/boot control, interrupt/exception control, a power-down control, and a free-running 32-bit timer for time stamp.

The peripheral set includes: an inter-integrated circuit bus module (I2C); two multichannel buffered serial ports (McBSPs); an 8-bit Universal Test and Operations PHY Interface for Asynchronous Transfer Mode (ATM) Slave [UTOPIA Slave] port; two 64-bit general-purpose timers (also configurable as four 32-bit timers); a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a 16-pin general-purpose input/output port (GPIO) with programmable interrupt/event generation modes; an 10/100/1000 Ethernet media access controller (EMAC), which provides an efficient interface between the C6457 DSP core processor and the network; a management data input/output (MDIO) module (also part of the EMAC) that continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system; a glueless external memory interface (64-bit EMIFA), which is capable of interfacing to synchronous and asynchronous peripherals; and a 32-bit DDR2 SDRAM interface.

The C6457 device has three high-performance embedded coprocessors [one enhanced Viterbi Decoder Coprocessor (VCP2) and two enhanced Turbo Decoder Coprocessors (TCP2_A and TCP2_B)] that significantly speed up channel-decoding operations on-chip. The VCP2 operating at CPU clock ÷ 3 can decode more than 694 7.95-Kbps adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels. The VCP2 supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 3/4, 1/2, 1/3, 1/4, and 1/5, and flexible polynomials, while generating hard decisions or soft decisions. Each TCP2 operating at CPU clock ÷ 3 can decode up to fifty 384-Kbps or eight 2-Mbps turbo encoded channels (assuming 6 iterations). The TCP2 implements the max*log-map algorithm and is designed to support all polynomials and rates required by Third-Generation Partnership Projects (3GPP and 3GPP2), with fully programmable frame length and turbo interleaver. Decoding parameters such as the number of iterations and stopping criteria are also programmable. Communications between the VCP2/TCP2s and the CPU are carried out through the EDMA3 controller.

The C6457 device has a complete set of development tools, which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

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No design support from TI available

This product does not have ongoing design support from TI for new projects, such as new content or software updates. If available, you will find relevant collateral, software and tools in the product folder. You can also search for archived information in the TI E2ETM support forums.

技术文档

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类型 项目标题 下载最新的英语版本 日期
* 数据表 TMS320C6457 Fixed-Point Digital Signal Processor 数据表 (Rev. B) 09 Jul 2010
* 勘误表 TMS320C6457 DSP Silicon Errata (Silicon Revisions 1.0, 1.1, 1.2) (Rev. A) 22 Jan 2010
应用手册 如何将 CCS 3.x 工程迁移至最新的 Code Composer Studio™ (CCS) (Rev. A) 下载英文版本 (Rev.A) PDF | HTML 19 May 2021
用户指南 SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V) 01 Jun 2020
应用手册 FFT PDF | HTML 11 Jun 2019
应用手册 TMS320TCI6484 and TMS320C6457 SERDES Implementation Guidelines (Rev. B) 30 Apr 2019
技术文章 Difficult to see. Always in motion is the future 04 Jan 2016
技术文章 Announcing the new entry-level Sitara processor 09 Dec 2015
技术文章 Automotive Surround View Technology trends 31 Aug 2015
技术文章 Solar Inverter Gateways Made Simple with AM335x 28 Jul 2015
应用手册 Error Detection and Correction Mechanism of TMS320C64x+/C674x (Rev. A) 19 Jul 2013
用户指南 TMS320C6457 DSP EMAC / MDIO User's Guide (Rev. A) 02 May 2012
应用手册 Power Consumption Guide for the C66x 06 Oct 2011
用户指南 TMS320C6457 DSP DDR2 Memory Controller User's Guide (Rev. D) 22 Jun 2011
用户指南 Bootloader User's Guide for the TMS320C645x/C647x (Rev. G) 03 Jun 2011
应用手册 TMS320C6457 Power Consumption Application Report (Rev. A) 25 Mar 2011
应用手册 Tuning VCP2 and TCP2 Bit Error Rate Performance Application Note 11 Feb 2011
用户指南 TMS320C6457 DSP Serial RapidIO (SRIO) User's Guide (Rev. D) 03 Feb 2011
用户指南 TMS320C64x+ DSP Megamodule Reference Guide (Rev. K) 03 Aug 2010
用户指南 TMS320C6457 DSP External Memory Interface (EMIF) User's Guide (Rev. B) 30 Jul 2010
用户指南 TMS320C6457 DSP Host Port Interface (HPI) User's Guide (Rev. A) 30 Jul 2010
用户指南 TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (Rev. J) 30 Jul 2010
用户指南 TMS320C6457 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (Rev. A) 18 May 2010
应用手册 TMS320C6457/TMS320TCI6484/TMS320TCI6487/88 DDR2 Implementation Guidelines (Rev. D) 28 Jan 2010
用户指南 TMS320C6457 DSP Viterbi-Decoder Coprocessor 2 Reference (VCP2) Guide (Rev. A) 08 Dec 2009
用户指南 TMS320C6457 DSP Inter-Integrated Circuit (I2C) Module User's Guide (Rev. A) 28 Oct 2009
应用手册 TMS320TCI6484 and TMS320C6457 DSPs Hardware Design Guide (Rev. B) 08 Oct 2009
用户指南 TMS320C6457 DSP 64-Bit Timer User’s Guide 11 Mar 2009
用户指南 TMS320C6457 DSP Enhanced DMA Controller User's Guide 11 Mar 2009
用户指南 TMS320C6457 DSP General-Purpose Input/Output User's Guide 11 Mar 2009
用户指南 TMS320C6457 DSP Power/Sleep Controller User's Guide 11 Mar 2009
用户指南 TMS320C6457 DSP Turbo-Decoder Coprocessor 2 Reference Guide 11 Mar 2009
用户指南 TMS320C6457 DSP Universal Test&Operations PHY Interface for ATM 2 User's Guide 11 Mar 2009
用户指南 TMS320C6457 DSP Software-Programmable Phase-Locked Loop Controller User's Guide 11 Mar 2008
应用手册 TMS320C64x to TMS320C64x+ CPU Migration Guide (Rev. A) 20 Oct 2005
用户指南 High-Speed DSP Systems Design Reference Guide 20 May 2005

设计和开发

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调试探针

TMDSEMU200-U — Spectrum Digital XDS200 USB 仿真器

Spectrum Digital XDS200 是最新 XDS200 系列 TI 处理器调试探针(仿真器)的首个模型。XDS200 系列拥有超低成本 XDS100 与高性能 XDS560v2 之间的低成本与高性能的完美平衡。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS 调试探针均支持内核和系统跟踪。

Spectrum Digital XDS200 通过 TI 20 引脚连接器(带有适合 TI 14 引脚、TI 10 引脚和 ARM 20 引脚的多个适配器)连接到目标板,而通过 USB2.0 高速连接 (480Mbps) 连接到主机 PC。要在主机 (...)

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调试探针

TMDSEMU560V2STM-U — XDS560™ software v2 system trace USB debug probe

XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针(仿真器)的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件,通过捕获相关器件级信息,获得准确的总线性能活动和吞吐量,并对内核和外设进行电源管理。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS (...)

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调试探针

TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 系统跟踪 USB 和以太网

XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针(仿真器)的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件,通过捕获相关器件级信息,获得准确的总线性能活动和吞吐量,并对内核和外设进行电源管理。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS (...)

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软件开发套件 (SDK)

BIOSMCSDK-C64XPLUS 用于 C647x 和 C645x 的 SYS/BIOS MCSDK

NOTE: K2x, C665x and C667x devices are now actively maintained on the Processor-SDK release stream. See links above.

Our Multicore Software Development Kits (MCSDK) provide highly-optimized bundles of foundational, platform-specific drivers to enable development on selected TI ARM and DSP devices. (...)

支持的产品和硬件

支持的产品和硬件

产品
数字信号处理器 (DSP)
TMS320C6457 通信基础设施数字信号处理器
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软件开发套件 (SDK)

BIOSMCSDK-C66X 用于 C66x 的 SYS/BIOS MCSDK

NOTE: K2x, C665x and C667x devices are now actively maintained on the Processor-SDK release stream. See links above.

Our Multicore Software Development Kits (MCSDK) provide highly-optimized bundles of foundational, platform-specific drivers to enable development on selected TI ARM and DSP devices. (...)

支持的产品和硬件

支持的产品和硬件

产品
数字信号处理器 (DSP)
TMS320C6457 通信基础设施数字信号处理器 TMS320C6657 高性能双核 C66x 定点和浮点 DSP- 高达 1.25GHz、2 UART TMS320C6670 用于通信和电信的 4 核定点和浮点 DSP TMS320C6678 高性能八核 C66x 定点和浮点 DSP- 高达 1.25GHz
硬件开发
下载选项
软件开发套件 (SDK)

LINUXMCSDK 用于 C66x、C647x 和 C645x 的 Linux MCSDK

NOTE: K2x, C665x and C667x devices are now actively maintained on the Processor-SDK release stream. See links above.

Our Multicore Software Development Kits (MCSDK) provide highly-optimized bundles of foundational, platform-specific drivers to enable development on selected TI ARM and DSP devices. (...)

支持的产品和硬件

支持的产品和硬件

产品
数字信号处理器 (DSP)
TMS320C6455 C64x+ 定点 DSP - 高达 1.2GHz、64 位 EMIFA、32/16 位 DDR2、1Gbps 以太网 TMS320C6457 通信基础设施数字信号处理器 TMS320C6472 定点数字信号处理器 TMS320C6474 多核数字信号处理器 TMS320C6670 用于通信和电信的 4 核定点和浮点 DSP TMS320C6678 高性能八核 C66x 定点和浮点 DSP- 高达 1.25GHz
硬件开发
TMDSDSK6455 TMS320C6455 DSP 入门套件 (DSK)
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软件开发套件 (SDK)

MEDIMGSTK-C66X 用于医疗成像的 TI 嵌入式处理器软件工具套件 (STK-MED) - 用于基于 C66x 和 C64x+ 的处理器

The TI Embedded Processor Software Toolkit for Medical Imaging (STK-MED) is a collection of several standard ultrasound and optical coherence tomography (OCT) algorithms for TI’s C66x™ and C64x+™ architecture. The algorithms showcase how medical imaging functions can leverage the C66x and (...)
支持的产品和硬件

支持的产品和硬件

产品
数字信号处理器 (DSP)
DM505 适用于视觉分析的 SoC,采用 15mm 封装 SM320C6678-HIREL 高可靠性产品高性能 8 核 C6678 定点和浮点 DSP TMS320C6454 C64x+ 定点 DSP - 高达 1GHz、64 位 EMIFA、32/16 位 DDR2、1Gbps 以太网 TMS320C6455 C64x+ 定点 DSP - 高达 1.2GHz、64 位 EMIFA、32/16 位 DDR2、1Gbps 以太网 TMS320C6457 通信基础设施数字信号处理器 TMS320C6472 定点数字信号处理器 TMS320C6474 多核数字信号处理器
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驱动程序或库

AEC-AER 用于 TI C64x+、C674x、C55x 和 Cortex(tm)A8 处理器的回声抵消/消除 - 即刻可得

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

支持的产品和硬件

支持的产品和硬件

产品
基于 Arm 的处理器
66AK2G12 高性能多核 DSP+Arm - 1 个 Arm A15 内核、1 个 C66x DSP 内核
数字信号处理器 (DSP)
DM505 适用于视觉分析的 SoC,采用 15mm 封装 SM320C6201-EP 增强型产品 C6201 定点 DSP SM320C6415 军用级 C64x 定点 DSP SM320C6415-EP 增强型产品 C6415 定点 DSP SM320C6424-EP 增强型产品 C6424 定点 DSP SM320C6455-EP 增强型产品 C6455 定点 DSP SM320C6472-HIREL 高可靠性产品 6 核 C6472 定点 DSP SM320C6678-HIREL 高可靠性产品高性能 8 核 C6678 定点和浮点 DSP SM320C6701 用于军事应用的单核 C67x 浮点 DSP - 高达 167MHz SM320C6701-EP 增强型产品 C6701 浮点 DSP SM320C6711D-EP 增强型产品 C6711D 浮点 DSP SM320C6712D-EP 增强型产品 C6712D DSP SM320C6713B-EP 增强型产品 C6713 浮点 DSP SM320C6727B 军用级 C6727B 浮点 DSP SM320C6727B-EP 增强型产品 C6727 浮点 DSP SM320DM642-HIREL 高可靠性产品数字媒体 DM642 DSP SM32C6416T-EP 增强型产品 C6416T 定点 DSP SMJ320C6201B 军用定点数字信号处理器 SMJ320C6203 军用级 C62x 定点 DSP - 陶瓷封装 SMJ320C6415 军用级 C64x 定点 DSP - 陶瓷封装 SMJ320C6701 军用级 C67x 浮点 DSP - 陶瓷封装 SMJ320C6701-SP 航天级 C6701 浮点 DSP - 抗辐射 V 类、采用陶瓷封装 SMV320C6727B-SP 航天级 C6727B 浮点 DSP - 抗辐射 V 类、采用陶瓷封装 TMS320C5517 低功耗 C55x 定点 DSP- 高达 200MHz、USB、LCD 接口、FFT HWA、SAR ADC TMS320C5532 低功耗 C55x 定点 DSP- 高达 100MHz TMS320C5533 低功耗 C55x 定点 DSP- 高达 100MHz、USB TMS320C5534 低功耗 C55x 定点 DSP- 高达 100MHz、USB、LCD 接口 TMS320C5535 低功耗 C55x 定点 DSP- 高达 100MHz、USB、LCD 接口、FFT HWA、SAR ADC TMS320C6201 定点数字信号处理器 TMS320C6202 定点数字信号处理器 TMS320C6202B C62x 定点 DSP- 高达 300MHz、384KB TMS320C6203B C62x 定点 DSP- 高达 300MHz、896KB TMS320C6204 定点数字信号处理器 TMS320C6205 定点数字信号处理器 TMS320C6211B C62x 定点 DSP- 高达 167MHz TMS320C6411 C64x 定点 DSP- 高达 300MHz、McBSP TMS320C6414 C64x 定点 DSP- 高达 720MHz、McBSP TMS320C6415 C64x 定点 DSP- 高达 720MHz、McBSP、PCI TMS320C6416 C64x 定点 DSP- 高达 720MHz、McBSP、PCI、VCP/TCP TMS320C6421Q C64x+ 定点 DSP- 高达 600MHz、8 位 EMIFA、16 位 DDR2 TMS320C6424Q C64x+ 定点 DSP- 高达 600MHz、16/8 位 EMIFA、32/16 位 DDR2 TMS320C6454 C64x+ 定点 DSP - 高达 1GHz、64 位 EMIFA、32/16 位 DDR2、1Gbps 以太网 TMS320C6457 通信基础设施数字信号处理器 TMS320C6701 C67x 浮点 DSP- 高达 167MHz、McBSP TMS320C6711D C67x 浮点 DSP- 高达 250MHz、McBSP、32 位 EMIFA TMS320C6712D C67x 浮点 DSP- 高达 150MHz、McBSP、16 位 EMIFA TMS320C6720 C67x 浮点 DSP - 200MHz、McASP、16 位 EMIFA TMS320C6722B C67x 浮点 DSP- 高达 250MHz、McASP、16 位 EMIFA TMS320C6726B C67x 浮点 DSP- 高达 266MHz、McASP、16 位 EMIFA TMS320C6727 C67x 浮点 DSP- 高达 250MHz、McASP、32 位 EMIFA TMS320C6727B C67x 浮点 DSP- 高达 350MHz、McASP、32 位 EMIFA TMS320C6743 低功耗 C674x 浮点 DSP- 375MHz TMS320C6745 低功耗 C674x 浮点 DSP- 456MHz、QFP TMS320C6747 低功耗 C674x 浮点 DSP- 456MHz、PBGA TMS320DM642Q 视频/成像定点数字信号处理器 TMS320DM6431Q 数字媒体处理器,性能高达 2400MIPS、300MHz 时钟速率 TMS320DM6435Q 数字媒体处理器,性能高达 4800MIPS、600MHz 时钟速率、1 个 McASP、1 个 McBSP TMS320DM6437Q 数字媒体处理器,性能高达 4800MIPS、600MHz 时钟速率、1 个 McASP、2 个 McBSP TMS320DM6441 达芬奇数字媒体片上系统 TMS320DM6467T 数字媒体片上系统 TMS320DM647 数字媒体处理器
下载选项
驱动程序或库

FAXLIB 用于 C66x、C64x+ 和 C55x 处理器的传真库 (FAXLIB)

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

支持的产品和硬件

支持的产品和硬件

产品
基于 Arm 的处理器
66AK2G12 高性能多核 DSP+Arm - 1 个 Arm A15 内核、1 个 C66x DSP 内核
数字信号处理器 (DSP)
DM505 适用于视觉分析的 SoC,采用 15mm 封装 SM320C6201-EP 增强型产品 C6201 定点 DSP SM320C6415 军用级 C64x 定点 DSP SM320C6415-EP 增强型产品 C6415 定点 DSP SM320C6424-EP 增强型产品 C6424 定点 DSP SM320C6455-EP 增强型产品 C6455 定点 DSP SM320C6472-HIREL 高可靠性产品 6 核 C6472 定点 DSP SM320C6678-HIREL 高可靠性产品高性能 8 核 C6678 定点和浮点 DSP SM320C6701 用于军事应用的单核 C67x 浮点 DSP - 高达 167MHz SM320C6701-EP 增强型产品 C6701 浮点 DSP SM320C6711D-EP 增强型产品 C6711D 浮点 DSP SM320C6712D-EP 增强型产品 C6712D DSP SM320C6713B-EP 增强型产品 C6713 浮点 DSP SM320C6727B 军用级 C6727B 浮点 DSP SM320C6727B-EP 增强型产品 C6727 浮点 DSP SM320DM642-HIREL 高可靠性产品数字媒体 DM642 DSP SM32C6416T-EP 增强型产品 C6416T 定点 DSP SMJ320C6201B 军用定点数字信号处理器 SMJ320C6203 军用级 C62x 定点 DSP - 陶瓷封装 SMJ320C6415 军用级 C64x 定点 DSP - 陶瓷封装 SMJ320C6701 军用级 C67x 浮点 DSP - 陶瓷封装 SMJ320C6701-SP 航天级 C6701 浮点 DSP - 抗辐射 V 类、采用陶瓷封装 SMV320C6727B-SP 航天级 C6727B 浮点 DSP - 抗辐射 V 类、采用陶瓷封装 TMS320C5517 低功耗 C55x 定点 DSP- 高达 200MHz、USB、LCD 接口、FFT HWA、SAR ADC TMS320C5532 低功耗 C55x 定点 DSP- 高达 100MHz TMS320C5533 低功耗 C55x 定点 DSP- 高达 100MHz、USB TMS320C5534 低功耗 C55x 定点 DSP- 高达 100MHz、USB、LCD 接口 TMS320C5535 低功耗 C55x 定点 DSP- 高达 100MHz、USB、LCD 接口、FFT HWA、SAR ADC TMS320C6201 定点数字信号处理器 TMS320C6202 定点数字信号处理器 TMS320C6202B C62x 定点 DSP- 高达 300MHz、384KB TMS320C6203B C62x 定点 DSP- 高达 300MHz、896KB TMS320C6204 定点数字信号处理器 TMS320C6205 定点数字信号处理器 TMS320C6211B C62x 定点 DSP- 高达 167MHz TMS320C6411 C64x 定点 DSP- 高达 300MHz、McBSP TMS320C6414 C64x 定点 DSP- 高达 720MHz、McBSP TMS320C6415 C64x 定点 DSP- 高达 720MHz、McBSP、PCI TMS320C6416 C64x 定点 DSP- 高达 720MHz、McBSP、PCI、VCP/TCP TMS320C6421Q C64x+ 定点 DSP- 高达 600MHz、8 位 EMIFA、16 位 DDR2 TMS320C6424Q C64x+ 定点 DSP- 高达 600MHz、16/8 位 EMIFA、32/16 位 DDR2 TMS320C6454 C64x+ 定点 DSP - 高达 1GHz、64 位 EMIFA、32/16 位 DDR2、1Gbps 以太网 TMS320C6457 通信基础设施数字信号处理器 TMS320C6701 C67x 浮点 DSP- 高达 167MHz、McBSP TMS320C6711D C67x 浮点 DSP- 高达 250MHz、McBSP、32 位 EMIFA TMS320C6712D C67x 浮点 DSP- 高达 150MHz、McBSP、16 位 EMIFA TMS320C6720 C67x 浮点 DSP - 200MHz、McASP、16 位 EMIFA TMS320C6722B C67x 浮点 DSP- 高达 250MHz、McASP、16 位 EMIFA TMS320C6726B C67x 浮点 DSP- 高达 266MHz、McASP、16 位 EMIFA TMS320C6727 C67x 浮点 DSP- 高达 250MHz、McASP、32 位 EMIFA TMS320C6727B C67x 浮点 DSP- 高达 350MHz、McASP、32 位 EMIFA TMS320C6743 低功耗 C674x 浮点 DSP- 375MHz TMS320C6745 低功耗 C674x 浮点 DSP- 456MHz、QFP TMS320C6747 低功耗 C674x 浮点 DSP- 456MHz、PBGA TMS320DM642Q 视频/成像定点数字信号处理器 TMS320DM6431Q 数字媒体处理器,性能高达 2400MIPS、300MHz 时钟速率 TMS320DM6435Q 数字媒体处理器,性能高达 4800MIPS、600MHz 时钟速率、1 个 McASP、1 个 McBSP TMS320DM6437Q 数字媒体处理器,性能高达 4800MIPS、600MHz 时钟速率、1 个 McASP、2 个 McBSP TMS320DM6441 达芬奇数字媒体片上系统 TMS320DM6467T 数字媒体片上系统 TMS320DM647 数字媒体处理器
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驱动程序或库

SPRC122 — C62x/C64x 快速运行时支持 (RTS) 库

C62x/64x FastRTS Library 是优化型浮点函数库,适用于使用 TMS320C62x 或 TMS320C64x 器件的 C 语言编程器。这些例程通常用于计算密集型实时应用,在这些应用中,提高执行速度至关重要。通过将当前的浮点库 (RTS) 函数替换为 FastRTS Library,可以在不重写现有代码的情况下大大加快执行速度。

该版本还包括 FastRTS Library 中可用函数子集的 C 语言实施。C 代码可让用户内联这些函数并获得更高性能。

特性

单精度和双精度数学函数 单精度和双精度转换函数
浮点加法 将浮点值转换为 32 位带符号整数值
将 32 位带符号整数值转换为浮点值
(...)
用户指南: PDF
驱动程序或库

SPRC264 — TMS320C6000 图像库 (IMGLIB)

C5000/6000 Image Processing Library (IMGLIB) is an optimized image/video processing function library for C programmers. It includes C-callable general-purpose image/video processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
用户指南: PDF
驱动程序或库

SPRC265 — TMS320C6000 DSP 库 (DSPLIB)

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
用户指南: PDF
驱动程序或库

SPRC542 — C64x+ IQMath 库 - 虚拟浮点引擎

Texas Instruments TMS320C64x+ IQmath Library is collection of highly optimized and high precision mathematical Function Library for C/C++ programmers to seamlessly port the floating-point algorithm into fixed point code on TMS320C64x+ devices. These routines are typically used in computationally (...)
用户指南: PDF
驱动程序或库

SPRC924 — 用于 C6457 的芯片支持库

此版本的 TMS320C6457 CSL 包含适用于 C6457 模块的外设编程(功能和寄存器级)API。该 API 集提供了可供更高软件层使用的外设抽象。
驱动程序或库

VOLIB 用于 C66x、C64x+ 和 C55x 处理器的音频库 (VoLIB)

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

支持的产品和硬件

支持的产品和硬件

产品
基于 Arm 的处理器
66AK2G12 高性能多核 DSP+Arm - 1 个 Arm A15 内核、1 个 C66x DSP 内核
数字信号处理器 (DSP)
DM505 适用于视觉分析的 SoC,采用 15mm 封装 SM320C6201-EP 增强型产品 C6201 定点 DSP SM320C6415 军用级 C64x 定点 DSP SM320C6415-EP 增强型产品 C6415 定点 DSP SM320C6424-EP 增强型产品 C6424 定点 DSP SM320C6455-EP 增强型产品 C6455 定点 DSP SM320C6472-HIREL 高可靠性产品 6 核 C6472 定点 DSP SM320C6678-HIREL 高可靠性产品高性能 8 核 C6678 定点和浮点 DSP SM320C6701 用于军事应用的单核 C67x 浮点 DSP - 高达 167MHz SM320C6701-EP 增强型产品 C6701 浮点 DSP SM320C6711D-EP 增强型产品 C6711D 浮点 DSP SM320C6712D-EP 增强型产品 C6712D DSP SM320C6713B-EP 增强型产品 C6713 浮点 DSP SM320C6727B 军用级 C6727B 浮点 DSP SM320C6727B-EP 增强型产品 C6727 浮点 DSP SM320DM642-HIREL 高可靠性产品数字媒体 DM642 DSP SM32C6416T-EP 增强型产品 C6416T 定点 DSP SMJ320C6201B 军用定点数字信号处理器 SMJ320C6203 军用级 C62x 定点 DSP - 陶瓷封装 SMJ320C6415 军用级 C64x 定点 DSP - 陶瓷封装 SMJ320C6701 军用级 C67x 浮点 DSP - 陶瓷封装 SMJ320C6701-SP 航天级 C6701 浮点 DSP - 抗辐射 V 类、采用陶瓷封装 SMV320C6727B-SP 航天级 C6727B 浮点 DSP - 抗辐射 V 类、采用陶瓷封装 TMS320C5517 低功耗 C55x 定点 DSP- 高达 200MHz、USB、LCD 接口、FFT HWA、SAR ADC TMS320C5532 低功耗 C55x 定点 DSP- 高达 100MHz TMS320C5533 低功耗 C55x 定点 DSP- 高达 100MHz、USB TMS320C5534 低功耗 C55x 定点 DSP- 高达 100MHz、USB、LCD 接口 TMS320C5535 低功耗 C55x 定点 DSP- 高达 100MHz、USB、LCD 接口、FFT HWA、SAR ADC TMS320C6201 定点数字信号处理器 TMS320C6202 定点数字信号处理器 TMS320C6202B C62x 定点 DSP- 高达 300MHz、384KB TMS320C6203B C62x 定点 DSP- 高达 300MHz、896KB TMS320C6204 定点数字信号处理器 TMS320C6205 定点数字信号处理器 TMS320C6211B C62x 定点 DSP- 高达 167MHz TMS320C6411 C64x 定点 DSP- 高达 300MHz、McBSP TMS320C6414 C64x 定点 DSP- 高达 720MHz、McBSP TMS320C6415 C64x 定点 DSP- 高达 720MHz、McBSP、PCI TMS320C6416 C64x 定点 DSP- 高达 720MHz、McBSP、PCI、VCP/TCP TMS320C6421Q C64x+ 定点 DSP- 高达 600MHz、8 位 EMIFA、16 位 DDR2 TMS320C6424Q C64x+ 定点 DSP- 高达 600MHz、16/8 位 EMIFA、32/16 位 DDR2 TMS320C6454 C64x+ 定点 DSP - 高达 1GHz、64 位 EMIFA、32/16 位 DDR2、1Gbps 以太网 TMS320C6457 通信基础设施数字信号处理器 TMS320C6701 C67x 浮点 DSP- 高达 167MHz、McBSP TMS320C6711D C67x 浮点 DSP- 高达 250MHz、McBSP、32 位 EMIFA TMS320C6712D C67x 浮点 DSP- 高达 150MHz、McBSP、16 位 EMIFA TMS320C6720 C67x 浮点 DSP - 200MHz、McASP、16 位 EMIFA TMS320C6722B C67x 浮点 DSP- 高达 250MHz、McASP、16 位 EMIFA TMS320C6726B C67x 浮点 DSP- 高达 266MHz、McASP、16 位 EMIFA TMS320C6727 C67x 浮点 DSP- 高达 250MHz、McASP、32 位 EMIFA TMS320C6727B C67x 浮点 DSP- 高达 350MHz、McASP、32 位 EMIFA TMS320C6743 低功耗 C674x 浮点 DSP- 375MHz TMS320C6745 低功耗 C674x 浮点 DSP- 456MHz、QFP TMS320C6747 低功耗 C674x 浮点 DSP- 456MHz、PBGA TMS320DM642Q 视频/成像定点数字信号处理器 TMS320DM6431Q 数字媒体处理器,性能高达 2400MIPS、300MHz 时钟速率 TMS320DM6435Q 数字媒体处理器,性能高达 4800MIPS、600MHz 时钟速率、1 个 McASP、1 个 McBSP TMS320DM6437Q 数字媒体处理器,性能高达 4800MIPS、600MHz 时钟速率、1 个 McASP、2 个 McBSP TMS320DM6441 达芬奇数字媒体片上系统 TMS320DM6467T 数字媒体片上系统 TMS320DM647 数字媒体处理器
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IDE、配置、编译器或调试器

CCSTUDIO Code Composer Studio 集成式开发环境 (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It comprises a suite of tools used to develop and debug embedded applications.  Code Composer Studio is available for download across Windows®, Linux® and macOS® (...)

支持的产品和硬件

支持的产品和硬件

此设计资源支持这些类别中的大部分产品。

查看产品详情页,确认是否能提供支持

产品
汽车毫米波雷达传感器
AWR1243 76GHz 至 81GHz 高性能汽车类 MMIC AWR1443 集成 MCU 和硬件加速器的单芯片 76GHz 至 81GHz 汽车雷达传感器 AWR1642 集成 DSP 和 MCU 的单芯片 76GHz 至 81GHz 汽车雷达传感器 AWR1843 集成 DSP、MCU 和雷达加速器的单芯片 76GHz 至 81GHz 汽车雷达传感器 AWR1843AOP Single-chip 76-GHz to 81-GHz automotive radar sensor integrating antenna on package, DSP and MCU AWR2243 76GHz 至 81GHz 汽车类第二代高性能 MMIC AWR2944 适用于角雷达和远距离雷达的汽车类第二代 76GHz 至 81GHz 高性能 SoC AWR6443 Single-chip 60-GHz to 64-GHz automotive radar sensor integrating MCU and radar accelerator AWR6843 集成 DSP、MCU 和雷达加速器的单芯片 60GHz 至 64GHz 汽车雷达传感器 AWR6843AOP 集成封装天线、DSP 和 MCU 的单芯片 60GHz 至 64GHz 汽车雷达传感器
工业毫米波雷达传感器
IWR1443 集成 MCU 和硬件加速器的 76GHz 至 81GHz 单芯片毫米波传感器 IWR1642 集成 DSP 和 MCU 的 76GHz 至 81GHz 单芯片毫米波传感器 IWR1843 集成 DSP、MCU 和雷达加速器的 76GHz 至 81GHz 单芯片工业雷达传感器 IWR6443 集成 MCU 和硬件加速器的 60GHz 至 64GHz 单芯片毫米波传感器 IWR6843 集成有处理功能的 60GHz 至 64GHz 单芯片智能毫米波传感器 IWR6843AOP 具有集成封装天线 (AoP) 的单芯片 60GHz 至 64GHz 智能毫米波传感器
在云端开发 下载选项
软件编解码器

ADT-3P-DSPVOIPCODECS — 自适应数字技术 DSP VOIP、语音和音频编解码器

Adaptive Digital 是音质增强算法的开发公司,提供可与 TI DSP 配合使用的一流声学回声消除软件。Adaptive Digital 在算法开发、实施、优化和配置调优方面具有丰富的经验。他们提供适用于语音技术、音质软件、回声消除、会议软件、语音压缩算法的解决方案和即用型解决方案。

如需了解有关 Adaptive Digital 的更多信息,请访问 https://www.adaptivedigital.com
软件编解码器

C64XPLUSCODECSPCH 用于 C64x+ 器件的语音编解码器

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into video and voice applications. Click GET SOFTWARE button (above) to access the most recent, tested codec versions available. Datasheets and Release Notes are on (...)

支持的产品和硬件

支持的产品和硬件

产品
数字信号处理器 (DSP)
TMS320C6457 通信基础设施数字信号处理器 TMS320DM6437Q 数字媒体处理器,性能高达 4800MIPS、600MHz 时钟速率、1 个 McASP、2 个 McBSP TMS320DM6441 达芬奇数字媒体片上系统 TMS320DM6467T 数字媒体片上系统
下载选项
软件编解码器

C64XPLUSCODECSVID C64x+ 视频编解码器 - 软件和文档

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into video and voice applications. Click GET SOFTWARE button (above) to access the most recent, tested codec versions available. Datasheets and Release Notes are on (...)

支持的产品和硬件

支持的产品和硬件

产品
数字信号处理器 (DSP)
TMS320C6457 通信基础设施数字信号处理器 TMS320DM6437Q 数字媒体处理器,性能高达 4800MIPS、600MHz 时钟速率、1 个 McASP、2 个 McBSP TMS320DM6441 达芬奇数字媒体片上系统 TMS320DM6467T 数字媒体片上系统
下载选项
软件编解码器

COUTH-3P-DSPVOIPCODECS — CouthIT DSP VoIP、语音和音频编解码器

自 1999 年以来,CouthIT 一直帮助客户将其理念转换成强大可靠的实时软件解决方案。CouthIT 许可在 VoIP 以及语音和音频编解码器领域内使用预先构建且高度优化的专用软件模块,并为多媒体应用提供软件优化和定制服务。我们的目标客户是寻求 DSP 平台(包括 TI C5000™ DSP)上嵌入式软件模块支持的 OEM 和 ODM。

如需了解有关 CouthIT 的更多信息,请访问 http://www.couthit.com
软件编解码器

VOCAL-3P-DSPVOIPCODECS — Vocal Technologies DSP VoIP 编解码器

经过 25 年以上的组装和 C 代码开发,VOCAL 的模块化软件套件可用于各种各样的 TI DSP 产品。产品具体包括 ATA、VoIP 服务器和网关、基于 HPNA 的 IPBX、视频监控、语音和视频会议、语音和数据射频器件、RoIP 网关、政务安全器件、合法拦截软件、医疗设备、嵌入式调制解调器、T.38 传真和 FoIP。

如需了解有关 Vocal Technologies 的更多信息,请访问 https://www.vocal.com
仿真模型

C6457 CMH IBIS Model (Rev. A)

SPRM360A.ZIP (524 KB) - IBIS Model
仿真模型

C6457 CMH and GMH BSDL Model

SPRM381.ZIP (17 KB) - BSDL Model
设计工具

PROCESSORS-3P-SEARCH — Arm®-based MPU, Arm-based MCU and DSP third-party search tool

TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)
封装 引脚数 下载
(CMH) 688 了解详情

订购和质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 认证摘要
  • 持续可靠性监测

支持与培训

视频