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参数

DSP 1 C67x On-chip L2 cache/RAM 512 KB Operating system DSP/BIOS DRAM SDRAM Serial I/O McASP, SPI, I2C I2C 2 SPI 2 Operating temperature range (C) 0 to 90 Rating Catalog open-in-new 查找其它 C6000 浮点 DSP

封装|引脚|尺寸

HTQFP (RFP) 144 484 mm² 22 x 22 open-in-new 查找其它 C6000 浮点 DSP

特性

  • C672x: 32-/64-Bit 350-MHz Floating-Point DSPs
  • Upgrades to C67x+ CPU From C67x™ DSP Generation:
    • 2X CPU Registers [64 General-Purpose]
    • New Audio-Specific Instructions
    • Compatible With the C67x CPU
  • Enhanced Memory System
    • 256K-Byte Unified Program/Data RAM
    • 384K-Byte Unified Program/Data ROM
    • Single-Cycle Data Access From CPU
    • Large Program Cache (32K Byte) Supports RAM, ROM, and External Memory
  • External Memory Interface (EMIF) Supports
    • 133-MHz SDRAM (16- or 32-Bit)
    • Asynchronous NOR Flash, SRAM (8-,16-, or 32-Bit)
    • NAND Flash (8- or 16-Bit)
  • Enhanced I/O System
    • High-Performance Crossbar Switch
    • Dedicated McASP DMA Bus
    • Deterministic I/O Performance
  • dMAX (Dual Data Movement Accelerator) Supports:
    • 16 Independent Channels
    • Concurrent Processing of Two Transfer Requests
    • 1-, 2-, and 3-Dimensional Memory-to-Memory and Memory-to-Peripheral Data Transfers
    • Circular Addressing Where the Size of a Circular Buffer (FIFO) is not Limited to 2n
    • Table-Based Multi-Tap Delay Read and Write Transfers From/To a Circular Buffer
  • Three Multichannel Audio Serial Ports
    • Transmit/Receive Clocks up to 50 MHz
    • Six Clock Zones and 16 Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
    • DIT-Capable (McASP2)
  • Universal Host-Port Interface (UHPI)
    • 32-Bit-Wide Data Bus for High Bandwidth
    • Muxed and Non-Muxed Address and Data
  • Two 10-MHz SPI Ports With 3-, 4-, and 5-Pin Options
  • Two Inter-Integrated Circuit (I2C) Ports
  • Real-Time Interrupt Counter/Watchdog
  • Oscillator- and Software-Controlled PLL
  • Applications:
    • Professional Audio
      • Mixers
      • Effects Boxes
      • Audio Synthesis
      • Instrument/Amp Modeling
      • Audio Conferencing
      • Audio Broadcast
      • Audio Encoder
    • Emerging Audio Applications
    • Biometrics
    • Medical
    • Industrial
  • Commercial or Extended Temperature
  • 144-Pin, 0.5-mm, PowerPAD™ Thin Quad Flatpack (TQFP) [RFP Suffix]
  • 256-Terminal, 1.0-mm, 16x16 Array Plastic Ball Grid Array (PBGA) [GDH and ZDH Suffixes]

C67x, PowerPAD, TMS320C6000, C6000, DSP/BIOS, XDS, TMS320 are trademarks of Texas Instruments.
Philips is a registered trademark of Koninklijki Philips Electronics N.V.
All other trademarks are the property of their respective owners.

open-in-new 查找其它 C6000 浮点 DSP

描述

The TMS320C672x is the next generation of Texas Instruments' C67x generation of high-performance 32-/64-bit floating-point digital signal processors. The TMS320C672x includes the TMS320C6727B, TMS320C6726B, TMS320C6722B, and TMS320C6720 devices.(1)

Enhanced C67x+ CPU. The C67x+ CPU is an enhanced version of the C67x CPU used on the C671x DSPs. It is compatible with the C67x CPU but offers significant improvements in speed, code density, and floating-point performance per clock cycle. At 350 MHz, the CPU is capable of a maximum performance of 2800 MIPS/2100 MFLOPS by executing up to eight instructions (six of which are floating-point instructions) in parallel each cycle. The CPU natively supports 32-bit fixed-point, 32-bit single-precision floating-point, and 64-bit double-precision floating-point arithmetic.

Efficient Memory System. The memory controller maps the large on-chip 256K-byte RAM and 384K-byte ROM as unified program/data memory. Development is simplified since there is no fixed division between program and data memory size as on some other devices.

The memory controller supports single-cycle data accesses from the C67x+ CPU to the RAM and ROM. Up to three parallel accesses to the internal RAM and ROM from three of the following four sources are supported:

  • Two 64-bit data accesses from the C67x+ CPU
  • One 256-bit program fetch from the core and program cache
  • One 32-bit data access from the peripheral system (either dMAX or UHPI)

The large (32K-byte) program cache translates to a high hit rate for most applications. This prevents most program/data access conflicts to the on-chip memory. It also enables effective program execution from an off-chip memory such as an SDRAM.

High-Performance Crossbar Switch. A high-performance crossbar switch acts as a central hub between the different bus masters (CPU, dMAX, UHPI) and different targets (peripherals and memory). The crossbar is partially connected; some connections are not supported (for example, UHPI-to-peripheral connections).

Multiple transfers occur in parallel through the crossbar as long as there is no conflict between bus masters for a particular target. When a conflict does occur, the arbitration is a simple and deterministic fixed-priority scheme.

The dMAX is given highest-priority since it is responsible for the most time-critical I/O transfers, followed next by the UHPI, and finally by the CPU.

dMAX Dual Data Movement Accelerator. The dMAX is a module designed to perform Data Movement Acceleration. The Data Movement Accelerator (dMAX) controller handles user-programmed data transfers between the internal data memory controller and the device peripherals on the C672x DSPs. The dMAX allows movement of data to/from any addressable memory space including internal memory, peripherals, and external memory.

The dMAX controller includes features such as the capability to perform three-dimensional data transfers for advanced data sorting, and the capability to manage a section of the memory as a circular buffer/FIFO with delay-tap based reading and writing of data. The dMAX controller is capable of concurrently processing two transfer requests (provided that they are to/from different source/destinations).

External Memory Interface (EMIF) for Flexibility and Expansion. The external memory interface on the C672x supports a single bank of SDRAM and a single bank of asynchronous memory. The EMIF data width is 16 bits wide on the C6726B, C6722B, and C6720 and 32 bits wide on the C6727B.

SDRAM support includes x16 and x32 SDRAM devices with 1, 2, or 4 banks.

The C6726B, C6722B, and C6720 support SDRAM devices up to 128M bits.

The C6727B extends SDRAM support to 256M-bit and 512M-bit devices.

Asynchronous memory support is typically used to boot from a parallel non-multiplexed NOR flash device that can be 8, 16, or 32 bits wide. Booting from larger flash devices than are natively supported by the dedicated EMIF address lines is accomplished by using general-purpose I/O pins for upper address lines.

The asynchronous memory interface can also be configured to support 8- or 16-bit-wide NAND flash. It includes a hardware ECC calculation (for single-bit errors) that can operate on blocks of data up to 512 bytes.

Universal Host-Port Interface (UHPI) for High-Speed Parallel I/O. The Universal Host-Port Interface (UHPI) is a parallel interface through which an external host CPU can access memories on the DSP.

Three modes are supported by the C672x UHPI:

  • Multiplexed Address/Data - Half-Word (16-bit-wide) Mode (similar to C6713)
  • Multiplexed Address/Data - Full Word (32-bit-wide) Mode
  • Non-Multiplexed Mode - 16-bit Address and 32-bit Data Bus

The UHPI can also be restricted to accessing a single page (64K bytes) of memory anywhere in the address space of the C672x; this page can be changed, but only by the C672x CPU. This feature allows the UHPI to be used for high-speed data transfers even in systems where security is an important requirement.

The UHPI is only available on the C6727B.

Multichannel Audio Serial Ports (McASP0, McASP1, and McASP2) - Up to 16 Stereo Channels I2S. The multichannel audio serial port (McASP) seamlessly interfaces to CODECs, DACs, ADCs, and other devices. It supports the ubiquitous IIS format as well as many variations of this format, including time division multiplex (TDM) formats with up to 32 time slots.

Each McASP includes a transmit and receive section which may operate independently or synchronously; furthermore, each section includes its own flexible clock generator and extensive error-checking logic.

As data passes through the McASP, it can be realigned so that the fixed-point representation used by the application code can be independent of the representation used by the external devices without requiring any CPU overhead to make the conversion.

The McASP is a configurable module and supports between 2 and 16 serial data pins. It also has the option of supporting a Digital Interface Transmitter (DIT) mode with a full 384 bits of channel status and user data memory.

McASP2 is not available on the C6722B and C6720.

Inter-Integrated Circuit Serial Ports (I2C0, I2C1). The C672x includes two inter-integrated circuit (I2C) serial ports. A typical application is to configure one I2C serial port as a slave to an external user-interface microcontroller. The other I2C serial port may then be used by the C672x DSP to control external peripheral devices, such as a CODEC or network controller, which are functionally peripherals of the DSP device.

The two I2C serial ports are pin-multiplexed with the SPI0 serial port.

Serial Peripheral Interface Ports (SPI0, SPI1). As in the case of the I2C serial ports, the C672x DSP also includes two serial peripheral interface (SPI) serial ports. This allows one SPI port to be configured as a slave to control the DSP while the other SPI serial port is used by the DSP to control external peripherals.

The SPI ports support a basic 3-pin mode as well as optional 4- and 5-pin modes. The optional pins include a slave chip-select pin and an enable pin which implements handshaking automatically in hardware for maximum SPI throughput.

The SPI0 port is pin-multiplexed with the two I2C serial ports (I2C0 and I2C1). The SPI1 serial port is pin-multiplexed with five of the serial data pins from McASP0 and McASP1.

Real-Time Interrupt Timer (RTI). The real-time interrupt timer module includes:

  • Two 32-bit counter/prescaler pairs
  • Two input captures (tied to McASP direct memory access [DMA] events for sample rate measurement)
  • Four compares with automatic update capability
  • Digital Watchdog (optional) for enhanced system robustness

Clock Generation (PLL and OSC). The C672x DSP includes an on-chip oscillator that supports crystals in the range of 12 MHz to 25 MHz. Alternatively, the clock can be provided externally through the CLKIN pin.

The DSP includes a flexible, software-programmable phase-locked loop (PLL) clock generator. Three different clock domains (SYSCLK1, SYSCLK2, and SYSCLK3) are generated by dividing down the PLL output. SYSCLK1 is the clock used by the CPU, memory controller, and memories. SYSCLK2 is used by the peripheral subsystem and dMAX. SYSCLK3 is used exclusively for the EMIF.

(1) Throughout the remainder of the document, TMS320C6727B (or C6727B), TMS320C6726B (or C6726B), TMS320C6722B (or C6722B), and/or TMS320C6720 (or C6720) will be referred to as TMS320C672x (or C672x).

open-in-new 查找其它 C6000 浮点 DSP
下载

Special Note

The current ROM version for TMS320C672x DSPs, C9230C100, contains a system initialization error. Download the patch from the Tools & Software section of this product folder. For more details, see the application note number SPRS277.

技术文档

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类型 标题 下载最新的英文版本 日期
* 数据表 TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point DSPs 数据表 2008年 7月 11日
* 勘误表 TMS320C6727/B, TMS320C6726/B, TMS32C6722/B, TMS320C6720 DSPs Silicon Errata 2008年 10月 23日
应用手册 How to Migrate Old CCS 3.x Projects to the Latest CCS 2020年 2月 6日
用户指南 TMS320C6000 Assembly Language Tools v 7.3 User's Guide 2012年 8月 21日
用户指南 TMS320C6000 Optimizing Compiler v 7.3 User's Guide 2012年 8月 21日
应用手册 Power Consumption Guide for the C66x 2011年 10月 6日
用户指南 TMS320C6000 Assembly Language Tools v 7.0 User's Guide 2010年 3月 18日
用户指南 TMS320C6000 Optimizing Compiler v 7.0 User's Guide 2010年 3月 18日
应用手册 Using the TMS320C672x Bootloader 2009年 9月 10日
应用手册 常用对象文件格式 (COFF) 2009年 4月 15日
应用手册 CSL - 2 Application Report 2008年 7月 11日
用户指南 TMS320C6000 Assembly Language Tools v 6.1 User's Guide 2008年 5月 15日
用户指南 TMS320C6000 Optimizing Compiler v 6.1 User's Guide 2008年 5月 15日
用户指南 TMS320C672x DSP Multichannel Audio Serial Port (McASP) Reference Guide 2008年 3月 13日
应用手册 Using ROM Contents on TMS320C672x 2008年 2月 5日
用户指南 TMS320C672x DSP Inter-Integrated Circuit (I2C) Module Reference Guide 2007年 12月 11日
用户指南 TMS320C672x DSP Dual Data Movement Accelerator (dMAX) Reference Guide 2007年 10月 12日
用户指南 TMS320C672x DSP Serial Peripheral Interface (SPI) Reference Guide 2007年 7月 12日
应用手册 Thermal Considerations Application Report 2007年 5月 20日
用户指南 TMS320C672x DSP External Memory Interface (EMIF) User's Guide 2007年 4月 2日
用户指南 TMS320C67x/C67x+ DSP CPU and Instruction Set Reference Guide 2006年 11月 7日
更多文献资料 TMS320C672x Floating-Point DSPs Product Bulletin 2006年 10月 20日
应用手册 C9230C100 TMS320C672x Floating-Point Digital Signal Processor ROM 2006年 9月 25日
应用手册 TMS320C672x Hardware Designer's Resource Guide 2006年 9月 22日
应用手册 TMS320C672x Power Consumption Summary 2006年 9月 22日
用户指南 TMS320C672x DSP Peripherals Overview Reference Guide 2006年 6月 25日
应用手册 How to Create Delay-based Audio Effects on a TMS320C6727 DSP 2005年 11月 1日
应用手册 TMS320C6713 to TMS320C672x Migration Guide 2005年 5月 23日
用户指南 TMS320C672x DSP Software-Programmable Phase-Locked Loop (PLL) Controller RG 2005年 5月 23日
用户指南 TMS320C672x DSP Real-Time Interrupt Reference Guide 2005年 4月 13日

设计与开发

有关其他条款或所需资源,请点击下面的任何链接来查看详情页面。

软件开发

调试探测 下载
Blackhawk XDS560v2 系统跟踪 USB 仿真器
TMDSEMU560V2STM-U XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针(仿真器)的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件,通过捕获相关器件级信息,获得准确的总线性能活动和吞吐量,并对内核和外设进行电源管理。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS 调试探针均支持内核和系统跟踪。

Blackhawk XDS560v2 System Trace 通过 MIPI HSPT 60 引脚连接器(带有适合 TI 14 引脚、TI 20 引脚和 ARM 20 (...)

995
特性

XDS560v2 是 XDS560 系列高性能 TI 处理器调试探针(仿真器)的最新型号。XDS560v2 具有整个系列中最快的速度和最多的功能,对于 TI 微控制器、处理器和无线连接微控制器的调试来说,它是最全面的解决方案。

XDS560v2 是 XDS560 调试探针系列中最先提供系统跟踪 (STM) 功能的一款,这种类型的跟踪可以通过捕获系统事件(例如处理内核的状态、内部总线和外设)来监控整个设备。大多数 XDS560v2 模型还提供系统引脚跟踪模式,在这种模式中,系统跟踪数据被送到 XDS560v2 内的外部存储器缓冲区 (128MB),因此能够捕获大量系统事件。系统引脚跟踪数据连接需要通过额外的接线连接 JTAG 连接器。

在 XDS560 调试探针系列中,XDS560v2 PRO TRACE 是提供内核引脚跟踪功能(指令和数据)的第二代产品,这种跟踪可以捕获内核执行的所有指令并将其发送到 XDS560v2 PRO TRACE 内的外部存储器缓冲区 (1GB)。内核引脚跟踪并不干扰系统的实时行为,而且可以捕获更多的指令。内核引脚跟踪数据连接需要通过额外的接线连接 JTAG 连接器。

为了支持所有类型的引脚跟踪(指令和系统),XDS560v2 的所有型号都提供标准的 60 引脚 MIPI HSPT 连接器作为与目标之间的主要 JTAG 连接。此外,所有型号都提供针对 TI 和 ARM 标准 JTAG 连接器的模块化目标适配器(提供的适配器因型号而异)。

XDS560v2 支持传统的 IEEE1149.1 (JTAG) 仿真和 IEEE1149.7 (cJTAG),运行时的 JTAG 接口电平为 1.2V 至 +4.1V。

与传统 JTAG 相比,紧凑 JTAG (cJTAG) 有巨大的进步;因为它仅需使用两个引脚即可支持所有功能,可用于某些指定的 TI 无线连接微控制器中。

所有 XDS560v2 (...)

调试探测 下载
Spectrum Digital XDS560v2 系统跟踪 USB 和以太网
TMDSEMU560V2STM-UE XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针(仿真器)的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件,通过捕获相关器件级信息,获得准确的总线性能活动和吞吐量,并对内核和外设进行电源管理。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS 调试探针均支持内核和系统跟踪。

Spectrum Digital XDS560v2 System Trace 通过 MIPI HSPT 60 引脚连接器(适合 TI 14 引脚、TI 20 引脚、ARM 20 引脚和 TI 60 (...)

1495
特性

XDS560v2 是 XDS560 系列高性能 TI 处理器调试探针(仿真器)的最新型号。XDS560v2 具有整个系列中最快的速度和最多的功能,对于 TI 微控制器、处理器和无线连接微控制器的调试来说,它是最全面的解决方案。

XDS560v2 是 XDS560 调试探针系列中最先提供系统跟踪 (STM) 功能的一款,这种类型的跟踪可以通过捕获系统事件(例如处理内核的状态、内部总线和外设)来监控整个设备。大多数 XDS560v2 模型还提供系统引脚跟踪模式,在这种模式中,系统跟踪数据被送到 XDS560v2 内的外部存储器缓冲区 (128MB),因此能够捕获大量系统事件。系统引脚跟踪数据连接需要通过额外的接线连接 JTAG 连接器。

在 XDS560 调试探针系列中,XDS560v2 PRO TRACE 是提供内核引脚跟踪功能(指令和数据)的第二代产品,这种跟踪可以捕获内核执行的所有指令并将其发送到 XDS560v2 PRO TRACE 内的外部存储器缓冲区 (1GB)。内核引脚跟踪并不干扰系统的实时行为,而且可以捕获更多的指令。内核引脚跟踪数据连接需要通过额外的接线连接 JTAG 连接器。

为了支持所有类型的引脚跟踪(指令和系统),XDS560v2 的所有型号都提供标准的 60 引脚 MIPI HSPT 连接器作为与目标之间的主要 JTAG 连接。此外,所有型号都提供针对 TI 和 ARM 标准 JTAG 连接器的模块化目标适配器(提供的适配器因型号而异)。

XDS560v2 支持传统的 IEEE1149.1 (JTAG) 仿真和 IEEE1149.7 (cJTAG),运行时的 JTAG 接口电平为 1.2V 至 +4.1V。

与传统 JTAG 相比,紧凑 JTAG (cJTAG) 有巨大的进步;因为它仅需使用两个引脚即可支持所有功能,可用于某些指定的 TI 无线连接微控制器中。

所有 XDS560v2 (...)

驱动程序和库 下载
用于浮点器件的 DSP 数学函数库
MATHLIB — 德州仪器 (TI) 数学库是优化的浮点数学函数库,用于使用 TI 浮点器件的 C 编程器。这些例程通常用于计算密集型实时应用,最佳执行速度是这些应用的关键。通过使用这些例程(而不是在现有运行时支持中找到的例程),您可以在无需重写现有代码的情况下获得更快的执行速度。MATHLIB 库包括目前在现有实时支持库中提供的所有浮点数学例程。这些新函数可称为当前实时支持库名称或包含在数学库中的新名称。
特性
  • 自然 C 源码
  • 优化的 C 代码,具有内建运算符
  • 手工编码、经汇编语言优化的例程
  • C 调用的例程,可内联且与 TMS320C6000 编译器完全兼容
  • 接受单样片或向量输入的例程
  • 提供的函数经 C 模型和现有实时支持函数测试
  • 基准(周期和代码大小)
  • 使用代码生成工具 v7.2.0 进行编译
    驱动程序和库 下载
    TMS320C6000 DSP 库 (DSPLIB)
    SPRC265 TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
    特性

    Optimized DSP routines including functions for:

    • Adaptive filtering
    • Correlation
    • FFT
    • Filtering and convolution: FIR, biquad, IIR, convolution
    • Math: Dot products, max value, min value, etc.
    • Matrix operations
    驱动程序和库 下载
    IDE、配置、编译器和调试器 下载
    C6000 代码生成工具 - 编译器
    C6000-CGT — TI C6000 C/C++ 编译器和汇编语言工具支持开发适用于 TI C6000 数字信号处理器平台的应用,包括 C66x 多核处理器、C674x 和 C64x+ 单核数字信号处理器。
    特性
    • 在 v8.3.0 和更高版本的 C6000 代码生成工具中提供:
      • 支持 C++14 标准 ISO/IEC 14882:2014(不再支持 C++03)
    • 在 v8.2.0 和更高版本的 C6000 代码生成工具中提供:
      • 将浮点值转换为无符号字符或短整型字符时,不再生成 RTS 库调用
      • 提高了 OpenCL-C 矢量类型的性能
    • 在 v8.1.0 和更高版本的 C6000 代码生成工具中提供:
      • 编译 OpenCL-C 内核时,缩短了编译时间,减小了内存使用量

    TI 编译器支持

    TI 拥有一个快速响应的活跃 E2E™ 社区,该社区为 TI 编译器提供了支持。
    支持软件 下载
    TMS310C672x ROM C9230C100 启动器系统初始化路径
    SPRC203 Patch Code, FastRts(V1.20)/DSPLIB (V2.00) ROM Examples & Libraries, and Boot Configuration Utlities + Boot Examples

    System Patch V2.00.00 , FastRts(1.20), DSPLIB (V2.00), genBootCfg(1.0030), genAIS(1.03.06)

    设计工具和仿真

    仿真模型 下载
    SPRM212.ZIP (3 KB) - BSDL Model
    仿真模型 下载
    SPRM213.ZIP (32 KB) - IBIS Model

    CAD/CAE 符号

    封装 引脚 下载
    HTQFP (RFP) 144 了解详情

    订购与质量

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