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TMS320C6747

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低功耗 C674x 浮点 DSP- 456MHz、PBGA

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TMS320C6747

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产品详情

CPU 32-/64-bit Frequency (MHz) 375, 456 Display type 1 Features 1 RTC, 3 enhanced-capture peripherals Operating system SYS/BIOS Rating Catalog Operating temperature range (°C) -40 to 125
CPU 32-/64-bit Frequency (MHz) 375, 456 Display type 1 Features 1 RTC, 3 enhanced-capture peripherals Operating system SYS/BIOS Rating Catalog Operating temperature range (°C) -40 to 125
PBGA (ZKB) 256 289 mm² (17 mm × 17 mm)
  • Software Support
    • TI DSP/BIOS™
    • Chip Support Library and DSP Library
  • 375- and 456-MHz TMS320C674x VLIW DSP
  • C674x Instruction Set Features
    • Superset of the C67x+ and C64x+ ISAs
    • Up to 3648 MIPS and 2736 MFLOPS C674x
    • Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • Compact 16-Bit Instructions
  • C674x Two-Level Cache Memory Architecture
    • 32KB of L1P Program RAM/Cache
    • 32KB of L1D Data RAM/Cache
    • 256KB of L2 Unified Mapped RAM/Cache
    • Flexible RAM/Cache Partition (L1 and L2)
  • Enhanced Direct Memory Access Controller 3 (EDMA3):
    • 2 Transfer Controllers
    • 32 Independent DMA Channels
    • 8 Quick DMA Channels
    • Programmable Transfer Burst Size
  • TMS320C674x Fixed- and Floating-Point VLIW DSP Core
    • Load-Store Architecture with Nonaligned Support
    • 64 General-Purpose Registers (32-Bit)
    • Six ALU (32- and 40-Bit) Functional Units
      • Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
      • Supports up to Four SP Additions Per Clock, Four DP Additions Every 2 Clocks
      • Supports up to Two Floating-Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
    • Two Multiply Functional Units
      • Mixed-Precision IEEE Floating Point Multiply Supported up to:
        • 2 SP x SP -> SP Per Clock
        • 2 SP x SP -> DP Every Two Clocks
        • 2 SP x DP -> DP Every Three Clocks
        • 2 DP x DP -> DP Every Four Clocks
      • Fixed-Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Hardware Support for Modulo Loop
      Operation
    • Protected Mode Operation
    • Exceptions Support for Error Detection and Program Redirection
  • 128KB of RAM Shared Memory (TMS320C6747 Only)
  • 3.3-V LVCMOS I/Os (Except for USB Interfaces)
  • Two External Memory Interfaces:
    • EMIFA
      • NOR (8- or 16-Bit-Wide Data)
      • NAND (8- or 16-Bit-Wide Data)
      • 16-Bit SDRAM with 128-MB Address Space (TMS320C6747 Only)
    • EMIFB
      • 32-Bit or 16-Bit SDRAM with 256-MB Address Space (TMS320C6747)
      • 16-Bit SDRAM with 128-MB Address Space (TMS320C6745)
  • Three Configurable 16550-Type UART Modules:
    • UART0 with Modem Control Signals
    • Autoflow Control Signals (CTS, RTS) on UART0 Only
    • 16-Byte FIFO
    • 16x or 13x Oversampling Option
  • LCD Controller (TMS320C6747 Only)
  • Two Serial Peripheral Interfaces (SPIs) Each with One Chip Select
  • Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO)
  • Two Master and Slave Inter-Integrated Circuit (I2C Bus™)
  • One Host-Port Interface (HPI) with 16-Bit-Wide Muxed Address/Data Bus for High Bandwidth (TMS320C6747 Only)
  • Programmable Real-Time Unit Subsystem (PRUSS)
    • Two Independent Programmable Realtime Unit (PRU) Cores
      • 32-Bit Load and Store RISC Architecture
      • 4KB of Instruction RAM per Core
      • 512 Bytes of Data RAM per Core
      • PRUSS can be Disabled via Software to Save Power
    • Standard Power-Management Mechanism
      • Clock Gating
      • Entire Subsystem Under a Single PSC Clock Gating Domain
    • Dedicated Interrupt Controller
    • Dedicated Switched Central Resource
  • USB 1.1 OHCI (Host) with Integrated PHY (USB1) (TMS320C6747 Only)
  • USB 2.0 OTG Port with Integrated PHY (USB0)
    • USB 2.0 High- and Full-Speed Client (TMS320C6747)
    • USB 2.0 Full-Speed Client (TMS320C6745)
    • USB 2.0 High-, Full-, and Low-Speed Host (TMS320C6747)
    • USB 2.0 Full- and Low-Speed Host (TMS320C6745)
    • High-Speed Functionality Available on TMS320C6747 Device Only
    • End Point 0 (Control)
    • End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) RX and TX
  • Three Multichannel Audio Serial Ports (McASPs):
    • TMS320C6747 Supports 3 McASPs
    • TMS320C6745 Supports 2 McASPs
    • Six Clock Zones and 28 Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
    • DIT-Capable (McASP2)
    • FIFO Buffers for Transmit and Receive
  • 10/100 Mbps Ethernet MAC (EMAC):
    • IEEE 802.3 Compliant (3.3-V I/O Only)
    • RMII Media-Independent Interface
    • Management Data I/O (MDIO) Module
  • Real-Time Clock with 32-kHz Oscillator and Separate Power Rail (TMS320C6747 Only)
  • One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
  • One 64-Bit General-Purpose Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
  • Three Enhanced Pulse Width Modulators (eHRPWMs):
    • Dedicated 16-Bit Time-Base Counter with Period and Frequency Control
    • 6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs
    • Dead-Band Generation
    • PWM Chopping by High-Frequency Carrier
    • Trip Zone Input
  • Three 32-Bit Enhanced Capture (eCAP) Modules:
    • Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
    • Single-Shot Capture of up to Four Event Time-Stamps
  • Two 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
  • TMS320C6747 Device:
    • 256-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZKB Suffix], 1.0-mm Ball Pitch
  • TMS320C6745 Device:
    • 176-pin PowerPAD™ Plastic Quad Flat Pack [PTP suffix], 0.5-mm Pin Pitch
  • Commercial, Industrial, Extended, or Automotive Temperature
  • Software Support
    • TI DSP/BIOS™
    • Chip Support Library and DSP Library
  • 375- and 456-MHz TMS320C674x VLIW DSP
  • C674x Instruction Set Features
    • Superset of the C67x+ and C64x+ ISAs
    • Up to 3648 MIPS and 2736 MFLOPS C674x
    • Byte-Addressable (8-, 16-, 32-, and 64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • Compact 16-Bit Instructions
  • C674x Two-Level Cache Memory Architecture
    • 32KB of L1P Program RAM/Cache
    • 32KB of L1D Data RAM/Cache
    • 256KB of L2 Unified Mapped RAM/Cache
    • Flexible RAM/Cache Partition (L1 and L2)
  • Enhanced Direct Memory Access Controller 3 (EDMA3):
    • 2 Transfer Controllers
    • 32 Independent DMA Channels
    • 8 Quick DMA Channels
    • Programmable Transfer Burst Size
  • TMS320C674x Fixed- and Floating-Point VLIW DSP Core
    • Load-Store Architecture with Nonaligned Support
    • 64 General-Purpose Registers (32-Bit)
    • Six ALU (32- and 40-Bit) Functional Units
      • Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point
      • Supports up to Four SP Additions Per Clock, Four DP Additions Every 2 Clocks
      • Supports up to Two Floating-Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle
    • Two Multiply Functional Units
      • Mixed-Precision IEEE Floating Point Multiply Supported up to:
        • 2 SP x SP -> SP Per Clock
        • 2 SP x SP -> DP Every Two Clocks
        • 2 SP x DP -> DP Every Three Clocks
        • 2 DP x DP -> DP Every Four Clocks
      • Fixed-Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Hardware Support for Modulo Loop
      Operation
    • Protected Mode Operation
    • Exceptions Support for Error Detection and Program Redirection
  • 128KB of RAM Shared Memory (TMS320C6747 Only)
  • 3.3-V LVCMOS I/Os (Except for USB Interfaces)
  • Two External Memory Interfaces:
    • EMIFA
      • NOR (8- or 16-Bit-Wide Data)
      • NAND (8- or 16-Bit-Wide Data)
      • 16-Bit SDRAM with 128-MB Address Space (TMS320C6747 Only)
    • EMIFB
      • 32-Bit or 16-Bit SDRAM with 256-MB Address Space (TMS320C6747)
      • 16-Bit SDRAM with 128-MB Address Space (TMS320C6745)
  • Three Configurable 16550-Type UART Modules:
    • UART0 with Modem Control Signals
    • Autoflow Control Signals (CTS, RTS) on UART0 Only
    • 16-Byte FIFO
    • 16x or 13x Oversampling Option
  • LCD Controller (TMS320C6747 Only)
  • Two Serial Peripheral Interfaces (SPIs) Each with One Chip Select
  • Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO)
  • Two Master and Slave Inter-Integrated Circuit (I2C Bus™)
  • One Host-Port Interface (HPI) with 16-Bit-Wide Muxed Address/Data Bus for High Bandwidth (TMS320C6747 Only)
  • Programmable Real-Time Unit Subsystem (PRUSS)
    • Two Independent Programmable Realtime Unit (PRU) Cores
      • 32-Bit Load and Store RISC Architecture
      • 4KB of Instruction RAM per Core
      • 512 Bytes of Data RAM per Core
      • PRUSS can be Disabled via Software to Save Power
    • Standard Power-Management Mechanism
      • Clock Gating
      • Entire Subsystem Under a Single PSC Clock Gating Domain
    • Dedicated Interrupt Controller
    • Dedicated Switched Central Resource
  • USB 1.1 OHCI (Host) with Integrated PHY (USB1) (TMS320C6747 Only)
  • USB 2.0 OTG Port with Integrated PHY (USB0)
    • USB 2.0 High- and Full-Speed Client (TMS320C6747)
    • USB 2.0 Full-Speed Client (TMS320C6745)
    • USB 2.0 High-, Full-, and Low-Speed Host (TMS320C6747)
    • USB 2.0 Full- and Low-Speed Host (TMS320C6745)
    • High-Speed Functionality Available on TMS320C6747 Device Only
    • End Point 0 (Control)
    • End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) RX and TX
  • Three Multichannel Audio Serial Ports (McASPs):
    • TMS320C6747 Supports 3 McASPs
    • TMS320C6745 Supports 2 McASPs
    • Six Clock Zones and 28 Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
    • DIT-Capable (McASP2)
    • FIFO Buffers for Transmit and Receive
  • 10/100 Mbps Ethernet MAC (EMAC):
    • IEEE 802.3 Compliant (3.3-V I/O Only)
    • RMII Media-Independent Interface
    • Management Data I/O (MDIO) Module
  • Real-Time Clock with 32-kHz Oscillator and Separate Power Rail (TMS320C6747 Only)
  • One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
  • One 64-Bit General-Purpose Watchdog Timer (Configurable as Two 32-Bit General-Purpose Timers)
  • Three Enhanced Pulse Width Modulators (eHRPWMs):
    • Dedicated 16-Bit Time-Base Counter with Period and Frequency Control
    • 6 Single Edge, 6 Dual Edge Symmetric, or 3 Dual Edge Asymmetric Outputs
    • Dead-Band Generation
    • PWM Chopping by High-Frequency Carrier
    • Trip Zone Input
  • Three 32-Bit Enhanced Capture (eCAP) Modules:
    • Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) Outputs
    • Single-Shot Capture of up to Four Event Time-Stamps
  • Two 32-Bit Enhanced Quadrature Encoder Pulse (eQEP) Modules
  • TMS320C6747 Device:
    • 256-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZKB Suffix], 1.0-mm Ball Pitch
  • TMS320C6745 Device:
    • 176-pin PowerPAD™ Plastic Quad Flat Pack [PTP suffix], 0.5-mm Pin Pitch
  • Commercial, Industrial, Extended, or Automotive Temperature

The TMS320C6745/6747 device is a low-power digital signal processor based on a TMS320C674x DSP core. It consumes significantly lower power than other members of the TMS320C6000™ platform of DSPs.

The TMS320C6745/6747 device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring high processing performance .

The TMS320C6745/6747 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32-KB direct mapped cache and the Level 1 data cache (L1D) is a 32-KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 256-KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by other hosts in the system, an additional 128KB of RAM shared memory (TMS320C6747 only) is available for use by other hosts without affecting DSP performance.

The peripheral set includes: a 10/100 Mbps Ethernet MAC (EMAC) with a management data input/output (MDIO) module; two I2C Bus interfaces; 3 multichannel audio serial ports (McASPs) with 16/9 serializers and FIFO buffers; two 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host-port interface (HPI) [TMS320C6747 only]; up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UART interfaces (one with both RTS and CTS); three enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two 32-bit enhanced quadrature encoded pulse (eQEP) peripherals; and 2 external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the TMS320C6745/6747 device and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The TMS320C6745/6747 device is a low-power digital signal processor based on a TMS320C674x DSP core. It consumes significantly lower power than other members of the TMS320C6000™ platform of DSPs.

The TMS320C6745/6747 device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring high processing performance .

The TMS320C6745/6747 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32-KB direct mapped cache and the Level 1 data cache (L1D) is a 32-KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 256-KB memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by other hosts in the system, an additional 128KB of RAM shared memory (TMS320C6747 only) is available for use by other hosts without affecting DSP performance.

The peripheral set includes: a 10/100 Mbps Ethernet MAC (EMAC) with a management data input/output (MDIO) module; two I2C Bus interfaces; 3 multichannel audio serial ports (McASPs) with 16/9 serializers and FIFO buffers; two 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host-port interface (HPI) [TMS320C6747 only]; up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UART interfaces (one with both RTS and CTS); three enhanced high-resolution pulse width modulator (eHRPWM) peripherals; three 32-bit enhanced capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; two 32-bit enhanced quadrature encoded pulse (eQEP) peripherals; and 2 external memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the TMS320C6745/6747 device and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbps and 100 Mbps in either half- or full-duplex mode. Additionally, an MDIO interface is available for PHY configuration.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.
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技术文档

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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 TMS320C6745, TMS320C6747 Fixed- and Floating-Point Digital Signal Processor 数据表 (Rev. F) PDF | HTML 2014-6-17
* 用户指南 TMS320C6745/C6747 DSP Technical Reference Manual (Rev. D) 2016-9-21
* 用户指南 OMAP-L137 C6000 DSP+ARM Processor Technical Reference Manual (Rev. D) 2016-9-21
* 勘误表 TMS320C6747 Fixed/Floating-Point DSP SE (Silicon Revs 3.0, 2.1, 2.0, 1.1, & 1.0) (Rev. G) 2014-6-17
应用手册 如何将 CCS 3.x 工程迁移至最新的 Code Composer Studio™ (CCS) (Rev. A) 英语版 (Rev.A) PDF | HTML 2021-5-19
用户指南 SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V) 2020-6-1
应用手册 Using DSPLIB FFT Implementation for Real Input and Without Data Scaling PDF | HTML 2019-6-11
应用手册 Programming PLL Controllers on OMAP-L1x8/C674x/AM18xx PDF | HTML 2019-4-25
应用手册 TMS320C6747/45/43 Power Consumption Summary 2019-4-23
应用手册 General Hardware Design/BGA PCB Design/BGA PDF | HTML 2019-2-22
应用手册 OMAP-L13x / C674x / AM1x schematic review guidelines PDF | HTML 2019-2-14
应用手册 McASP Design Guide - Tips, Tricks, and Practical Examples 2019-1-10
白皮书 Designing professional audio mixers for every scenario 2018-6-28
白皮书 Voice as the user interface – a new era in speech processing white Paper 2017-5-9
应用手册 Processor SDK RTOS Audio Benchmark Starter Kit 2017-4-12
应用手册 Plastic Ball Grid Array [PBGA] Application Note (Rev. B) 2015-8-13
用户指南 System Analyzer User's Guide (Rev. F) 2013-11-18
应用手册 Using the TMS320C6747/45/43 Bootloader (Rev. C) 2012-6-1
应用手册 Using the OMAP-L1x7 Bootloader (Rev. G) 2012-6-1
应用手册 Powering the TMS320C6745 and TMS320C6747 with the TPS650061 2011-10-25
应用手册 Introduction to TMS320C6000 DSP Optimization 2011-10-6
用户指南 TMS320C674x/OMAP-L1x Processor Peripherals Overview Reference Guide (Rev. F) 2011-9-14
白皮书 Software and Hardware Design Challenges Due to Dynamic Raw NAND Market 2011-5-19
应用手册 使用离散 DC/DC 转换器和 LDO 的电源解决方案 (Rev. B) 英语版 (Rev.B) 2010-10-8
用户指南 TMS320C674x DSP Megamodule Reference Guide (Rev. A) 2010-8-3
用户指南 TMS320C674x DSP CPU and Instruction Set User's Guide (Rev. B) 2010-7-30
应用手册 Power Solution using a Dual DCDC Converter and a LDO (Rev. A) 2010-3-25
应用手册 Power Solution using LDO's (Rev. A) 2010-3-25
应用手册 OMAP-L137 TMS320C6747/6745/6743 Pin Multiplexing Utility (Rev. A) 2009-9-26
应用手册 TMS320C6747/45/43 Complementary Products 2009-9-23
白皮书 Efficient Fixed- and Floating-Point Code Execution on the TMS320C674x Core 2009-6-24
产品概述 TMS320C674x Product Bulletin (Rev. B) 2009-4-8
应用手册 TMS320C6747/45/43 & OMAP-L1x7 USB Downstream Host Compliance Testing 2009-3-12
应用手册 TMS320C6747/45/43 & OMAP-L1x7 USB Upstream Device Compliance Testing 2009-3-12
应用手册 TMS320C674x/OMAP-L1x USB Compliance Checklist 2009-3-12
应用手册 TMS320C6747 Technical Brief (Rev. B) 2009-2-18
用户指南 TMS320C674x DSP Cache User's Guide (Rev. A) 2009-2-11

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对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器，所有 XDS 调试探针均支持核心和系统跟踪。  对于引脚上的跟踪，则需要使用 XDS560v2 PRO TRACE。

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TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 系统跟踪 USB 和以太网

XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针（仿真器）的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款，同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件，通过捕获相关器件级信息，获得准确的总线性能活动和吞吐量，并对内核和外设进行电源管理。此外，对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器，所有 XDS (...)

支持的产品和硬件
有库存
限制：
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无货
调试探针

LB-3P-TRACE32-DSP — 适用于数字信号处理器 (DSP) 的 Lauterbach TRACE32 调试和跟踪系统

Lauterbach‘s TRACE32® tools are a suite of leading-edge hardware and software components that enables developers to analyze, optimize and certify all kinds of single- or multi-core Digital Signal processors (DSPs) which are a popular choice for audio and video processing as well as radar data (...)

来源：Lauterbach GmbH
支持的产品和硬件
软件开发套件 (SDK)

PROCESSOR-SDK-C6747 — 适用于 C6747 处理器且支持 TI-RTOS 的处理器 SDK

Processor SDK（软件开发套件）是统一的软件平台，适用于 TI 嵌入式处理器，设置简单，提供开箱即用的快速基准测试和演示。  Processor SDK 的所有版本在 TI 的广泛产品系列中保持一致，让开发人员可以无缝地在多种器件之间重用和迁移软件。  借助 Processor SDK 和 TI 的嵌入式处理器解决方案，开发可扩展平台解决方案从未如此简单。

适用于 C6747、C6745 和 C6743 的处理器 SDK 包括针对 TI-RTOS 操作系统的各种支持。

RTOS 亮点：

  • TI RTOS 内核，适用于 TI 器件的轻量级实时嵌入式操作系统
  • (...)
支持的产品和硬件
IDE、配置、编译器或调试器

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

CCStudio™ IDE is part of TI's extensive CCStudio™ development ecosystem and is an integrated development environment for TI's microcontrollers, processors, wireless connectivity devices, and radar sensors. CCStudio IDE is available as desktop or cloud-based applications. The cloud version (...)

支持的产品和硬件
驱动程序或库

AEC-AER — 用于 TI C64x+、C674x、C55x 和 Cortex(tm)A8 处理器的回声抵消/消除 - 即刻可得

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

支持的产品和硬件
驱动程序或库

C64X-DSPLIB — Download TMS320C64x DSP Library

TMS320C6000 数字信号处理器库 (DSPLIB) 是一款平台优化型 DSP 函数库，适用于 C 编程器。它包括 C 语言可调用的通用信号处理例程，通常用于计算密集型的实时应用中。使用这些例程可实现比等效标准 ANSI C 语言代码更高的性能。通过使用源代码提供即用型 DSP 函数，DSPLIB 可以显著缩短应用开发时间。

请参阅基准测试：DSP 内核基准测试

支持的产品和硬件
驱动程序或库

C67X-DSPLIB — Download TMS320C67x DSP Library

TMS320C6000 数字信号处理器库 (DSPLIB) 是一款平台优化型 DSP 函数库，适用于 C 编程器。它包括 C 语言可调用的通用信号处理例程，通常用于计算密集型的实时应用中。使用这些例程可实现比等效标准 ANSI C 语言代码更高的性能。通过使用源代码提供即用型 DSP 函数，DSPLIB 可以显著缩短应用开发时间。

请参阅基准测试：DSP 内核基准测试

支持的产品和硬件
驱动程序或库

C67X-MATHLIB — 用于 C67x 浮点器件的 DSP 数学库

德州仪器 (TI) 数学库是优化的浮点数学函数库，用于使用 TI 浮点器件的 C 编程器。这些例程通常用于计算密集型实时应用，最佳执行速度是这些应用的关键。通过使用这些例程（而不是在现有运行时支持中找到的例程），您可以在无需重写现有代码的情况下获得更快的执行速度。MATHLIB 库包括目前在现有实时支持库中提供的所有浮点数学例程。这些新函数可称为当前实时支持库名称或包含在数学库中的新名称。
支持的产品和硬件
驱动程序或库

FAXLIB — 用于 C66x、C64x+ 和 C55x 处理器的传真库 (FAXLIB)

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

支持的产品和硬件
驱动程序或库

SPRC264 — TMS320C5000/6000 图像库 (IMGLIB)

C5000/6000 图像处理库 (IMGLIB) 是一款经过优化的图像/视频处理函数库，适用于 C 语言程序员。其中包括计算量庞大的实时应用程序常用的可使用 C 语言调用的通用影像/视频处理例程。使用这些例程可实现比等效标准 ANSI C 语言代码更高的性能。通过使用源代码提供即用型 DSP 函数，IMGLIB 可以显著缩短应用开发时间。

请参阅基准测试：DSP 内核基准测试

支持的产品和硬件
驱动程序或库

VOLIB — 用于 C66x、C64x+ 和 C55x 处理器的音频库 (VoLIB)

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

支持的产品和硬件
软件编解码器

ADT-3P-DSPVOIPCODECS — 自适应数字技术 DSP VOIP、语音和音频编解码器

Adaptive Digital 是音质增强算法的开发公司，提供可与 TI DSP 配合使用的一流声学回声消除软件。Adaptive Digital 在算法开发、实施、优化和配置调优方面具有丰富的经验。他们提供适用于语音技术、音质软件、回声消除、会议软件、语音压缩算法的解决方案和即用型解决方案。

如需了解有关 Adaptive Digital 的更多信息，请访问 https://www.adaptivedigital.com。
来源：Adaptive Digital Technologies, Inc.
支持的产品和硬件
软件编解码器

AURO-3P-3DENGINE — Auro Technologies, Auro-3D Engine with Auro-Codec Decoder and Auro-Matic up-mixing

Auro Technologies’ Auro-Engine includes their Auro-Codec and Auro-Matic elements for real time audio stream encoding and up mixing affording 3D audio user experiences. The Auro-Codec and Auro-Matic algorithms have been ported to select TI C6x DSPs.
来源：Auro Technologies N.V.
支持的产品和硬件
仿真模型

C6747 ZKB BSDL Model (Rev. B)

SPRM329 (6 KB) - BSDL 模型
支持的产品和硬件
仿真模型

C6747 ZKB IBIS Model (Rev. A)

SPRM332A.ZIP (176 KB) - IBIS 模型
支持的产品和硬件
参考设计

PR2048 — 使用 TPS650061 为 TMS320C6745 和 TMS320C6747 供电

适用于 TI - C6745/6747 处理器的低成本集成电源解决方案
支持的产品和硬件
参考设计

TIDEP-0099 — 适用于语音应用的音频预处理系统参考设计

此参考设计采用多个麦克风、一个波束形成算法和其他处理器，可在噪声和其他杂波中提取清晰的语音和音频。  对于语音激活数字助理，在易产生噪音的环境中使用的应用数量快速增长，由此产生了对可以从嘈杂环境中提取清晰语音的系统的需求。  TIDEP-0099 参考设计采用麦克风阵列和精密的信号处理技术，可从嘈杂的环境中提取出清晰的音频。
支持的产品和硬件
封装 引脚 CAD 符号、封装和 3D 模型
PBGA (ZKB) 256 Ultra Librarian
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