产品详细信息

DSP 3 C64x+ DSP MHz (Max) 850, 1000, 1200 CPU 32-/64-bit Operating system DSP/BIOS Ethernet MAC 10/100/1000 Rating Catalog Operating temperature range (C) -40 to 100, -40 to 95, 0 to 85
DSP 3 C64x+ DSP MHz (Max) 850, 1000, 1200 CPU 32-/64-bit Operating system DSP/BIOS Ethernet MAC 10/100/1000 Rating Catalog Operating temperature range (C) -40 to 100, -40 to 95, 0 to 85
  • Key Features
    • High-Performance Multicore DSP (C6474)
    • Instruction Cycle Time: 0.83 ns (1.2-GHz Device); 1 ns (1-GHz Device); 1.18 ns (850-MHz Device)
    • Clock Rate: 1 GHz to 1.2 GHz (1.2-GHz Device); 1 GHz (1-GHz Device); 850 MHz (850-MHz Device)
    • Commercial Temperature and Extended Tmperature
    • 3 TMS320C64x+™ DSP Cores; Six RSAs for CDMA Processing (2 per core)
    • Enhanced VCP2/TCP2
    • Frame Synchronization Interface
    • 16-/32-Bit DDR2-667 Memory Controller
    • EDMA3 Controller
    • Antenna Interface
    • Two 1x Serial RapidIO® Links, v1.2 Compliant
    • One 1.8-V Inter-Integrated Circuit (I2C) Bus
    • Two 1.8-V McBSPs
    • 1000 Mbps Ethernet MAC (EMAC)
    • Six 64-Bit General-Purpose Timers
    • 16 General-Purpose I/O (GPIO) Pins
    • Internal Semaphore Module non-UMTS Systems
    • System PLL and PLL Controller/DDR PLL and PLL Controller, Dedicated to DDR2 Memory Controller
  • High-Performance Multicore DSP (C6474)
    • Instruction Cycle Time:
      • 1.2-GHz Device: 1.0-ns to 0.83-ns
      • 1-GHz Device: 1-ns
      • 850-MHz Device: 1.18 ns
    • Clock Rate:
      • 1.2-GHz Device: 1-GHz to 1.2-GHz
      • 1-GHz Device: 1-GHz
      • 850-MHz Device: 850 MHz
    • Eight 32-Bit Instructions/Cycle
    • Commercial Temperature:
      • 1.2-GHz Device: 0°C to 95°C
      • 1-GHz Device: 0°C to 100°C
      • 850-MHZ and 1-GHz Device: 0°C to 100°C
    • Extended Temperature:
      • 1.2-GHz Device: -40°C to 95°C(1)
      • 1-GHz Device: -40°C to 100°C
  • 3 TMS320C64x+™ DSP Cores
    • Dedicated SPLOOP Instructions
    • Compact Instructions (16-Bit)
    • Exception Handling
  • TMS320C64x+ Megamodule L1/L2 Memory Architecture
    • 256 K-Bit (32 K-Byte) L1P Program Cache [Direct Mapped]
    • 256 K-Bit (32 K-Byte) L1D Data Cache [2-Way Set-Associative]
    • 512 K-Bit (64 K-Byte) L3 ROM
  • Enhanced VCP2
    • Supports Over 694 7.95-Kbps AMR
  • Enhanced Turbo Decoder Coprocessor (TCP2)
    • Supports up to Eight 2-Mbps 3 GPP (6 Iterations)
  • Endianness: Little Endian, Big Endian
  • Frame Synchronization Interface
    • Time Alignment Between Internal Subsystems, External Devices/System
    • OBSAI RP1 Compliant for Frame Burst Data
    • Alternate Interfaces for non-RP1 and non-UMTS Systems
  • 16-/32-Bit DDR2-667 Memory Controller
  • EDMA3 Controller (64 Independent Channels)
  • Antenna Interface
    • 6 Configurable Links (Full Duplex)
    • Supports OBSAI RP3 Protocol, v1.0: 768-Mbps, 1.536-, 3.072-Gbps Link Rates
    • Supports CPRI Protocol V2.0:614.4-Mbps, 1.2288-, 2.4576-Gbps Link Rates
    • Clock Input Independent or Shared with CPU (Selectable at Boot-Time)
  • Two 1x Serial RapidIO® Links, v1.2 Compliant
    • 1.25-, 2.5-, 3.125-Gbps Link Rates
    • Message Passing and DirectIO Support
    • Error Management Extensions and Congestion Control
  • One 1.8-V Inter-Integrated Circuit (I2C) Bus
  • Two 1.8-V McBSPs
  • 1000 Mbps Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Supports SGMII, v1.8 Compliant
    • 8 Independent Transmit (TX) and 8 Independent Receive (RX) Channels
  • Six 64-Bit General-Purpose Timers
    • Configurable up to Twelve 32-Bit Timers
    • Configurable in a Watchdog Timer mode
  • 16 General-Purpose I/O (GPIO) Pins
  • Internal Semaphore Module
    • Software Method to Control Access to Shared Resources
    • 32 General Purpose Semaphore Resources
  • System PLL and PLL Controller
  • DDR PLL and PLL Controller, Dedicated to DDR2 Memory Controller
  • IEEE-1149.1 and IEEE-1149.6 (JTAG™) Boundary-Scan-Compatible
  • 561-Pin Ball Grid Array (BGA) Packages (CUN, GUN, or ZUN Suffix), 0.8-mm Ball Pitch
  • 0.065-µm/7-Level Cu Metal Process (CMOS)
  • SmartReflex™ Class 0 Enabled - 0.9-V to 1.2-V Adaptive Core Voltage
  • 1.8-V, 1.1-V I/Os

(1)Note: Advance Information is presented in this document for the C6474 1.2-GHz extended temperature device.

All trademarks are the property of their respective owners.

  • Key Features
    • High-Performance Multicore DSP (C6474)
    • Instruction Cycle Time: 0.83 ns (1.2-GHz Device); 1 ns (1-GHz Device); 1.18 ns (850-MHz Device)
    • Clock Rate: 1 GHz to 1.2 GHz (1.2-GHz Device); 1 GHz (1-GHz Device); 850 MHz (850-MHz Device)
    • Commercial Temperature and Extended Tmperature
    • 3 TMS320C64x+™ DSP Cores; Six RSAs for CDMA Processing (2 per core)
    • Enhanced VCP2/TCP2
    • Frame Synchronization Interface
    • 16-/32-Bit DDR2-667 Memory Controller
    • EDMA3 Controller
    • Antenna Interface
    • Two 1x Serial RapidIO® Links, v1.2 Compliant
    • One 1.8-V Inter-Integrated Circuit (I2C) Bus
    • Two 1.8-V McBSPs
    • 1000 Mbps Ethernet MAC (EMAC)
    • Six 64-Bit General-Purpose Timers
    • 16 General-Purpose I/O (GPIO) Pins
    • Internal Semaphore Module non-UMTS Systems
    • System PLL and PLL Controller/DDR PLL and PLL Controller, Dedicated to DDR2 Memory Controller
  • High-Performance Multicore DSP (C6474)
    • Instruction Cycle Time:
      • 1.2-GHz Device: 1.0-ns to 0.83-ns
      • 1-GHz Device: 1-ns
      • 850-MHz Device: 1.18 ns
    • Clock Rate:
      • 1.2-GHz Device: 1-GHz to 1.2-GHz
      • 1-GHz Device: 1-GHz
      • 850-MHz Device: 850 MHz
    • Eight 32-Bit Instructions/Cycle
    • Commercial Temperature:
      • 1.2-GHz Device: 0°C to 95°C
      • 1-GHz Device: 0°C to 100°C
      • 850-MHZ and 1-GHz Device: 0°C to 100°C
    • Extended Temperature:
      • 1.2-GHz Device: -40°C to 95°C(1)
      • 1-GHz Device: -40°C to 100°C
  • 3 TMS320C64x+™ DSP Cores
    • Dedicated SPLOOP Instructions
    • Compact Instructions (16-Bit)
    • Exception Handling
  • TMS320C64x+ Megamodule L1/L2 Memory Architecture
    • 256 K-Bit (32 K-Byte) L1P Program Cache [Direct Mapped]
    • 256 K-Bit (32 K-Byte) L1D Data Cache [2-Way Set-Associative]
    • 512 K-Bit (64 K-Byte) L3 ROM
  • Enhanced VCP2
    • Supports Over 694 7.95-Kbps AMR
  • Enhanced Turbo Decoder Coprocessor (TCP2)
    • Supports up to Eight 2-Mbps 3 GPP (6 Iterations)
  • Endianness: Little Endian, Big Endian
  • Frame Synchronization Interface
    • Time Alignment Between Internal Subsystems, External Devices/System
    • OBSAI RP1 Compliant for Frame Burst Data
    • Alternate Interfaces for non-RP1 and non-UMTS Systems
  • 16-/32-Bit DDR2-667 Memory Controller
  • EDMA3 Controller (64 Independent Channels)
  • Antenna Interface
    • 6 Configurable Links (Full Duplex)
    • Supports OBSAI RP3 Protocol, v1.0: 768-Mbps, 1.536-, 3.072-Gbps Link Rates
    • Supports CPRI Protocol V2.0:614.4-Mbps, 1.2288-, 2.4576-Gbps Link Rates
    • Clock Input Independent or Shared with CPU (Selectable at Boot-Time)
  • Two 1x Serial RapidIO® Links, v1.2 Compliant
    • 1.25-, 2.5-, 3.125-Gbps Link Rates
    • Message Passing and DirectIO Support
    • Error Management Extensions and Congestion Control
  • One 1.8-V Inter-Integrated Circuit (I2C) Bus
  • Two 1.8-V McBSPs
  • 1000 Mbps Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Supports SGMII, v1.8 Compliant
    • 8 Independent Transmit (TX) and 8 Independent Receive (RX) Channels
  • Six 64-Bit General-Purpose Timers
    • Configurable up to Twelve 32-Bit Timers
    • Configurable in a Watchdog Timer mode
  • 16 General-Purpose I/O (GPIO) Pins
  • Internal Semaphore Module
    • Software Method to Control Access to Shared Resources
    • 32 General Purpose Semaphore Resources
  • System PLL and PLL Controller
  • DDR PLL and PLL Controller, Dedicated to DDR2 Memory Controller
  • IEEE-1149.1 and IEEE-1149.6 (JTAG™) Boundary-Scan-Compatible
  • 561-Pin Ball Grid Array (BGA) Packages (CUN, GUN, or ZUN Suffix), 0.8-mm Ball Pitch
  • 0.065-µm/7-Level Cu Metal Process (CMOS)
  • SmartReflex™ Class 0 Enabled - 0.9-V to 1.2-V Adaptive Core Voltage
  • 1.8-V, 1.1-V I/Os

(1)Note: Advance Information is presented in this document for the C6474 1.2-GHz extended temperature device.

All trademarks are the property of their respective owners.

The TMS320C64x+ DSPs (including the TMS320C6474 device) are the highest-performance multicore DSP generation in the TMS320C6000™ DSP platform.

The C6474 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI).

The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform.

The TMS320C64x+ DSPs (including the TMS320C6474 device) are the highest-performance multicore DSP generation in the TMS320C6000™ DSP platform.

The C6474 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI).

The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform.

下载

No design support from TI available

This product does not have ongoing design support from TI for new projects, such as new content or software updates. If available, you will find relevant collateral, software and tools in the product folder. You can also search for archived information in the TI E2ETM support forums.

技术文档

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类型 项目标题 下载最新的英语版本 日期
* 数据表 TMS320C6474 Multicore Digital Signal Processor Data Manual 数据表 (Rev. H) 11 Apr 2011
* 勘误表 TMS320C6474 DSP Silicon Errata (Silicon Revisions 2.1, 1.3, 1.2) (Rev. C) 11 Mar 2011
应用手册 如何将 CCS 3.x 工程迁移至最新的 Code Composer Studio™ (CCS) (Rev. A) 下载英文版本 (Rev.A) PDF | HTML 19 May 2021
用户指南 SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V) 01 Jun 2020
技术文章 Difficult to see. Always in motion is the future 04 Jan 2016
技术文章 Announcing the new entry-level Sitara processor 09 Dec 2015
技术文章 Automotive Surround View Technology trends 31 Aug 2015
技术文章 Solar Inverter Gateways Made Simple with AM335x 28 Jul 2015
应用手册 Error Detection and Correction Mechanism of TMS320C64x+/C674x (Rev. A) 19 Jul 2013
更多文献资料 Picture it: DSPs in medical imaging (Rev. C) 12 Jul 2013
应用手册 Multicore Programming Guide (Rev. B) 29 Aug 2012
用户指南 TMS320C6474 DSP EMAC/MDIO Module Reference Guide (Rev. B) 02 Mar 2012
应用手册 Power Consumption Guide for the C66x 06 Oct 2011
用户指南 TMS320C6474 DSP Enhanced DMA (EDMA3) Controller User's Guide (Rev. B) 01 Jul 2011
用户指南 Bootloader User's Guide for the TMS320C645x/C647x (Rev. G) 03 Jun 2011
用户指南 TMS320C6474 DSP DDR2 Memory Controller User's Guide (Rev. D) 02 Jun 2011
应用手册 Tuning VCP2 and TCP2 Bit Error Rate Performance Application Note 11 Feb 2011
用户指南 TMS320C6474 Serial RapidIO (SRIO) User's Guide (Rev. D) 03 Feb 2011
应用手册 TMS320C6474 Hardware Design Guide (Rev. B) 03 Aug 2010
用户指南 TMS320C64x+ DSP Megamodule Reference Guide (Rev. K) 03 Aug 2010
用户指南 TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (Rev. J) 30 Jul 2010
用户指南 TMS320C6474 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (Rev. A) 18 May 2010
用户指南 TMS320C6474 DSP Viterbi-Decoder Coprocessor 2 Reference Guide (Rev. B) 08 Dec 2009
用户指南 TMS320C6474 DSP Inter-Integrated Circuit (I2C) Module User's Guide (Rev. A) 28 Oct 2009
应用手册 Connecting Antenna Interface (AIF) With TDM Bridge Chip (IDT 80HFC001) 28 Aug 2009
应用手册 Direct I/O Library 28 Aug 2009
应用手册 Using the TMS320C6474 Antenna Interface (AIF) for Inter-DSP Communication 28 Aug 2009
应用手册 TMS320C6474 DDR2 Implementation Guidelines (Rev. A) 04 Aug 2009
应用手册 How to Approach Inter-Core Communication on TMS320C6474 27 Jan 2009
应用手册 Inter-Core Communication on TMS320C6474 DSPs 12 Jan 2009
应用手册 Core Power for C6474 using a DCDC controller with external FETs 17 Dec 2008
白皮书 See the difference:DSPs in medical imaging 31 Oct 2008
用户指南 Catalog Faraday Antenna Interface User's Guide 14 Oct 2008
用户指南 Catalog Faraday DSP 64-Bit Timer User's Guide 14 Oct 2008
用户指南 Catalog Faraday DSP General-Purpose Input/Output (GPIO) User's Guide 14 Oct 2008
用户指南 Catalog Faraday DSP Software-Programmable Phase-Locked Loop (PLL) Controller UG 14 Oct 2008
用户指南 Catalog Faraday DSP Turbo-Decoder Coprocessor 2 (TCP2) Reference Guide 14 Oct 2008
用户指南 Catalog Faraday Frame Synchronization User's Guide 14 Oct 2008
应用手册 Catalog Faraday Module Throughput Application Report 14 Oct 2008
用户指南 Catalog Faraday PSC User's Guide 14 Oct 2008
应用手册 Catalog Faraday Power Consumption Summary 14 Oct 2008
应用手册 Catalog Faraday SERDES Implementation Guidelines 14 Oct 2008
用户指南 Catalog Faraday Semaphore User's Guide 14 Oct 2008
用户指南 Primus DSP PBIST/DFT Subsystem Reference Guide 14 Oct 2008
应用手册 TMS320C6455 to TMS320TCI6487 Migration Guide 14 Oct 2008
应用手册 TMS320C6474 Common Bus Architecture (CBA) Throughput 14 Oct 2008
应用手册 TMS320C6474 Multicore Digital Signal Processor Technical Brief 14 Oct 2008
应用手册 TMS320C6474 DSP Reference Design 01 Oct 2008
应用手册 TMS320C6474 Reference Design 30 Sep 2008
应用手册 EDMA v2.0 to EDMA v3.0 (EDMA3) Migration Guide (Rev. A) 21 Aug 2008
应用手册 TMS320C64x to TMS320C64x+ CPU Migration Guide (Rev. A) 20 Oct 2005
用户指南 High-Speed DSP Systems Design Reference Guide 20 May 2005

设计和开发

如需其他信息或资源,请查看下方列表,点击标题即可进入详情页面。

评估板

EINFO-3P-SOM-EVM — eInfochips 模块上系统和 EVM

eInfochips is a product engineering and design services company with over 20 years of experience, 500+ product developments, and over 40M deployments in 140 countries, across the world. The company has delivered turnkey technology solutions for many Fortune 500 companies, across multiple verticals. (...)

发件人: eInfochips
调试探针

TMDSEMU200-U — Spectrum Digital XDS200 USB 仿真器

Spectrum Digital XDS200 是最新 XDS200 系列 TI 处理器调试探针(仿真器)的首个模型。XDS200 系列拥有超低成本 XDS100 与高性能 XDS560v2 之间的低成本与高性能的完美平衡。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS 调试探针均支持内核和系统跟踪。

Spectrum Digital XDS200 通过 TI 20 引脚连接器(带有适合 TI 14 引脚、TI 10 引脚和 ARM 20 引脚的多个适配器)连接到目标板,而通过 USB2.0 高速连接 (480Mbps) 连接到主机 PC。要在主机 (...)

TI.com 無法提供
调试探针

TMDSEMU560V2STM-U — Blackhawk XDS560v2 系统跟踪 USB 仿真器

XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针(仿真器)的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件,通过捕获相关器件级信息,获得准确的总线性能活动和吞吐量,并对内核和外设进行电源管理。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS (...)

TI.com 無法提供
调试探针

TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 系统跟踪 USB 和以太网

XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针(仿真器)的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件,通过捕获相关器件级信息,获得准确的总线性能活动和吞吐量,并对内核和外设进行电源管理。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS (...)

TI.com 無法提供
软件开发套件 (SDK)

C6474SWPKG — TMS320C6474 软件

用于 64x/64x+ 的 AET 目标库 - 高级事件触发允许对目标代码的 AET 进行编程。

芯片支持库存 (CSL) - 提供用于配置和控制 DSP 片上外设的应用编程接口 (API),以实现简便易用和硬件抽象。

DSP/BIOS: - 一种为 DSP 器件提供抢先式多任务服务的实时操作系统。DSP/BIOS 服务包括 ISR 调度、任务、软件中断、信标、消息、器件 I/O、内存管理和电源管理。此外,DSP/BIOS 还包括调试仪表和工具,其中包括低成本印刷和统计信息收集。

DSP/BIOS 消息队列传输 - 可变长度消息能够通过 SRIO 在同一内核的 DSP/BIOS (...)

软件开发套件 (SDK)

LINUXMCSDK 用于 C66x、C647x 和 C645x 的 Linux MCSDK

NOTE: K2x, C665x and C667x devices are now actively maintained on the Processor-SDK release stream. See links above.

Our Multicore Software Development Kits (MCSDK) provide highly-optimized bundles of foundational, platform-specific drivers to enable development on selected TI ARM and DSP devices. (...)

支持的产品和硬件

支持的产品和硬件

产品
数字信号处理器 (DSP)
TMS320C6455 C64x+ 定点 DSP - 高达 1.2GHz、64 位 EMIFA、32/16 位 DDR2、1Gbps 以太网 TMS320C6457 通信基础设施数字信号处理器 TMS320C6472 定点数字信号处理器 TMS320C6474 多核数字信号处理器 TMS320C6670 用于通信和电信的 4 核定点和浮点 DSP TMS320C6678 高性能八核 C66x 定点和浮点 DSP- 高达 1.25GHz
硬件开发
TMDSDSK6455 TMS320C6455 DSP 入门套件 (DSK)
下载选项
软件开发套件 (SDK)

MEDIMGSTK-C66X 用于医疗成像的 TI 嵌入式处理器软件工具套件 (STK-MED) - 用于基于 C66x 和 C64x+ 的处理器

The TI Embedded Processor Software Toolkit for Medical Imaging (STK-MED) is a collection of several standard ultrasound and optical coherence tomography (OCT) algorithms for TI’s C66x™ and C64x+™ architecture. The algorithms showcase how medical imaging functions can leverage the C66x and (...)
支持的产品和硬件

支持的产品和硬件

产品
数字信号处理器 (DSP)
DM505 适用于视觉分析的 SoC,采用 15mm 封装 SM320C6678-HIREL 高可靠性产品高性能 8 核 C6678 定点和浮点 DSP TMS320C6454 C64x+ 定点 DSP - 高达 1GHz、64 位 EMIFA、32/16 位 DDR2、1Gbps 以太网 TMS320C6455 C64x+ 定点 DSP - 高达 1.2GHz、64 位 EMIFA、32/16 位 DDR2、1Gbps 以太网 TMS320C6457 通信基础设施数字信号处理器 TMS320C6472 定点数字信号处理器 TMS320C6474 多核数字信号处理器
下载选项
驱动程序或库

SPRC122 — C62x/C64x 快速运行时支持 (RTS) 库

C62x/64x FastRTS Library 是优化型浮点函数库,适用于使用 TMS320C62x 或 TMS320C64x 器件的 C 语言编程器。这些例程通常用于计算密集型实时应用,在这些应用中,提高执行速度至关重要。通过将当前的浮点库 (RTS) 函数替换为 FastRTS Library,可以在不重写现有代码的情况下大大加快执行速度。

该版本还包括 FastRTS Library 中可用函数子集的 C 语言实施。C 代码可让用户内联这些函数并获得更高性能。

特性

单精度和双精度数学函数 单精度和双精度转换函数
浮点加法 将浮点值转换为 32 位带符号整数值
将 32 位带符号整数值转换为浮点值
(...)
用户指南: PDF
驱动程序或库

SPRC264 — TMS320C6000 图像库 (IMGLIB)

C5000/6000 Image Processing Library (IMGLIB) is an optimized image/video processing function library for C programmers. It includes C-callable general-purpose image/video processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
用户指南: PDF
驱动程序或库

SPRC265 — TMS320C6000 DSP 库 (DSPLIB)

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
用户指南: PDF
驱动程序或库

SPRC542 — C64x+ IQMath 库 - 虚拟浮点引擎

Texas Instruments TMS320C64x+ IQmath Library is collection of highly optimized and high precision mathematical Function Library for C/C++ programmers to seamlessly port the floating-point algorithm into fixed point code on TMS320C64x+ devices. These routines are typically used in computationally (...)
用户指南: PDF
驱动程序或库

SPRC975 — C6474 芯片支持库 (CSL)

此版本的 TMS320C6474 CSL v3 包含适用于 C6474 模块的外设编程(功能和寄存器级)API。此版本支持的模块列表已在发布说明中列出,包含在下载安装程序中。该 API 集提供了可供更高软件层使用的外设抽象。
驱动程序或库

TELECOMLIB — 用于 TMS320C64x+ 和 TMS320C55x 处理器的电信和媒体库 - FAXLIB、VoLIB 和 AEC/AER

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)
IDE、配置、编译器或调试器

CCSTUDIO Code Composer Studio 集成式开发环境 (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It comprises a suite of tools used to develop and debug embedded applications.  Code Composer Studio is available for download across Windows®, Linux® and macOS® (...)

支持的产品和硬件

支持的产品和硬件

此设计资源支持这些类别中的大部分产品。

查看产品详情页,确认是否能提供支持

产品
汽车毫米波雷达传感器
AWR1243 76GHz 至 81GHz 高性能汽车类 MMIC AWR1443 集成 MCU 和硬件加速器的单芯片 76GHz 至 81GHz 汽车雷达传感器 AWR1642 集成 DSP 和 MCU 的单芯片 76GHz 至 81GHz 汽车雷达传感器 AWR1843 集成 DSP、MCU 和雷达加速器的单芯片 76GHz 至 81GHz 汽车雷达传感器 AWR1843AOP Single-chip 76-GHz to 81-GHz automotive radar sensor integrating antenna on package, DSP and MCU AWR2243 76GHz 至 81GHz 汽车类第二代高性能 MMIC AWR2944 适用于角雷达和远距离雷达的汽车类第二代 76GHz 至 81GHz 高性能 SoC AWR6443 Single-chip 60-GHz to 64-GHz automotive radar sensor integrating MCU and radar accelerator AWR6843 集成 DSP、MCU 和雷达加速器的单芯片 60GHz 至 64GHz 汽车雷达传感器 AWR6843AOP 集成封装天线、DSP 和 MCU 的单芯片 60GHz 至 64GHz 汽车雷达传感器
工业毫米波雷达传感器
IWR1443 集成 MCU 和硬件加速器的 76GHz 至 81GHz 单芯片毫米波传感器 IWR1642 集成 DSP 和 MCU 的 76GHz 至 81GHz 单芯片毫米波传感器 IWR1843 集成 DSP、MCU 和雷达加速器的 76GHz 至 81GHz 单芯片工业雷达传感器 IWR6443 集成 MCU 和硬件加速器的 60GHz 至 64GHz 单芯片毫米波传感器 IWR6843 集成有处理功能的 60GHz 至 64GHz 单芯片智能毫米波传感器 IWR6843AOP 具有集成封装天线 (AoP) 的单芯片 60GHz 至 64GHz 智能毫米波传感器
在云端开发 下载选项
软件编解码器

ADT-3P-DSPVOIPCODECS — 自适应数字技术 DSP VOIP、语音和音频编解码器

Adaptive Digital 是音质增强算法的开发公司,提供可与 TI DSP 配合使用的一流声学回声消除软件。Adaptive Digital 在算法开发、实施、优化和配置调优方面具有丰富的经验。他们提供适用于语音技术、音质软件、回声消除、会议软件、语音压缩算法的解决方案和即用型解决方案。

如需了解有关 Adaptive Digital 的更多信息,请访问 https://www.adaptivedigital.com
软件编解码器

C64XPLUSCODECS — 编解码器 - 视频和语音 - 基于 C64x+ 的器件(OMAP35x、C645x、C647x、DM646、DM644x 和 DM643x)

TI 编解码器免费提供,附带生产许可且现在可供下载。全部经过生产测试,可轻松地集成到音频、视频和语音应用中 单击“获取软件”按钮(上方),以获取经过测试的最新编解码器版本。该页面及每个安装程序中都包含有数据表和发布说明。

 

 

其它信息:

软件编解码器

COUTH-3P-DSPVOIPCODECS — CouthIT DSP VoIP、语音和音频编解码器

自 1999 年以来,CouthIT 一直帮助客户将其理念转换成强大可靠的实时软件解决方案。CouthIT 许可在 VoIP 以及语音和音频编解码器领域内使用预先构建且高度优化的专用软件模块,并为多媒体应用提供软件优化和定制服务。我们的目标客户是寻求 DSP 平台(包括 TI C5000™ DSP)上嵌入式软件模块支持的 OEM 和 ODM。

如需了解有关 CouthIT 的更多信息,请访问 http://www.couthit.com
软件编解码器

VOCAL-3P-DSPVOIPCODECS — Vocal Technologies DSP VoIP 编解码器

经过 25 年以上的组装和 C 代码开发,VOCAL 的模块化软件套件可用于各种各样的 TI DSP 产品。产品具体包括 ATA、VoIP 服务器和网关、基于 HPNA 的 IPBX、视频监控、语音和视频会议、语音和数据射频器件、RoIP 网关、政务安全器件、合法拦截软件、医疗设备、嵌入式调制解调器、T.38 传真和 FoIP。

如需了解有关 Vocal Technologies 的更多信息,请访问 https://www.vocal.com
仿真模型

C6474 ZUN BSDL Model

SPRM335.ZIP (7 KB) - BSDL Model
仿真模型

C6474 ZUN IBIS Model (Rev. A)

SPRM336A.ZIP (516 KB) - IBIS Model
设计工具

PROCESSORS-3P-SEARCH — Arm®-based MPU, Arm-based MCU and DSP third-party search tool

TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)
封装 引脚数 下载
(CUN) 561 了解详情

订购和质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 认证摘要
  • 持续可靠性监测

支持与培训

视频