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DSP type 1 C67x DSP (max) (MHz) 225, 266 CPU 32-/64-bit Operating system DSP/BIOS Rating Automotive, Catalog Operating temperature range (°C) -40 to 105
DSP type 1 C67x DSP (max) (MHz) 225, 266 CPU 32-/64-bit Operating system DSP/BIOS Rating Automotive, Catalog Operating temperature range (°C) -40 to 105
HTQFP (RFP) 144 484 mm² 22 x 22
  • C672x: 32-/64-Bit 350-MHz Floating-Point DSPs
  • Upgrades to C67x+ CPU From C67x™ DSP Generation:
    • 2X CPU Registers [64 General-Purpose]
    • New Audio-Specific Instructions
    • Compatible With the C67x CPU
  • Enhanced Memory System
    • 256K-Byte Unified Program/Data RAM
    • 384K-Byte Unified Program/Data ROM
    • Single-Cycle Data Access From CPU
    • Large Program Cache (32K Byte) Supports RAM, ROM, and External Memory
  • External Memory Interface (EMIF) Supports
    • 133-MHz SDRAM (16- or 32-Bit)
    • Asynchronous NOR Flash, SRAM (8-,16-, or 32-Bit)
    • NAND Flash (8- or 16-Bit)
  • Enhanced I/O System
    • High-Performance Crossbar Switch
    • Dedicated McASP DMA Bus
    • Deterministic I/O Performance
  • dMAX (Dual Data Movement Accelerator) Supports:
    • 16 Independent Channels
    • Concurrent Processing of Two Transfer Requests
    • 1-, 2-, and 3-Dimensional Memory-to-Memory and Memory-to-Peripheral Data Transfers
    • Circular Addressing Where the Size of a Circular Buffer (FIFO) is not Limited to 2n
    • Table-Based Multi-Tap Delay Read and Write Transfers From/To a Circular Buffer
  • Three Multichannel Audio Serial Ports
    • Transmit/Receive Clocks up to 50 MHz
    • Six Clock Zones and 16 Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
    • DIT-Capable (McASP2)
  • Universal Host-Port Interface (UHPI)
    • 32-Bit-Wide Data Bus for High Bandwidth
    • Muxed and Non-Muxed Address and Data
  • Two 10-MHz SPI Ports With 3-, 4-, and 5-Pin Options
  • Two Inter-Integrated Circuit (I2C) Ports
  • Real-Time Interrupt Counter/Watchdog
  • Oscillator- and Software-Controlled PLL
  • Applications:
    • Professional Audio
      • Mixers
      • Effects Boxes
      • Audio Synthesis
      • Instrument/Amp Modeling
      • Audio Conferencing
      • Audio Broadcast
      • Audio Encoder
    • Emerging Audio Applications
    • Biometrics
    • Medical
    • Industrial
  • Commercial or Extended Temperature
  • 144-Pin, 0.5-mm, PowerPAD™ Thin Quad Flatpack (TQFP) [RFP Suffix]
  • 256-Terminal, 1.0-mm, 16x16 Array Plastic Ball Grid Array (PBGA) [GDH and ZDH Suffixes]

C67x, PowerPAD, TMS320C6000, C6000, DSP/BIOS, XDS, TMS320 are trademarks of Texas Instruments.
Philips is a registered trademark of Koninklijki Philips Electronics N.V.
All other trademarks are the property of their respective owners.

  • C672x: 32-/64-Bit 350-MHz Floating-Point DSPs
  • Upgrades to C67x+ CPU From C67x™ DSP Generation:
    • 2X CPU Registers [64 General-Purpose]
    • New Audio-Specific Instructions
    • Compatible With the C67x CPU
  • Enhanced Memory System
    • 256K-Byte Unified Program/Data RAM
    • 384K-Byte Unified Program/Data ROM
    • Single-Cycle Data Access From CPU
    • Large Program Cache (32K Byte) Supports RAM, ROM, and External Memory
  • External Memory Interface (EMIF) Supports
    • 133-MHz SDRAM (16- or 32-Bit)
    • Asynchronous NOR Flash, SRAM (8-,16-, or 32-Bit)
    • NAND Flash (8- or 16-Bit)
  • Enhanced I/O System
    • High-Performance Crossbar Switch
    • Dedicated McASP DMA Bus
    • Deterministic I/O Performance
  • dMAX (Dual Data Movement Accelerator) Supports:
    • 16 Independent Channels
    • Concurrent Processing of Two Transfer Requests
    • 1-, 2-, and 3-Dimensional Memory-to-Memory and Memory-to-Peripheral Data Transfers
    • Circular Addressing Where the Size of a Circular Buffer (FIFO) is not Limited to 2n
    • Table-Based Multi-Tap Delay Read and Write Transfers From/To a Circular Buffer
  • Three Multichannel Audio Serial Ports
    • Transmit/Receive Clocks up to 50 MHz
    • Six Clock Zones and 16 Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
    • DIT-Capable (McASP2)
  • Universal Host-Port Interface (UHPI)
    • 32-Bit-Wide Data Bus for High Bandwidth
    • Muxed and Non-Muxed Address and Data
  • Two 10-MHz SPI Ports With 3-, 4-, and 5-Pin Options
  • Two Inter-Integrated Circuit (I2C) Ports
  • Real-Time Interrupt Counter/Watchdog
  • Oscillator- and Software-Controlled PLL
  • Applications:
    • Professional Audio
      • Mixers
      • Effects Boxes
      • Audio Synthesis
      • Instrument/Amp Modeling
      • Audio Conferencing
      • Audio Broadcast
      • Audio Encoder
    • Emerging Audio Applications
    • Biometrics
    • Medical
    • Industrial
  • Commercial or Extended Temperature
  • 144-Pin, 0.5-mm, PowerPAD™ Thin Quad Flatpack (TQFP) [RFP Suffix]
  • 256-Terminal, 1.0-mm, 16x16 Array Plastic Ball Grid Array (PBGA) [GDH and ZDH Suffixes]

C67x, PowerPAD, TMS320C6000, C6000, DSP/BIOS, XDS, TMS320 are trademarks of Texas Instruments.
Philips is a registered trademark of Koninklijki Philips Electronics N.V.
All other trademarks are the property of their respective owners.

The TMS320C672x is the next generation of Texas Instruments' C67x generation of high-performance 32-/64-bit floating-point digital signal processors. The TMS320C672x includes the TMS320C6727B, TMS320C6726B, TMS320C6722B, and TMS320C6720 devices.(1)

Enhanced C67x+ CPU. The C67x+ CPU is an enhanced version of the C67x CPU used on the C671x DSPs. It is compatible with the C67x CPU but offers significant improvements in speed, code density, and floating-point performance per clock cycle. At 350 MHz, the CPU is capable of a maximum performance of 2800 MIPS/2100 MFLOPS by executing up to eight instructions (six of which are floating-point instructions) in parallel each cycle. The CPU natively supports 32-bit fixed-point, 32-bit single-precision floating-point, and 64-bit double-precision floating-point arithmetic.

Efficient Memory System. The memory controller maps the large on-chip 256K-byte RAM and 384K-byte ROM as unified program/data memory. Development is simplified since there is no fixed division between program and data memory size as on some other devices.

The memory controller supports single-cycle data accesses from the C67x+ CPU to the RAM and ROM. Up to three parallel accesses to the internal RAM and ROM from three of the following four sources are supported:

  • Two 64-bit data accesses from the C67x+ CPU
  • One 256-bit program fetch from the core and program cache
  • One 32-bit data access from the peripheral system (either dMAX or UHPI)

The large (32K-byte) program cache translates to a high hit rate for most applications. This prevents most program/data access conflicts to the on-chip memory. It also enables effective program execution from an off-chip memory such as an SDRAM.

High-Performance Crossbar Switch. A high-performance crossbar switch acts as a central hub between the different bus masters (CPU, dMAX, UHPI) and different targets (peripherals and memory). The crossbar is partially connected; some connections are not supported (for example, UHPI-to-peripheral connections).

Multiple transfers occur in parallel through the crossbar as long as there is no conflict between bus masters for a particular target. When a conflict does occur, the arbitration is a simple and deterministic fixed-priority scheme.

The dMAX is given highest-priority since it is responsible for the most time-critical I/O transfers, followed next by the UHPI, and finally by the CPU.

dMAX Dual Data Movement Accelerator. The dMAX is a module designed to perform Data Movement Acceleration. The Data Movement Accelerator (dMAX) controller handles user-programmed data transfers between the internal data memory controller and the device peripherals on the C672x DSPs. The dMAX allows movement of data to/from any addressable memory space including internal memory, peripherals, and external memory.

The dMAX controller includes features such as the capability to perform three-dimensional data transfers for advanced data sorting, and the capability to manage a section of the memory as a circular buffer/FIFO with delay-tap based reading and writing of data. The dMAX controller is capable of concurrently processing two transfer requests (provided that they are to/from different source/destinations).

External Memory Interface (EMIF) for Flexibility and Expansion. The external memory interface on the C672x supports a single bank of SDRAM and a single bank of asynchronous memory. The EMIF data width is 16 bits wide on the C6726B, C6722B, and C6720 and 32 bits wide on the C6727B.

SDRAM support includes x16 and x32 SDRAM devices with 1, 2, or 4 banks.

The C6726B, C6722B, and C6720 support SDRAM devices up to 128M bits.

The C6727B extends SDRAM support to 256M-bit and 512M-bit devices.

Asynchronous memory support is typically used to boot from a parallel non-multiplexed NOR flash device that can be 8, 16, or 32 bits wide. Booting from larger flash devices than are natively supported by the dedicated EMIF address lines is accomplished by using general-purpose I/O pins for upper address lines.

The asynchronous memory interface can also be configured to support 8- or 16-bit-wide NAND flash. It includes a hardware ECC calculation (for single-bit errors) that can operate on blocks of data up to 512 bytes.

Universal Host-Port Interface (UHPI) for High-Speed Parallel I/O. The Universal Host-Port Interface (UHPI) is a parallel interface through which an external host CPU can access memories on the DSP.

Three modes are supported by the C672x UHPI:

  • Multiplexed Address/Data - Half-Word (16-bit-wide) Mode (similar to C6713)
  • Multiplexed Address/Data - Full Word (32-bit-wide) Mode
  • Non-Multiplexed Mode - 16-bit Address and 32-bit Data Bus

The UHPI can also be restricted to accessing a single page (64K bytes) of memory anywhere in the address space of the C672x; this page can be changed, but only by the C672x CPU. This feature allows the UHPI to be used for high-speed data transfers even in systems where security is an important requirement.

The UHPI is only available on the C6727B.

Multichannel Audio Serial Ports (McASP0, McASP1, and McASP2) - Up to 16 Stereo Channels I2S. The multichannel audio serial port (McASP) seamlessly interfaces to CODECs, DACs, ADCs, and other devices. It supports the ubiquitous IIS format as well as many variations of this format, including time division multiplex (TDM) formats with up to 32 time slots.

Each McASP includes a transmit and receive section which may operate independently or synchronously; furthermore, each section includes its own flexible clock generator and extensive error-checking logic.

As data passes through the McASP, it can be realigned so that the fixed-point representation used by the application code can be independent of the representation used by the external devices without requiring any CPU overhead to make the conversion.

The McASP is a configurable module and supports between 2 and 16 serial data pins. It also has the option of supporting a Digital Interface Transmitter (DIT) mode with a full 384 bits of channel status and user data memory.

McASP2 is not available on the C6722B and C6720.

Inter-Integrated Circuit Serial Ports (I2C0, I2C1). The C672x includes two inter-integrated circuit (I2C) serial ports. A typical application is to configure one I2C serial port as a slave to an external user-interface microcontroller. The other I2C serial port may then be used by the C672x DSP to control external peripheral devices, such as a CODEC or network controller, which are functionally peripherals of the DSP device.

The two I2C serial ports are pin-multiplexed with the SPI0 serial port.

Serial Peripheral Interface Ports (SPI0, SPI1). As in the case of the I2C serial ports, the C672x DSP also includes two serial peripheral interface (SPI) serial ports. This allows one SPI port to be configured as a slave to control the DSP while the other SPI serial port is used by the DSP to control external peripherals.

The SPI ports support a basic 3-pin mode as well as optional 4- and 5-pin modes. The optional pins include a slave chip-select pin and an enable pin which implements handshaking automatically in hardware for maximum SPI throughput.

The SPI0 port is pin-multiplexed with the two I2C serial ports (I2C0 and I2C1). The SPI1 serial port is pin-multiplexed with five of the serial data pins from McASP0 and McASP1.

Real-Time Interrupt Timer (RTI). The real-time interrupt timer module includes:

  • Two 32-bit counter/prescaler pairs
  • Two input captures (tied to McASP direct memory access [DMA] events for sample rate measurement)
  • Four compares with automatic update capability
  • Digital Watchdog (optional) for enhanced system robustness

Clock Generation (PLL and OSC). The C672x DSP includes an on-chip oscillator that supports crystals in the range of 12 MHz to 25 MHz. Alternatively, the clock can be provided externally through the CLKIN pin.

The DSP includes a flexible, software-programmable phase-locked loop (PLL) clock generator. Three different clock domains (SYSCLK1, SYSCLK2, and SYSCLK3) are generated by dividing down the PLL output. SYSCLK1 is the clock used by the CPU, memory controller, and memories. SYSCLK2 is used by the peripheral subsystem and dMAX. SYSCLK3 is used exclusively for the EMIF.

(1) Throughout the remainder of the document, TMS320C6727B (or C6727B), TMS320C6726B (or C6726B), TMS320C6722B (or C6722B), and/or TMS320C6720 (or C6720) will be referred to as TMS320C672x (or C672x).

The TMS320C672x is the next generation of Texas Instruments' C67x generation of high-performance 32-/64-bit floating-point digital signal processors. The TMS320C672x includes the TMS320C6727B, TMS320C6726B, TMS320C6722B, and TMS320C6720 devices.(1)

Enhanced C67x+ CPU. The C67x+ CPU is an enhanced version of the C67x CPU used on the C671x DSPs. It is compatible with the C67x CPU but offers significant improvements in speed, code density, and floating-point performance per clock cycle. At 350 MHz, the CPU is capable of a maximum performance of 2800 MIPS/2100 MFLOPS by executing up to eight instructions (six of which are floating-point instructions) in parallel each cycle. The CPU natively supports 32-bit fixed-point, 32-bit single-precision floating-point, and 64-bit double-precision floating-point arithmetic.

Efficient Memory System. The memory controller maps the large on-chip 256K-byte RAM and 384K-byte ROM as unified program/data memory. Development is simplified since there is no fixed division between program and data memory size as on some other devices.

The memory controller supports single-cycle data accesses from the C67x+ CPU to the RAM and ROM. Up to three parallel accesses to the internal RAM and ROM from three of the following four sources are supported:

  • Two 64-bit data accesses from the C67x+ CPU
  • One 256-bit program fetch from the core and program cache
  • One 32-bit data access from the peripheral system (either dMAX or UHPI)

The large (32K-byte) program cache translates to a high hit rate for most applications. This prevents most program/data access conflicts to the on-chip memory. It also enables effective program execution from an off-chip memory such as an SDRAM.

High-Performance Crossbar Switch. A high-performance crossbar switch acts as a central hub between the different bus masters (CPU, dMAX, UHPI) and different targets (peripherals and memory). The crossbar is partially connected; some connections are not supported (for example, UHPI-to-peripheral connections).

Multiple transfers occur in parallel through the crossbar as long as there is no conflict between bus masters for a particular target. When a conflict does occur, the arbitration is a simple and deterministic fixed-priority scheme.

The dMAX is given highest-priority since it is responsible for the most time-critical I/O transfers, followed next by the UHPI, and finally by the CPU.

dMAX Dual Data Movement Accelerator. The dMAX is a module designed to perform Data Movement Acceleration. The Data Movement Accelerator (dMAX) controller handles user-programmed data transfers between the internal data memory controller and the device peripherals on the C672x DSPs. The dMAX allows movement of data to/from any addressable memory space including internal memory, peripherals, and external memory.

The dMAX controller includes features such as the capability to perform three-dimensional data transfers for advanced data sorting, and the capability to manage a section of the memory as a circular buffer/FIFO with delay-tap based reading and writing of data. The dMAX controller is capable of concurrently processing two transfer requests (provided that they are to/from different source/destinations).

External Memory Interface (EMIF) for Flexibility and Expansion. The external memory interface on the C672x supports a single bank of SDRAM and a single bank of asynchronous memory. The EMIF data width is 16 bits wide on the C6726B, C6722B, and C6720 and 32 bits wide on the C6727B.

SDRAM support includes x16 and x32 SDRAM devices with 1, 2, or 4 banks.

The C6726B, C6722B, and C6720 support SDRAM devices up to 128M bits.

The C6727B extends SDRAM support to 256M-bit and 512M-bit devices.

Asynchronous memory support is typically used to boot from a parallel non-multiplexed NOR flash device that can be 8, 16, or 32 bits wide. Booting from larger flash devices than are natively supported by the dedicated EMIF address lines is accomplished by using general-purpose I/O pins for upper address lines.

The asynchronous memory interface can also be configured to support 8- or 16-bit-wide NAND flash. It includes a hardware ECC calculation (for single-bit errors) that can operate on blocks of data up to 512 bytes.

Universal Host-Port Interface (UHPI) for High-Speed Parallel I/O. The Universal Host-Port Interface (UHPI) is a parallel interface through which an external host CPU can access memories on the DSP.

Three modes are supported by the C672x UHPI:

  • Multiplexed Address/Data - Half-Word (16-bit-wide) Mode (similar to C6713)
  • Multiplexed Address/Data - Full Word (32-bit-wide) Mode
  • Non-Multiplexed Mode - 16-bit Address and 32-bit Data Bus

The UHPI can also be restricted to accessing a single page (64K bytes) of memory anywhere in the address space of the C672x; this page can be changed, but only by the C672x CPU. This feature allows the UHPI to be used for high-speed data transfers even in systems where security is an important requirement.

The UHPI is only available on the C6727B.

Multichannel Audio Serial Ports (McASP0, McASP1, and McASP2) - Up to 16 Stereo Channels I2S. The multichannel audio serial port (McASP) seamlessly interfaces to CODECs, DACs, ADCs, and other devices. It supports the ubiquitous IIS format as well as many variations of this format, including time division multiplex (TDM) formats with up to 32 time slots.

Each McASP includes a transmit and receive section which may operate independently or synchronously; furthermore, each section includes its own flexible clock generator and extensive error-checking logic.

As data passes through the McASP, it can be realigned so that the fixed-point representation used by the application code can be independent of the representation used by the external devices without requiring any CPU overhead to make the conversion.

The McASP is a configurable module and supports between 2 and 16 serial data pins. It also has the option of supporting a Digital Interface Transmitter (DIT) mode with a full 384 bits of channel status and user data memory.

McASP2 is not available on the C6722B and C6720.

Inter-Integrated Circuit Serial Ports (I2C0, I2C1). The C672x includes two inter-integrated circuit (I2C) serial ports. A typical application is to configure one I2C serial port as a slave to an external user-interface microcontroller. The other I2C serial port may then be used by the C672x DSP to control external peripheral devices, such as a CODEC or network controller, which are functionally peripherals of the DSP device.

The two I2C serial ports are pin-multiplexed with the SPI0 serial port.

Serial Peripheral Interface Ports (SPI0, SPI1). As in the case of the I2C serial ports, the C672x DSP also includes two serial peripheral interface (SPI) serial ports. This allows one SPI port to be configured as a slave to control the DSP while the other SPI serial port is used by the DSP to control external peripherals.

The SPI ports support a basic 3-pin mode as well as optional 4- and 5-pin modes. The optional pins include a slave chip-select pin and an enable pin which implements handshaking automatically in hardware for maximum SPI throughput.

The SPI0 port is pin-multiplexed with the two I2C serial ports (I2C0 and I2C1). The SPI1 serial port is pin-multiplexed with five of the serial data pins from McASP0 and McASP1.

Real-Time Interrupt Timer (RTI). The real-time interrupt timer module includes:

  • Two 32-bit counter/prescaler pairs
  • Two input captures (tied to McASP direct memory access [DMA] events for sample rate measurement)
  • Four compares with automatic update capability
  • Digital Watchdog (optional) for enhanced system robustness

Clock Generation (PLL and OSC). The C672x DSP includes an on-chip oscillator that supports crystals in the range of 12 MHz to 25 MHz. Alternatively, the clock can be provided externally through the CLKIN pin.

The DSP includes a flexible, software-programmable phase-locked loop (PLL) clock generator. Three different clock domains (SYSCLK1, SYSCLK2, and SYSCLK3) are generated by dividing down the PLL output. SYSCLK1 is the clock used by the CPU, memory controller, and memories. SYSCLK2 is used by the peripheral subsystem and dMAX. SYSCLK3 is used exclusively for the EMIF.

(1) Throughout the remainder of the document, TMS320C6727B (or C6727B), TMS320C6726B (or C6726B), TMS320C6722B (or C6722B), and/or TMS320C6720 (or C6720) will be referred to as TMS320C672x (or C672x).

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类型 标题 下载最新的英语版本 日期
* 数据表 TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720 Floating-Point DSPs 数据表 (Rev. E) 2008年 7月 11日
* 勘误表 TMS320C6727/B, TMS320C6726/B, TMS32C6722/B, TMS320C6720 DSPs Silicon Errata (Rev. F) 2008年 10月 23日
应用手册 如何将 CCS 3.x 工程迁移至最新的 Code Composer Studio™ (CCS) (Rev. A) 英语版 (Rev.A) PDF | HTML 2021年 5月 19日
用户指南 TMS320C6000 Assembly Language Tools v 7.4 User's Guide (Rev. W) 2012年 8月 21日
用户指南 TMS320C6000 Optimizing Compiler v 7.4 User's Guide (Rev. U) 2012年 8月 21日
应用手册 Introduction to TMS320C6000 DSP Optimization 2011年 10月 6日
用户指南 TMS320C6000 Assembly Language Tools v 7.0 User's Guide (Rev. S) 2010年 3月 18日
用户指南 TMS320C6000 Optimizing Compiler v 7.0 User's Guide (Rev. Q) 2010年 3月 18日
应用手册 Using the TMS320C672x Bootloader (Rev. D) 2009年 9月 10日
应用手册 常用对象文件格式 (COFF) 2009年 4月 15日
应用手册 Configuring External Interrupts on TMS320C672x Devices 2008年 7月 11日
用户指南 TMS320C6000 Assembly Language Tools v 6.1 User's Guide (Rev. Q) 2008年 5月 15日
用户指南 TMS320C6000 Optimizing Compiler v 6.1 User's Guide (Rev. O) 2008年 5月 15日
用户指南 TMS320C672x DSP Multichannel Audio Serial Port (McASP) Reference Guide (Rev. B) 2008年 3月 13日
应用手册 Using ROM Contents on TMS320C672x 2008年 2月 5日
用户指南 TMS320C672x DSP Inter-Integrated Circuit (I2C) Module Reference Guide (Rev. E) 2007年 12月 11日
用户指南 TMS320C672x DSP Dual Data Movement Accelerator (dMAX) Reference Guide (Rev. D) 2007年 10月 12日
用户指南 TMS320C672x DSP Serial Peripheral Interface (SPI) Reference Guide (Rev. B) 2007年 7月 12日
用户指南 TMS320C672x DSP External Memory Interface (EMIF) User's Guide (Rev. C) 2007年 4月 2日
用户指南 TMS320C67x/C67x+ DSP CPU and Instruction Set Reference Guide (Rev. A) 2006年 11月 7日
产品概述 TMS320C672x Floating-Point DSPs Product Bulletin (Rev. D) 2006年 10月 20日
应用手册 C9230C100 TMS320C672x Floating-Point Digital Signal Processor ROM (Rev. C) 2006年 9月 25日
应用手册 TMS320C672x Hardware Designer's Resource Guide (Rev. A) 2006年 9月 22日
应用手册 TMS320C672x Power Consumption Summary (Rev. B) 2006年 9月 22日
用户指南 TMS320C672x DSP Peripherals Overview Reference Guide (Rev. B) 2006年 6月 25日
应用手册 How to Create Delay-based Audio Effects on a TMS320C6727 DSP 2005年 11月 1日
应用手册 Migrating from TMS320C6713 to TMS320C672x 2005年 5月 23日
用户指南 TMS320C672x DSP Software-Programmable Phase-Locked Loop (PLL) Controller RG (Rev. A) 2005年 5月 23日
用户指南 TMS320C672x DSP Real-Time Interrupt Reference Guide 2005年 4月 13日

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基于 Arm 的处理器
66AK2G12 高性能多核 DSP+Arm - 1 个 Arm A15 内核、1 个 C66x DSP 内核
数字信号处理器 (DSP)
DM505 适用于视觉分析的 SoC,采用 15mm 封装 SM320C6424-EP C6424 定点 DSP(增强型产品) SM320C6472-HIREL 高可靠性产品 6 核 C6472 定点 DSP SM320C6678-HIREL 高可靠性产品高性能 8 核 C6678 定点和浮点 DSP SM320C6701 用于军事应用的单核 C67x 浮点 DSP - 高达 167MHz SM320C6701-EP 增强型产品 C6701 浮点 DSP SMJ320C6203 军用级 C62x 定点 DSP - 陶瓷封装 SMJ320C6701 军用级 C67x 浮点 DSP - 陶瓷封装 SMJ320C6701-SP 航天级 C6701 浮点 DSP - 抗辐射 V 类、采用陶瓷封装 SMV320C6727B-SP 航天级 C6727B 浮点 DSP - 抗辐射 V 类、采用陶瓷封装 TMS320C5517 低功耗 C55x 定点 DSP - 高达 200MHz、USB、LCD 接口、FFT HWA、SAR ADC TMS320C5532 低功耗 C55x 定点 DSP- 高达 100MHz TMS320C5533 低功耗 C55x 定点 DSP- 高达 100MHz、USB TMS320C5534 低功耗 C55x 定点 DSP- 高达 100MHz、USB、LCD 接口 TMS320C5535 低功耗 C55x 定点 DSP- 高达 100MHz、USB、LCD 接口、FFT HWA、SAR ADC TMS320C6202B C62x 定点 DSP- 高达 300MHz、384KB TMS320C6203B C62x 定点 DSP- 高达 300MHz、896KB TMS320C6211B C62x 定点 DSP- 高达 167MHz TMS320C6421Q C64x+ 定点 DSP- 高达 600MHz、8 位 EMIFA、16 位 DDR2 TMS320C6424Q C64x+ 定点 DSP- 高达 600MHz、16/8 位 EMIFA、32/16 位 DDR2 TMS320C6454 C64x+ 定点 DSP - 高达 1GHz、64 位 EMIFA、32/16 位 DDR2、1Gbps 以太网 TMS320C6457 通信基础设施数字信号处理器 TMS320C6701 C67x 浮点 DSP- 高达 167MHz、McBSP TMS320C6711D C67x 浮点 DSP- 高达 250MHz、McBSP、32 位 EMIFA TMS320C6712D C67x 浮点 DSP- 高达 150MHz、McBSP、16 位 EMIFA TMS320C6720 C67x 浮点 DSP - 200MHz、McASP、16 位 EMIFA TMS320C6722B C67x 浮点 DSP- 高达 250MHz、McASP、16 位 EMIFA TMS320C6726B C67x 浮点 DSP- 高达 266MHz、McASP、16 位 EMIFA TMS320C6727 C67x 浮点 DSP- 高达 250MHz、McASP、32 位 EMIFA TMS320C6727B C67x 浮点 DSP- 高达 350MHz、McASP、32 位 EMIFA TMS320C6743 低功耗 C674x 浮点 DSP- 375MHz TMS320C6745 低功耗 C674x 浮点 DSP- 456MHz、QFP TMS320C6747 低功耗 C674x 浮点 DSP- 456MHz、PBGA TMS320DM642Q 视频/成像定点数字信号处理器 TMS320DM6431Q 数字媒体处理器,性能高达 2400MIPS、300MHz 时钟速率 TMS320DM6435Q 数字媒体处理器,性能高达 4800MIPS、600MHz 时钟速率、1 个 McASP、1 个 McBSP TMS320DM6437Q 数字媒体处理器,性能高达 4800MIPS、600MHz 时钟速率、1 个 McASP、2 个 McBSP TMS320DM6441 达芬奇数字媒体片上系统 TMS320DM6467T 数字媒体片上系统 TMS320DM647 数字媒体处理器
下载选项
驱动程序或库

C64X-DSPLIB Download TMS320C64x DSP Library

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)

支持的产品和硬件

支持的产品和硬件

产品
基于 Arm 的处理器
OMAPL137-HT 高温低功耗 C674x 浮点 DSP + Arm 处理器 - 高达 456MHz OMAPL138B-EP 345MHz 低功耗 C674x 浮点 DSP + ARM9 处理器(增强型产品) TMS320DM8127 DaVinci 数字媒体处理器
数字信号处理器 (DSP)
SM320C6424-EP C6424 定点 DSP(增强型产品) SM320C6472-HIREL 高可靠性产品 6 核 C6472 定点 DSP SM320C6678-HIREL 高可靠性产品高性能 8 核 C6678 定点和浮点 DSP SM320C6701 用于军事应用的单核 C67x 浮点 DSP - 高达 167MHz SM320C6701-EP 增强型产品 C6701 浮点 DSP SMJ320C6203 军用级 C62x 定点 DSP - 陶瓷封装 SMJ320C6701 军用级 C67x 浮点 DSP - 陶瓷封装 SMJ320C6701-SP 航天级 C6701 浮点 DSP - 抗辐射 V 类、采用陶瓷封装 SMV320C6727B-SP 航天级 C6727B 浮点 DSP - 抗辐射 V 类、采用陶瓷封装 TMS320C6202B C62x 定点 DSP- 高达 300MHz、384KB TMS320C6203B C62x 定点 DSP- 高达 300MHz、896KB TMS320C6211B C62x 定点 DSP- 高达 167MHz TMS320C6421Q C64x+ 定点 DSP- 高达 600MHz、8 位 EMIFA、16 位 DDR2 TMS320C6424Q C64x+ 定点 DSP- 高达 600MHz、16/8 位 EMIFA、32/16 位 DDR2 TMS320C6452 C64x+ 定点 DSP- 高达 900MHz、1Gbps 以太网 TMS320C6454 C64x+ 定点 DSP - 高达 1GHz、64 位 EMIFA、32/16 位 DDR2、1Gbps 以太网 TMS320C6455 C64x+ 频率高达 1.2GHz、具有 64 位 EMIFA、32 位和 16 位 DDR2、1Gbps 以太网的定点 DSP TMS320C6457 通信基础设施数字信号处理器 TMS320C6701 C67x 浮点 DSP- 高达 167MHz、McBSP TMS320C6711D C67x 浮点 DSP- 高达 250MHz、McBSP、32 位 EMIFA TMS320C6712D C67x 浮点 DSP- 高达 150MHz、McBSP、16 位 EMIFA TMS320C6720 C67x 浮点 DSP - 200MHz、McASP、16 位 EMIFA TMS320C6722B C67x 浮点 DSP- 高达 250MHz、McASP、16 位 EMIFA TMS320C6726B C67x 浮点 DSP- 高达 266MHz、McASP、16 位 EMIFA TMS320C6727 C67x 浮点 DSP- 高达 250MHz、McASP、32 位 EMIFA TMS320C6727B C67x 浮点 DSP- 高达 350MHz、McASP、32 位 EMIFA TMS320C6743 低功耗 C674x 浮点 DSP- 375MHz TMS320C6745 低功耗 C674x 浮点 DSP- 456MHz、QFP TMS320C6747 低功耗 C674x 浮点 DSP- 456MHz、PBGA
驱动程序或库

C67X-DSPLIB Download TMS320C67x DSP Library

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)

支持的产品和硬件

支持的产品和硬件

产品
基于 Arm 的处理器
OMAPL137-HT 高温低功耗 C674x 浮点 DSP + Arm 处理器 - 高达 456MHz OMAPL138B-EP 345MHz 低功耗 C674x 浮点 DSP + ARM9 处理器(增强型产品) TMS320DM8127 DaVinci 数字媒体处理器
数字信号处理器 (DSP)
SM320C6424-EP C6424 定点 DSP(增强型产品) SM320C6472-HIREL 高可靠性产品 6 核 C6472 定点 DSP SM320C6678-HIREL 高可靠性产品高性能 8 核 C6678 定点和浮点 DSP SM320C6701 用于军事应用的单核 C67x 浮点 DSP - 高达 167MHz SM320C6701-EP 增强型产品 C6701 浮点 DSP SMJ320C6203 军用级 C62x 定点 DSP - 陶瓷封装 SMJ320C6701 军用级 C67x 浮点 DSP - 陶瓷封装 SMJ320C6701-SP 航天级 C6701 浮点 DSP - 抗辐射 V 类、采用陶瓷封装 SMV320C6727B-SP 航天级 C6727B 浮点 DSP - 抗辐射 V 类、采用陶瓷封装 TMS320C6202B C62x 定点 DSP- 高达 300MHz、384KB TMS320C6203B C62x 定点 DSP- 高达 300MHz、896KB TMS320C6211B C62x 定点 DSP- 高达 167MHz TMS320C6421Q C64x+ 定点 DSP- 高达 600MHz、8 位 EMIFA、16 位 DDR2 TMS320C6424Q C64x+ 定点 DSP- 高达 600MHz、16/8 位 EMIFA、32/16 位 DDR2 TMS320C6452 C64x+ 定点 DSP- 高达 900MHz、1Gbps 以太网 TMS320C6454 C64x+ 定点 DSP - 高达 1GHz、64 位 EMIFA、32/16 位 DDR2、1Gbps 以太网 TMS320C6455 C64x+ 频率高达 1.2GHz、具有 64 位 EMIFA、32 位和 16 位 DDR2、1Gbps 以太网的定点 DSP TMS320C6457 通信基础设施数字信号处理器 TMS320C6701 C67x 浮点 DSP- 高达 167MHz、McBSP TMS320C6711D C67x 浮点 DSP- 高达 250MHz、McBSP、32 位 EMIFA TMS320C6712D C67x 浮点 DSP- 高达 150MHz、McBSP、16 位 EMIFA TMS320C6720 C67x 浮点 DSP - 200MHz、McASP、16 位 EMIFA TMS320C6722B C67x 浮点 DSP- 高达 250MHz、McASP、16 位 EMIFA TMS320C6726B C67x 浮点 DSP- 高达 266MHz、McASP、16 位 EMIFA TMS320C6727 C67x 浮点 DSP- 高达 250MHz、McASP、32 位 EMIFA TMS320C6727B C67x 浮点 DSP- 高达 350MHz、McASP、32 位 EMIFA TMS320C6743 低功耗 C674x 浮点 DSP- 375MHz TMS320C6745 低功耗 C674x 浮点 DSP- 456MHz、QFP TMS320C6747 低功耗 C674x 浮点 DSP- 456MHz、PBGA
驱动程序或库

C67X-MATHLIB 用于 C67x 浮点器件的 DSP 数学库

The Texas Instruments math library is an optimized floating-point math function library for C programmers using TI floating point devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By using these routines instead (...)
支持的产品和硬件

支持的产品和硬件

产品
基于 Arm 的处理器
OMAPL137-HT 高温低功耗 C674x 浮点 DSP + Arm 处理器 - 高达 456MHz OMAPL138B-EP 345MHz 低功耗 C674x 浮点 DSP + ARM9 处理器(增强型产品)
数字信号处理器 (DSP)
DM505 适用于视觉分析的 SoC,采用 15mm 封装 SM320C6678-HIREL 高可靠性产品高性能 8 核 C6678 定点和浮点 DSP SMV320C6727B-SP 航天级 C6727B 浮点 DSP - 抗辐射 V 类、采用陶瓷封装 TMS320C6701 C67x 浮点 DSP- 高达 167MHz、McBSP TMS320C6711D C67x 浮点 DSP- 高达 250MHz、McBSP、32 位 EMIFA TMS320C6712D C67x 浮点 DSP- 高达 150MHz、McBSP、16 位 EMIFA TMS320C6720 C67x 浮点 DSP - 200MHz、McASP、16 位 EMIFA TMS320C6722B C67x 浮点 DSP- 高达 250MHz、McASP、16 位 EMIFA TMS320C6726B C67x 浮点 DSP- 高达 266MHz、McASP、16 位 EMIFA TMS320C6727 C67x 浮点 DSP- 高达 250MHz、McASP、32 位 EMIFA TMS320C6727B C67x 浮点 DSP- 高达 350MHz、McASP、32 位 EMIFA TMS320C6743 低功耗 C674x 浮点 DSP- 375MHz TMS320C6745 低功耗 C674x 浮点 DSP- 456MHz、QFP TMS320C6747 低功耗 C674x 浮点 DSP- 456MHz、PBGA
下载选项
驱动程序或库

FAXLIB 用于 C66x、C64x+ 和 C55x 处理器的传真库 (FAXLIB)

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

支持的产品和硬件

支持的产品和硬件

产品
基于 Arm 的处理器
66AK2G12 高性能多核 DSP+Arm - 1 个 Arm A15 内核、1 个 C66x DSP 内核
数字信号处理器 (DSP)
DM505 适用于视觉分析的 SoC,采用 15mm 封装 SM320C6424-EP C6424 定点 DSP(增强型产品) SM320C6472-HIREL 高可靠性产品 6 核 C6472 定点 DSP SM320C6678-HIREL 高可靠性产品高性能 8 核 C6678 定点和浮点 DSP SM320C6701 用于军事应用的单核 C67x 浮点 DSP - 高达 167MHz SM320C6701-EP 增强型产品 C6701 浮点 DSP SMJ320C6203 军用级 C62x 定点 DSP - 陶瓷封装 SMJ320C6701 军用级 C67x 浮点 DSP - 陶瓷封装 SMJ320C6701-SP 航天级 C6701 浮点 DSP - 抗辐射 V 类、采用陶瓷封装 SMV320C6727B-SP 航天级 C6727B 浮点 DSP - 抗辐射 V 类、采用陶瓷封装 TMS320C5517 低功耗 C55x 定点 DSP - 高达 200MHz、USB、LCD 接口、FFT HWA、SAR ADC TMS320C5532 低功耗 C55x 定点 DSP- 高达 100MHz TMS320C5533 低功耗 C55x 定点 DSP- 高达 100MHz、USB TMS320C5534 低功耗 C55x 定点 DSP- 高达 100MHz、USB、LCD 接口 TMS320C5535 低功耗 C55x 定点 DSP- 高达 100MHz、USB、LCD 接口、FFT HWA、SAR ADC TMS320C6202B C62x 定点 DSP- 高达 300MHz、384KB TMS320C6203B C62x 定点 DSP- 高达 300MHz、896KB TMS320C6211B C62x 定点 DSP- 高达 167MHz TMS320C6421Q C64x+ 定点 DSP- 高达 600MHz、8 位 EMIFA、16 位 DDR2 TMS320C6424Q C64x+ 定点 DSP- 高达 600MHz、16/8 位 EMIFA、32/16 位 DDR2 TMS320C6454 C64x+ 定点 DSP - 高达 1GHz、64 位 EMIFA、32/16 位 DDR2、1Gbps 以太网 TMS320C6457 通信基础设施数字信号处理器 TMS320C6701 C67x 浮点 DSP- 高达 167MHz、McBSP TMS320C6711D C67x 浮点 DSP- 高达 250MHz、McBSP、32 位 EMIFA TMS320C6712D C67x 浮点 DSP- 高达 150MHz、McBSP、16 位 EMIFA TMS320C6720 C67x 浮点 DSP - 200MHz、McASP、16 位 EMIFA TMS320C6722B C67x 浮点 DSP- 高达 250MHz、McASP、16 位 EMIFA TMS320C6726B C67x 浮点 DSP- 高达 266MHz、McASP、16 位 EMIFA TMS320C6727 C67x 浮点 DSP- 高达 250MHz、McASP、32 位 EMIFA TMS320C6727B C67x 浮点 DSP- 高达 350MHz、McASP、32 位 EMIFA TMS320C6743 低功耗 C674x 浮点 DSP- 375MHz TMS320C6745 低功耗 C674x 浮点 DSP- 456MHz、QFP TMS320C6747 低功耗 C674x 浮点 DSP- 456MHz、PBGA TMS320DM642Q 视频/成像定点数字信号处理器 TMS320DM6431Q 数字媒体处理器,性能高达 2400MIPS、300MHz 时钟速率 TMS320DM6435Q 数字媒体处理器,性能高达 4800MIPS、600MHz 时钟速率、1 个 McASP、1 个 McBSP TMS320DM6437Q 数字媒体处理器,性能高达 4800MIPS、600MHz 时钟速率、1 个 McASP、2 个 McBSP TMS320DM6441 达芬奇数字媒体片上系统 TMS320DM6467T 数字媒体片上系统 TMS320DM647 数字媒体处理器
下载选项
驱动程序或库

SPRC203 System PatchV2.00.00 FastRtsV1.20 DSPLIB V2.00 genBootCfgV1.0030 genAIS V1.03.06

Patch Code, FastRts(V1.20)/DSPLIB (V2.00) ROM Examples & Libraries, and Boot Configuration Utlities + Boot Examples

System Patch V2.00.00 , FastRts(1.20), DSPLIB (V2.00), genBootCfg(1.0030), genAIS(1.03.06)

支持的产品和硬件

支持的产品和硬件

产品
数字信号处理器 (DSP)
TMS320C6720 C67x 浮点 DSP - 200MHz、McASP、16 位 EMIFA TMS320C6722B C67x 浮点 DSP- 高达 250MHz、McASP、16 位 EMIFA TMS320C6726B C67x 浮点 DSP- 高达 266MHz、McASP、16 位 EMIFA TMS320C6727 C67x 浮点 DSP- 高达 250MHz、McASP、32 位 EMIFA TMS320C6727B C67x 浮点 DSP- 高达 350MHz、McASP、32 位 EMIFA
驱动程序或库

VOLIB 用于 C66x、C64x+ 和 C55x 处理器的音频库 (VoLIB)

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

支持的产品和硬件

支持的产品和硬件

产品
基于 Arm 的处理器
66AK2G12 高性能多核 DSP+Arm - 1 个 Arm A15 内核、1 个 C66x DSP 内核
数字信号处理器 (DSP)
DM505 适用于视觉分析的 SoC,采用 15mm 封装 SM320C6424-EP C6424 定点 DSP(增强型产品) SM320C6472-HIREL 高可靠性产品 6 核 C6472 定点 DSP SM320C6678-HIREL 高可靠性产品高性能 8 核 C6678 定点和浮点 DSP SM320C6701 用于军事应用的单核 C67x 浮点 DSP - 高达 167MHz SM320C6701-EP 增强型产品 C6701 浮点 DSP SMJ320C6203 军用级 C62x 定点 DSP - 陶瓷封装 SMJ320C6701 军用级 C67x 浮点 DSP - 陶瓷封装 SMJ320C6701-SP 航天级 C6701 浮点 DSP - 抗辐射 V 类、采用陶瓷封装 SMV320C6727B-SP 航天级 C6727B 浮点 DSP - 抗辐射 V 类、采用陶瓷封装 TMS320C5517 低功耗 C55x 定点 DSP - 高达 200MHz、USB、LCD 接口、FFT HWA、SAR ADC TMS320C5532 低功耗 C55x 定点 DSP- 高达 100MHz TMS320C5533 低功耗 C55x 定点 DSP- 高达 100MHz、USB TMS320C5534 低功耗 C55x 定点 DSP- 高达 100MHz、USB、LCD 接口 TMS320C5535 低功耗 C55x 定点 DSP- 高达 100MHz、USB、LCD 接口、FFT HWA、SAR ADC TMS320C6202B C62x 定点 DSP- 高达 300MHz、384KB TMS320C6203B C62x 定点 DSP- 高达 300MHz、896KB TMS320C6211B C62x 定点 DSP- 高达 167MHz TMS320C6421Q C64x+ 定点 DSP- 高达 600MHz、8 位 EMIFA、16 位 DDR2 TMS320C6424Q C64x+ 定点 DSP- 高达 600MHz、16/8 位 EMIFA、32/16 位 DDR2 TMS320C6454 C64x+ 定点 DSP - 高达 1GHz、64 位 EMIFA、32/16 位 DDR2、1Gbps 以太网 TMS320C6457 通信基础设施数字信号处理器 TMS320C6701 C67x 浮点 DSP- 高达 167MHz、McBSP TMS320C6711D C67x 浮点 DSP- 高达 250MHz、McBSP、32 位 EMIFA TMS320C6712D C67x 浮点 DSP- 高达 150MHz、McBSP、16 位 EMIFA TMS320C6720 C67x 浮点 DSP - 200MHz、McASP、16 位 EMIFA TMS320C6722B C67x 浮点 DSP- 高达 250MHz、McASP、16 位 EMIFA TMS320C6726B C67x 浮点 DSP- 高达 266MHz、McASP、16 位 EMIFA TMS320C6727 C67x 浮点 DSP- 高达 250MHz、McASP、32 位 EMIFA TMS320C6727B C67x 浮点 DSP- 高达 350MHz、McASP、32 位 EMIFA TMS320C6743 低功耗 C674x 浮点 DSP- 375MHz TMS320C6745 低功耗 C674x 浮点 DSP- 456MHz、QFP TMS320C6747 低功耗 C674x 浮点 DSP- 456MHz、PBGA TMS320DM642Q 视频/成像定点数字信号处理器 TMS320DM6431Q 数字媒体处理器,性能高达 2400MIPS、300MHz 时钟速率 TMS320DM6435Q 数字媒体处理器,性能高达 4800MIPS、600MHz 时钟速率、1 个 McASP、1 个 McBSP TMS320DM6437Q 数字媒体处理器,性能高达 4800MIPS、600MHz 时钟速率、1 个 McASP、2 个 McBSP TMS320DM6441 达芬奇数字媒体片上系统 TMS320DM6467T 数字媒体片上系统 TMS320DM647 数字媒体处理器
下载选项
IDE、配置、编译器或调试器

CCSTUDIO Code Composer Studio 集成式开发环境 (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It comprises a suite of tools used to develop and debug embedded applications.  Code Composer Studio is available for download across Windows®, Linux® and macOS® desktops. It can also (...)

支持的产品和硬件

支持的产品和硬件

此设计资源支持这些类别中的大部分产品。

查看产品详情页,验证是否能提供支持。

启动 下载选项
仿真模型

C6726 RFP BSDL Model (Rev. B)

SPRM182B.ZIP (6 KB) - BSDL Model
仿真模型

C6726 RFP IBIS Model (Rev. A)

SPRM193A.ZIP (32 KB) - IBIS Model
设计工具

PROCESSORS-3P-SEARCH — 基于 Arm® 的 MPU、基于 Arm 的 MCU 和 DSP 第三方搜索工具

TI 已与多家公司合作,提供各种使用 TI 处理器的软件、工具和 SOM,从而加快您的量产速度。下载此搜索工具,快速浏览我们的第三方解决方案,并寻找合适的第三方来满足您的需求。此处所列的软件、工具和模块由独立的第三方生产和管理,而非德州仪器 (TI)。

搜索工具按产品类型划分为以下类别:

  • 工具包括 IDE/编译器、调试和跟踪、仿真和建模软件以及闪存编程器。
  • 操作系统包括 TI 处理器支持的操作系统。
  • 应用软件是指应用特定的软件,包括在 TI 处理器上运行的中间件和库。
  • SoM 是模块上系统解决方案
封装 引脚 CAD 符号、封装和 3D 模型
HTQFP (RFP) 144 Ultra Librarian

订购和质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息:
  • 制造厂地点
  • 封装厂地点

支持和培训

视频