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TMS320C6211B

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C62x 定点 DSP- 高达 167MHz

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TMS320C6211B

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产品详情

CPU 32-/64-bit Frequency (MHz) 167 Rating Catalog Operating temperature range (°C) -40 to 105
CPU 32-/64-bit Frequency (MHz) 167 Rating Catalog Operating temperature range (°C) -40 to 105
BGA (ZFN) 256 729 mm² (27 mm × 27 mm) PBGA (GFN) 256 729 mm² (27 mm × 27 mm)
  • Excellent Price/Performance Digital Signal Processors (DSPs): TMS320C62x™ (TMS320C6211 and TMS320C6211B)
    • Eight 32-Bit Instructions/Cycle
    • C6211, C6211B, C6711, and C6711B are Pin-Compatible
    • 150-, 167-MHz Clock Rates
    • 6.7-, 6-ns Instruction Cycle Time
    • 1200, 1333 MIPS
    • Extended Temperature Device (C6211B)
  • VelociTI™ Advanced Very Long Instruction Word (VLIW) C62x™ DSP Core (C6211/11B)
    • Eight Highly Independent Functional Units:
      • Six ALUs (32-/40-Bit)
      • Two 16-Bit Multipliers (32-Bit Results)
    • Load-Store Architecture With 32 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Byte-Addressable (8-, 16-, 32-Bit Data)
    • 8-Bit Overflow Protection
    • Saturation
    • Bit-Field Extract, Set, Clear
    • Bit-Counting
    • Normalization
  • L1/L2 Memory Architecture
    • 32K-Bit (4K-Byte) L1P Program Cache (Direct Mapped)
    • 32K-Bit (4K-Byte) L1D Data Cache (2-Way Set-Associative)
    • 512K-Bit (64K-Byte) L2 Unified Mapped RAM/Cache (Flexible Data/Program Allocation)
  • Device Configuration
    • Boot Mode: HPI, 8-, 16-, and 32-Bit ROM Boot
    • Endianness: Little Endian, Big Endian
  • 32-Bit External Memory Interface (EMIF)
    • Glueless Interface to Asynchronous Memories: SRAM and EPROM
    • Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
    • 512M-Byte Total Addressable External Memory Space
  • Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels)
  • 16-Bit Host-Port Interface (HPI)
    • Access to Entire Memory Map
  • Two Multichannel Buffered Serial Ports (McBSPs)
    • Direct Interface to T1/E1, MVIP, SCSA Framers
    • ST-Bus-Switching Compatible
    • Up to 256 Channels Each
    • AC97-Compatible
    • Serial-Peripheral-Interface (SPI) Compatible (Motorola™)
  • Two 32-Bit General-Purpose Timers
  • Flexible Phase-Locked-Loop (PLL) Clock Generator
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • 256-Pin Ball Grid Array (BGA) Package (GFN and ZFN Suffixes)
  • 0.18-µm/5-Level Metal Process
    • CMOS Technology
  • 3.3-V I/Os, 1.8-V Internal

TMS320C62x, VelociTI, and C62x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
All trademarks are the property of their respective owners.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
  • Excellent Price/Performance Digital Signal Processors (DSPs): TMS320C62x™ (TMS320C6211 and TMS320C6211B)
    • Eight 32-Bit Instructions/Cycle
    • C6211, C6211B, C6711, and C6711B are Pin-Compatible
    • 150-, 167-MHz Clock Rates
    • 6.7-, 6-ns Instruction Cycle Time
    • 1200, 1333 MIPS
    • Extended Temperature Device (C6211B)
  • VelociTI™ Advanced Very Long Instruction Word (VLIW) C62x™ DSP Core (C6211/11B)
    • Eight Highly Independent Functional Units:
      • Six ALUs (32-/40-Bit)
      • Two 16-Bit Multipliers (32-Bit Results)
    • Load-Store Architecture With 32 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Byte-Addressable (8-, 16-, 32-Bit Data)
    • 8-Bit Overflow Protection
    • Saturation
    • Bit-Field Extract, Set, Clear
    • Bit-Counting
    • Normalization
  • L1/L2 Memory Architecture
    • 32K-Bit (4K-Byte) L1P Program Cache (Direct Mapped)
    • 32K-Bit (4K-Byte) L1D Data Cache (2-Way Set-Associative)
    • 512K-Bit (64K-Byte) L2 Unified Mapped RAM/Cache (Flexible Data/Program Allocation)
  • Device Configuration
    • Boot Mode: HPI, 8-, 16-, and 32-Bit ROM Boot
    • Endianness: Little Endian, Big Endian
  • 32-Bit External Memory Interface (EMIF)
    • Glueless Interface to Asynchronous Memories: SRAM and EPROM
    • Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
    • 512M-Byte Total Addressable External Memory Space
  • Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels)
  • 16-Bit Host-Port Interface (HPI)
    • Access to Entire Memory Map
  • Two Multichannel Buffered Serial Ports (McBSPs)
    • Direct Interface to T1/E1, MVIP, SCSA Framers
    • ST-Bus-Switching Compatible
    • Up to 256 Channels Each
    • AC97-Compatible
    • Serial-Peripheral-Interface (SPI) Compatible (Motorola™)
  • Two 32-Bit General-Purpose Timers
  • Flexible Phase-Locked-Loop (PLL) Clock Generator
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • 256-Pin Ball Grid Array (BGA) Package (GFN and ZFN Suffixes)
  • 0.18-µm/5-Level Metal Process
    • CMOS Technology
  • 3.3-V I/Os, 1.8-V Internal

TMS320C62x, VelociTI, and C62x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
All trademarks are the property of their respective owners.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

The TMS320C62x™ DSPs (including the TMS320C6211/C6211B devices) compose one of the fixed-point DSP families in the TMS320C6000™ DSP platform. The TMS320C6211 (C6211) and TMS320C6211B (C6211B) devices are based on the high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications.

With performance of up to 1333 million instructions per second (MIPS) at a clock rate of 167 MHz, the C6211/C6211B device offers cost-effective solutions to high-performance DSP programming challenges. The C6211/C6211B DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide six arithmetic logic units (ALUs) for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. The C6211/C6211B can produce two multiply-accumulates (MACs) per cycle for a total of 333 million MACs per second (MMACS). The C6211/C6211B DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

The C6211/C6211B uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 32-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 32-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 512-Kbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM and asynchronous peripherals.

The C6211/C6211B has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

The TMS320C62x™ DSPs (including the TMS320C6211/C6211B devices) compose one of the fixed-point DSP families in the TMS320C6000™ DSP platform. The TMS320C6211 (C6211) and TMS320C6211B (C6211B) devices are based on the high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications.

With performance of up to 1333 million instructions per second (MIPS) at a clock rate of 167 MHz, the C6211/C6211B device offers cost-effective solutions to high-performance DSP programming challenges. The C6211/C6211B DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide six arithmetic logic units (ALUs) for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. The C6211/C6211B can produce two multiply-accumulates (MACs) per cycle for a total of 333 million MACs per second (MMACS). The C6211/C6211B DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.

The C6211/C6211B uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 32-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 32-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 512-Kbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM and asynchronous peripherals.

The C6211/C6211B has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.
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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 TMS320C6211, TMS320C6211B Fixed-Point Digital Signal Processors 数据表 (Rev. L) 2004-6-9
* 勘误表 TMS320C6211/TMS320C6211B DSPs Silicon Errata (Revs 1.0, 1.1, 2.1, 2.2, 3.0, 3.1) (Rev. L) 2004-5-28
应用手册 如何将 CCS 3.x 工程迁移至最新的 Code Composer Studio™ (CCS) (Rev. A) 英语版 (Rev.A) PDF | HTML 2021-5-19
应用手册 Introduction to TMS320C6000 DSP Optimization 2011-10-6
用户指南 TMS320C62x DSP CPU and Instruction Set Reference Guide (Rev. A) 2010-5-20
用户指南 TMS320C6000 DSP Peripherals Overview Reference Guide (Rev. Q) 2009-7-2
应用手册 TMS320C6000 EMIF-to-External SDRAM Interface (Rev. E) 2007-9-4
应用手册 Thermal Considerations for the DM64xx, DM64x, and C6000 Devices 2007-5-20
用户指南 TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide (Rev. E) 2007-4-11
用户指南 TMS320C6000 DSP Multichannel Buffered Serial Port (McBSP) Reference Guide (Rev. G) 2006-12-14
用户指南 TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (Rev. C) 2006-11-15
用户指南 TMS320C6000 CPU and Instruction Set Reference Guide (Rev. G) 2006-7-11
用户指南 TMS320C6000 DSP Host-Post Interface (HPI) Reference Guide (Rev. C) 2006-1-1
应用手册 Migrating from TMS320C6211B/C6711/C6711B and C6713 to TMS320C6713B (Rev. H) 2005-11-11
应用手册 Migrating From TMS320C6211B/C6711/C6711B/C6711C to TMS320C6711D (Rev. H) 2005-11-10
用户指南 TMS320C6000 DSP Power-Down Logic and Modes Reference Guide (Rev. C) 2005-3-1
用户指南 TMS320C6000 DSP 32-bit Timer Reference Guide (Rev. B) 2005-1-25
用户指南 TMS320C621x/C671x DSP Two Level Internal Memory Reference Guide (Rev. B) 2004-6-8
应用手册 TMS320C6000 Tools: Vector Table and Boot ROM Creation (Rev. D) 2004-4-26
应用手册 TMS320C6000 Board Design: Considerations for Debug (Rev. C) 2004-4-21
应用手册 TMS320C6000 McBSP Initialization (Rev. C) 2004-3-8
应用手册 TMS320C621x/TMS320C671x EDMA Architecture 2004-3-5
应用手册 TMS320C621x/671x EDMA Performance Data 2004-3-5
用户指南 TMS320C6000 DSP Designing for JTAG Emulation Reference Guide 2003-7-31
用户指南 TMS320C6000 DSP Cache User's Guide (Rev. A) 2003-5-5
应用手册 Migrating from TMS320C6211 to TMS320C6211B 2003-4-28
应用手册 Using IBIS Models for Timing Analysis (Rev. A) 2003-4-15
应用手册 Extended Precision Radix-4 Fast Fourier Transform Implemented on the TMS320C62x 2002-11-23
应用手册 TMS320C6000 McBSP Interface to an ST-BUS Device (Rev. B) 2002-6-4
应用手册 TMS320C6000 HPI to PCI Interfacing Using the PLX PCI9050 (Rev. C) 2002-4-17
应用手册 TMS320C6000 DMA Example Applications (Rev. A) 2002-4-10
应用手册 TMS320C6000 Board Design for JTAG (Rev. C) 2002-4-2
应用手册 TMS320C6000 EMIF to External Flash Memory (Rev. A) 2002-2-13
应用手册 Using a TMS320C6000 McBSP for Data Packing (Rev. A) 2001-10-31
应用手册 TMS320C6000 Enhanced DMA: Example Applications (Rev. A) 2001-10-24
应用手册 Interfacing theTMS320C6000 EMIFto a PCI Bus Using the AMCC S5933 PCI Controller (Rev. A) 2001-9-30
应用手册 TMS320C6000 Host Port to MC68360 Interface (Rev. A) 2001-9-30
应用手册 Using the TMS320C6000 McBSP as a High Speed Communication Port (Rev. A) 2001-8-31
应用手册 TMS320C6000 Host Port to the i80960 Microprocessors Interface (Rev. A) 2001-8-31
应用手册 TMS320C6000 EMIF to External Asynchronous SRAM Interface (Rev. A) 2001-8-31
应用手册 TMS320C6000 System Clock Circuit Example (Rev. A) 2001-8-15
应用手册 TMS320C6000 McBSP to Voice Band Audio Processor (VBAP) Interface (Rev. A) 2001-7-23
应用手册 TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27) (Rev. A) 2001-7-10
应用手册 TMS320C6000 McBSP: Interface to SPI ROM (Rev. C) 2001-6-30
应用手册 TMS320C6000 Host Port to MPC860 Interface (Rev. A) 2001-6-21
应用手册 TMS320C6000 McBSP: IOM-2 Interface (Rev. A) 2001-5-21
应用手册 ETSI Math Operations in C for the TMS320C62x (Rev. A) 2000-11-13
应用手册 TMS320C621x/C671x EDMA Queue Management Guidelines 2000-11-7
应用手册 Optimizing JPEG on the TMS320C6211 2-Level Cache DSP 2000-9-13
应用手册 Circular Buffering on TMS320C6000 (Rev. A) 2000-9-12
应用手册 TMS320C6000 McBSP as a TDM Highway (Rev. A) 2000-9-11
应用手册 MPEG-2 Video Decoder: TMS320C62x (TM) DSP Implementation 2000-2-29
应用手册 TMS320C6000 u-Law and a-Law Companding with Software or the McBSP 2000-2-2
应用手册 General Guide to Implement Logarithmic and Exponential Operations on Fixed-Point 2000-1-31
应用手册 G.723.1 Dual Rate Speech Coder: Multichannel TMS320C62x Implementation (Rev. B) 2000-1-4
应用手册 GSM Enhanced Full Rate Speech Coder: Multichannel TMS320C62x Implementation (Rev. B) 2000-1-4
应用手册 IS-127 Enhanced Var Rate Speech Coder:Multichannel TMS320C62x Implementation (Rev. B) 2000-1-4
应用手册 G.729/A Speech Coder: Multichannel TMS320C62x Implementation (Rev. B) 2000-1-4
应用手册 TMS320C6000 C Compiler: C Implementation of Intrinsics 1999-12-7
应用手册 TMS320C6000 McBSP: I2S Interface 1999-9-8
应用手册 On the Implementation of MPEG-4 Motion Compensation Using the TMS320C62x 1999-7-29

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仿真模型

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