Enhanced product C6424 fixed point DSP
产品详细信息
参数
封装|引脚|尺寸
特性
- High-Performance Digital Signal Processor (C6424)
- 2.5-, 2-, 1.67-, 1.43-ns Instruction Cycle Time
- 400-, 500-, 600-, 700-MHz C64x+™ Clock Rate
- Eight 32-Bit C64x+ Instructions/Cycle
- 3200, 4000, 4800, 5600 MIPS
- Fully Software-Compatible With C64x
- Commercial and Automotive (Q or S suffix) Grades
- Low-Power Device (L suffix)
- VelociTI.2™ Extensions to VelociTI™ Advanced
Very-Long-Instruction-Word (VLIW) SM320C64x+™ DSP Core- Eight Highly Independent Functional Units
With VelociTI.2 Extensions:- Six ALUs (32-/40-Bit), Each Supports Single 32-Bit,
Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle - Two Multipliers Support Four 16 & times 16-Bit Multiplies
(32-Bit Results) per Clock Cycle or Eight 8 × 8-Bit
Multiplies (16-Bit Results) per Clock Cycle
- Six ALUs (32-/40-Bit), Each Supports Single 32-Bit,
- Load-Store Architecture With Non-Aligned Support
- 64 32-Bit General-Purpose Registers
- Instruction Packing Reduces Code Size
- All Instructions Conditional
- Additional C64x+™ Enhancements
- Protected Mode Operation
- Exceptions Support for Error Detection
and Program Redirection - Hardware Support for Modulo Loop
Auto-Focus Module Operation
- Eight Highly Independent Functional Units
- C64x+ Instruction Set Features
- Byte-Addressable (8-/16-/32-/64-Bit Data)
- 8-Bit Overflow Protection
- Bit-Field Extract, Set, Clear
- Normalization, Saturation, Bit-Counting
- VelociTI.2 Increased Orthogonality
- C64x+ Extensions
- Compact 16-bit Instructions
- Additional Instructions to Support Complex Multiplies
- C64x+ L1/L2 Memory Architecture
- 256K-Bit (32K-Byte) L1P Program
RAM/Cache [Flexible Allocation] - 640K-Bit (80K-Byte) L1D Data RAM/Cache
[Flexible Allocation] - 1M-Bit (128K-Byte) L2 Unified Mapped
RAM/Cache [Flexible Allocation]
- 256K-Bit (32K-Byte) L1P Program
- Endianess: Supports Both Little Endian and Big Endian
- External Memory Interfaces (EMIFs)
- 32-Bit DDR2 SDRAM Memory Controller
With 256M-Byte Address Space (1.8-V I/O)- Supports up to 333-MHz (data rate) bus
and interfaces to DDR2-400 SDRAM
- Supports up to 333-MHz (data rate) bus
- Asynchronous 16-Bit Wide EMIF (EMIFA)
With up to 128M-Byte Address Reach- Flash Memory Interfaces
- NOR (8-/16-Bit-Wide Data)
- NAND (8-/16-Bit-Wide Data)
- Flash Memory Interfaces
- 32-Bit DDR2 SDRAM Memory Controller
- Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels) - Two 64-Bit General-Purpose Timers (Each
Configurable as Two 32-Bit Timers) - One 64-Bit Watch Dog Timer
- Two UARTs (One with RTS and CTS Flow Control)
- Master/Slave Inter-Integrated Circuit (I2C Bus™)
- Two Multichannel Buffered Serial Ports (McBSPs)
- I2S and TDM
- AC97 Audio Codec Interface
- SPI
- Standard Voice Codec Interface (AIC12)
- Telecom Interfaces – ST-Bus, H-100
- 128 Channel Mode
- Multichannel Audio Serial Port (McASP0)
- Four Serializers and SPDIF (DIT) Mode
- 16-Bit Host-Port Interface (HPI)
- 32-Bit 33-MHz, 3.3-V Peripheral Component
Interconnect (PCI) Master/Slave Interface - 10/100 Mb/s Ethernet MAC (EMAC)
- IEEE 802.3 Compliant
- Supports Multiple Media Independent Interfaces
(MII, RMII) - Management Data Input/Output (MDIO) Module
- VLYNQ™ Interface (FPGA Interface)
- Three Pulse Width Modulator (PWM) Outputs
- On-Chip ROM Bootloader
- Individual Power-Savings Modes
- Flexible PLL Clock Generators
- IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible
- Up to 111 General-Purpose I/O (GPIO) Pins
(Multiplexed With Other Device Functions) - Packages:
- 376-Pin Plastic BGA Package, 1.0-mm Ball Pitch
- 0.09-µm/6-Level Cu Metal Process (CMOS)
- 3.3-V and 1.8-V I/O, 1.2-V Internal
(-7/-6/-5/-4/Q6/-Q5/-Q4) - 3.3-V and 1.8-V I/O, 1.05-V Internal
(-7/-6/-5/-4/-L/-Q5) - Applications:
- Telecom
- Audio
- Industrial Applications
- SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS
- Controlled Baseline
- One Assembly/Test Site
- One Fabrication Site
- Extended Product Life Cycle
- Extended Product-Change Notification
- Product Traceability
All trademarks are the property of their respective owners.
描述
The 320C64x+ DSPs (including the SMS320C6424 device) are the highest-performance fixed-point DSP generation in the 320C6000 DSP platform. The C6424 device is based on the third-generation high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for digital signal processor applications. The C64x+ devices are upward code-compatible from previous devices that are part of the C6000 DSP platform. The C64x DSPs support added functionality and have an expanded instruction set from previous devices.
Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively.
With performance of up to 5600 million instructions per second (MIPS) at a clock rate of 700 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional unitstwo multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in telecom, audio, and industrial applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2800 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 5600 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732).
The C6424 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The C6424 core uses a two-level cache-based architecture. The Level 1 program memory/cache (L1P) consists of a 256K-bit memory space that can be configured as mapped memory or direct mapped cache, and the Level 1 data (L1D) consists of a 640K-bit memory space 384K-bit of which is mapped memory and 256K-bit of which can be configured as mapped memory or 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 1M-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.
The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a management data input/output (MDIO) module; a 4-bit transmit, 4-bit receive VLYNQ interface; an inter-integrated circuit (I2C) Bus interface; two multichannel buffered serial ports (McBSPs); a multichannel audio serial port (McASP0) with 4 serializers; 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; a user-configurable 16-bit host-port interface (HPI); up to 111-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 2 UARTs with hardware handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; 1 peripheral component interconnect (PCI) [33 MHz]; and 2 glueless external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2.
The Ethernet Media Access Controller (EMAC) provides an efficient interface between the C6424 and the network. The C6424 EMAC supports 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.
The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system.
The I2C and VLYNQ ports allow C6424 to easily control peripheral devices and/or communicate with host processors.
The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.
The C6424 has a complete set of development tools. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution.
技术文档
类型 | 标题 | 下载最新的英文版本 | 日期 | |
---|---|---|---|---|
* | 数据表 | Fixed-Point Digital Signal Processor 数据表 | 2009年 6月 8日 | |
* | VID | SM320C6424-EP VID V6209629 | 2016年 6月 21日 | |
* | 辐射与可靠性报告 | SM320C6424GDUQ6EP Reliability Report | 2013年 3月 22日 | |
技术文章 | Bringing the next evolution of machine learning to the edge | 2018年 11月 27日 | ||
技术文章 | Industry 4.0 spelled backward makes no sense – and neither does the fact that you haven’t heard of TI’s newest processor yet | 2018年 10月 30日 | ||
技术文章 | How quality assurance on the Processor SDK can improve software scalability | 2018年 8月 22日 | ||
技术文章 | Clove: Low-Power video solutions based on Sitara™ AM57x processors | 2016年 7月 21日 | ||
应用手册 | Power Consumption Guide for the C66x | 2011年 10月 6日 |
设计与开发
有关其他条款或所需资源,请点击下面的任何链接来查看详情页面。硬件开发
说明
Spectrum Digital XDS200 是最新 XDS200 系列 TI 处理器调试探针(仿真器)的首个模型。XDS200 系列拥有超低成本 XDS100 与高性能 XDS560v2 之间的低成本与高性能的完美平衡。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS 调试探针均支持内核和系统跟踪。
Spectrum Digital XDS200 通过 TI 20 引脚连接器(带有适合 TI 14 引脚、TI 10 引脚和 ARM 20 引脚的多个适配器)连接到目标板,而通过 USB2.0 高速连接 (480Mbps) 连接到主机 PC。要在主机 PC 上运行,还需要 Code Composer Studio™ IDE 许可证。
(...)
特性
XDS200 是最新的 JTAG 系列 TI 处理器调试探针(仿真器)。XDS200 旨在提供良好的性能和最常见的功能,定位于低成本 XDS100 和高性能 XDS560v2 之间,是用于调试 TI 微控制器、处理器和无线器件的均衡型解决方案。
XDS200 适合取代老化的 XDS510 系列 JTAG 调试器,其具有更高的 JTAG 数据吞吐量、增加了对 ARM 串行线调试模式的支持并降低了成本。
XDS200 的所有型号均顺应在现代 TI 开发板上减小空间的趋势,为此提供标准的 TI 20 引脚连接器作为与目标之间的主要 JTAG 连接。此外,所有型号都提供针对 TI 和 ARM 标准 JTAG 接头的模块化目标配置适配器(提供的适配器因型号而异)。
XDS200 支持传统的 IEEE1149.1 (JTAG)、IEEE1149.7 (cJTAG) 以及 ARM 的串行线调试 (SWD) 和串行线输出 (SWO),运行时的接口电平为 +1.5V 到 4.1V。
与传统 JTAG 相比,IEEE1149.7 或紧凑 JTAG (cJTAG) 有巨大的进步;因为它仅需使用两个引脚即可支持所有功能,可用于某些指定的 TI 无线连接微控制器中。
串行线调试 (SWD) 作为一种调试模式,也使用两个引脚,并且与 JTAG 相比能够以更高的时钟速率传输数据。串行线输出 (SWO) 多增加了一个引脚,此引脚允许对指定的 Cortex M4 微控制器执行简单的跟踪操作。
所有 XDS200 型号均支持通过 USB2.0 高速连接 (480Mbps) 连接到主机,某些型号还支持以太网 10/100Mbps。此外,某些型号支持对目标板进行功耗监控。
(...)
说明
XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针(仿真器)的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。
XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件,通过捕获相关器件级信息,获得准确的总线性能活动和吞吐量,并对内核和外设进行电源管理。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS 调试探针均支持内核和系统跟踪。
Blackhawk XDS560v2 System Trace 通过 MIPI HSPT 60 引脚连接器(带有适合 TI 14 引脚、TI 20 引脚和 ARM 20 (...)
特性
XDS560v2 是 XDS560 系列高性能 TI 处理器调试探针(仿真器)的最新型号。XDS560v2 具有整个系列中最快的速度和最多的功能,对于 TI 微控制器、处理器和无线连接微控制器的调试来说,它是最全面的解决方案。
XDS560v2 是 XDS560 调试探针系列中最先提供系统跟踪 (STM) 功能的一款,这种类型的跟踪可以通过捕获系统事件(例如处理内核的状态、内部总线和外设)来监控整个设备。大多数 XDS560v2 模型还提供系统引脚跟踪模式,在这种模式中,系统跟踪数据被送到 XDS560v2 内的外部存储器缓冲区 (128MB),因此能够捕获大量系统事件。系统引脚跟踪数据连接需要通过额外的接线连接 JTAG 连接器。
在 XDS560 调试探针系列中,XDS560v2 PRO TRACE 是提供内核引脚跟踪功能(指令和数据)的第二代产品,这种跟踪可以捕获内核执行的所有指令并将其发送到 XDS560v2 PRO TRACE 内的外部存储器缓冲区 (1GB)。内核引脚跟踪并不干扰系统的实时行为,而且可以捕获更多的指令。内核引脚跟踪数据连接需要通过额外的接线连接 JTAG 连接器。
为了支持所有类型的引脚跟踪(指令和系统),XDS560v2 的所有型号都提供标准的 60 引脚 MIPI HSPT 连接器作为与目标之间的主要 JTAG 连接。此外,所有型号都提供针对 TI 和 ARM 标准 JTAG 连接器的模块化目标适配器(提供的适配器因型号而异)。
XDS560v2 支持传统的 IEEE1149.1 (JTAG) 仿真和 IEEE1149.7 (cJTAG),运行时的 JTAG 接口电平为 1.2V 至 +4.1V。
与传统 JTAG 相比,紧凑 JTAG (cJTAG) 有巨大的进步;因为它仅需使用两个引脚即可支持所有功能,可用于某些指定的 TI 无线连接微控制器中。
所有 XDS560v2 (...)
说明
XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针(仿真器)的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。
XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件,通过捕获相关器件级信息,获得准确的总线性能活动和吞吐量,并对内核和外设进行电源管理。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS 调试探针均支持内核和系统跟踪。
Spectrum Digital XDS560v2 System Trace 通过 MIPI HSPT 60 引脚连接器(适合 TI 14 引脚、TI 20 引脚、ARM 20 引脚和 TI 60 (...)
特性
XDS560v2 是 XDS560 系列高性能 TI 处理器调试探针(仿真器)的最新型号。XDS560v2 具有整个系列中最快的速度和最多的功能,对于 TI 微控制器、处理器和无线连接微控制器的调试来说,它是最全面的解决方案。
XDS560v2 是 XDS560 调试探针系列中最先提供系统跟踪 (STM) 功能的一款,这种类型的跟踪可以通过捕获系统事件(例如处理内核的状态、内部总线和外设)来监控整个设备。大多数 XDS560v2 模型还提供系统引脚跟踪模式,在这种模式中,系统跟踪数据被送到 XDS560v2 内的外部存储器缓冲区 (128MB),因此能够捕获大量系统事件。系统引脚跟踪数据连接需要通过额外的接线连接 JTAG 连接器。
在 XDS560 调试探针系列中,XDS560v2 PRO TRACE 是提供内核引脚跟踪功能(指令和数据)的第二代产品,这种跟踪可以捕获内核执行的所有指令并将其发送到 XDS560v2 PRO TRACE 内的外部存储器缓冲区 (1GB)。内核引脚跟踪并不干扰系统的实时行为,而且可以捕获更多的指令。内核引脚跟踪数据连接需要通过额外的接线连接 JTAG 连接器。
为了支持所有类型的引脚跟踪(指令和系统),XDS560v2 的所有型号都提供标准的 60 引脚 MIPI HSPT 连接器作为与目标之间的主要 JTAG 连接。此外,所有型号都提供针对 TI 和 ARM 标准 JTAG 连接器的模块化目标适配器(提供的适配器因型号而异)。
XDS560v2 支持传统的 IEEE1149.1 (JTAG) 仿真和 IEEE1149.7 (cJTAG),运行时的 JTAG 接口电平为 1.2V 至 +4.1V。
与传统 JTAG 相比,紧凑 JTAG (cJTAG) 有巨大的进步;因为它仅需使用两个引脚即可支持所有功能,可用于某些指定的 TI 无线连接微控制器中。
所有 XDS560v2 (...)
软件开发
特性
Optimized DSP routines including functions for:
- Adaptive filtering
- Correlation
- FFT
- Filtering and convolution: FIR, biquad, IIR, convolution
- Math: Dot products, max value, min value, etc.
- Matrix operations
设计工具和仿真
特性
- Supports many TI processors including Sitara and Jacinto Processors and DSPs
- Search by type of product, TI devices supported, or country
- Links and contacts for quick engagement
- Third-party companies located around the world
CAD/CAE 符号
封装 | 引脚 | 下载 |
---|---|---|
BGA (GDU) | 376 | 了解详情 |
订购与质量
- RoHS
- REACH
- 器件标识
- 引脚镀层/焊球材料
- MSL 等级/回流焊峰值温度
- MTBF/FIT 估算
- 材料成分
- 认证摘要
- 持续可靠性监测