SMJ320C6201B
- Highest Performance Fixed-Point Digital Signal Processor (DSP) SM/SMJ320C6201B
- 5-, 6.7-ns Instruction Cycle Time
- 150 and 200-MHz Clock Rate
- Eight 32-Bit Instructions/Cycle
- 1200 and 1600 MIPS
- VelociTI™ Advanced Very Long Instruction Word (VLIW) C62x™ CPU Core
- Eight Independent Functional Units:
- Six ALUs (32-/40-Bit)
- Two 16-Bit Multipliers (32-Bit Results)
- Load-Store Architecture With 32 32-Bit General-Purpose Registers
- Instruction Packing Reduces Code Size
- All Instructions Conditional
- Eight Independent Functional Units:
- Instruction Set Features
- Byte-Addressable (8-, 16-, 32-Bit Data)
- 32-Bit Address Range
- 8-Bit Overflow Protection
- Saturation
- Bit-Field Extract, Set, Clear
- Bit-Counting
- Normalization
- 1M-Bit On-Chip SRAM
- 512K-Bit Internal Program/Cache (16K 32-Bit Instructions)
- 512K-Bit Dual-Access Internal Data (64K Bytes) Organized as Two Blocks for Improved Concurrency
- 32-Bit External Memory Interface (EMIF)
- Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
- Glueless Interface to Asynchronous Memories: SRAM and EPROM
- Four-Channel Bootloading Direct-Memory-Access (DMA) Controller with an Auxiliary Channel
- 16-Bit Host-Port Interface (HPI)
- Access to Entire Memory Map
- Two Multichannel Buffered Serial Ports (McBSPs)
- Direct Interface to T1/E1, MVIP, SCSA Framers
- ST-Bus-Switching Compatible
- Up to 256 Channels Each
- AC97-Compatible
- Serial Peripheral Interface (SPI) Compatible (Motorola™)
- Two 32-Bit General-Purpose Timers
- Flexible Phase-Locked Loop (PLL) Clock Generator
- IEEE-1149.1 (JTAG
) Boundary-Scan Compatible - 429-Pin BGA Package (GLP Suffix)
- CMOS Technology
- 0.18-um/5-Level Metal Process
- 3.3-V I/Os, 1.8-V Internal
C62x and VelociTI are trademarks of Texas Instruments Incorporated.
Motorola is a trademark of Motorola, Inc. IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
TI is a trademark of Texas Instruments Incorporated.
Windows is a registered trademark of the Microsoft Corporation.
The 320C6201B DSP is a member of the fixed-point DSP family in the 320C6000 platform. The SM/SMJ320C6201B (C6201B) device is based on the high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI™), making this DSP an excellent choice for multichannel and multifunction applications. With performance of up to 1600 million instructions per second (MIPS) at a clock rate of 200 MHz, the C6201B offers cost-effective solutions to high-performance DSP programming challenges. The C6201B is a newer revision of the C6201. The C6201B DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide six arithmetic logic units (ALUs) for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. The C6201B can produce two multiply-accumulates (MACs) per cycle - for a total of 400 million MACs per second (MMACS). The C6201B DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.
The C6201B includes a large bank of on-chip memory and has a powerful and diverse set of peripherals. Program memory consists of a 64K-byte block that is user-configurable as cache or memory-mapped program space. Data memory of the C6201B consists of two 32K-byte blocks of RAM for improved concurrency. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.
The C6201B has a complete set of development tools which includes: a new C compiler, a third-party Ada 95 compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.
技术文档
| 类型 | 标题 | 下载最新的英文版本 | 日期 | |
|---|---|---|---|---|
| * | 数据表 | SM320C6201B, SMJ320C6201B Digital Signal Processor 数据表 (Rev. B) | 2001年 8月 31日 | |
| * | SMD | SMJ320C6201B SMD 5962-98578 | 2016年 6月 21日 | |
| 技术文章 | Bringing the next evolution of machine learning to the edge | 2018年 11月 27日 | ||
| 技术文章 | How quality assurance on the Processor SDK can improve software scalability | 2018年 8月 22日 | ||
| 技术文章 | Clove: Low-Power video solutions based on Sitara™ AM57x processors | 2016年 7月 21日 | ||
| 技术文章 | TI's new DSP Benchmark Site | 2016年 2月 8日 | ||
| 应用手册 | Power Consumption Guide for the C66x | 2011年 10月 6日 | ||
| 更多文献资料 | SMJ320C6201B/5962-9857801QXA (Rev. O) | 2002年 5月 3日 | ||
| 更多文献资料 | Military C6000 DSPs (Rev. A) | 2000年 5月 8日 |
设计与开发
有关其他条款或所需资源，请点击下面的任何链接来查看详情页面。
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XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件，通过捕获相关器件级信息，获得准确的总线性能活动和吞吐量，并对内核和外设进行电源管理。此外，对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器，所有 XDS 调试探针均支持内核和系统跟踪。
Blackhawk XDS560v2 System Trace 通过 MIPI HSPT 60 引脚连接器（带有适合 TI 14 引脚、TI 20 引脚和 ARM 20 (...)
TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 系统跟踪 USB 和以太网
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XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件，通过捕获相关器件级信息，获得准确的总线性能活动和吞吐量，并对内核和外设进行电源管理。此外，对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器，所有 XDS 调试探针均支持内核和系统跟踪。
Spectrum Digital XDS560v2 System Trace 通过 MIPI HSPT 60 引脚连接器（适合 TI 14 引脚、TI 20 引脚、ARM 20 引脚和 TI 60 (...)
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该版本还包括 FastRTS Library 中可用函数子集的 C 语言实施。C 代码可让用户内联这些函数并获得更高性能。
特性
| 单精度和双精度数学函数 | 单精度和双精度转换函数 |
| 浮点加法 | 将浮点值转换为 32 位带符号整数值 |
| 将 32 位带符号整数值转换为浮点值 | |
| 浮点减法 | 将浮点值转换为 40 位带符号长整数值 |
| 将 40 位带符号长整数值转换为浮点值 | |
| 浮点乘法 | 将浮点值转换为 32 位无符号整数值 |
| 将 32 位无符号整数值转换为浮点值 | |
| 浮点倒数 | 将浮点值转换为 40 位无符号长整数值 |
| 将 40 位无符号长整数值转换为浮点值 | |
| 浮点减法 | 将双精度浮点值转换为单精度浮点值 |
| 将单精度浮点值转换为双精度浮点值 |
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PROCESSORS-3P-SEARCH — Arm-based MPU, arm-based MCU and DSP third-party search tool
| 封装 | 引脚 | 下载 |
|---|---|---|
| CFCBGA (GLP) | 429 | 了解详情 |
订购与质量
- RoHS
- REACH
- 器件标识
- 引脚镀层/焊球材料
- MSL 等级/回流焊峰值温度
- MTBF/FIT 估算
- 材料成分
- 认证摘要
- 持续可靠性监测