产品详细信息

DSP 1 C64x+ DSP MHz (Max) 400, 500, 600 CPU 32-/64-bit Operating system DSP/BIOS Ethernet MAC 10/100 Rating Catalog Operating temperature range (C) -40 to 105, 0 to 90
DSP 1 C64x+ DSP MHz (Max) 400, 500, 600 CPU 32-/64-bit Operating system DSP/BIOS Ethernet MAC 10/100 Rating Catalog Operating temperature range (C) -40 to 105, 0 to 90
BGA (ZDU) 376 529 mm² 23 x 23 NFBGA (ZWT) 361 256 mm² 16 x 16
  • High-Performance Digital Signal Processor (C6424)
    • 2.5-, 2-, 1.67, 1.43-ns Instruction Cycle Time
    • 400-, 500-, 600-MHz C64x+™ Clock Rate
    • Eight 32-Bit C64x+ Instructions/Cycle
    • 3200, 4000, 4800, 5600 MIPS
    • Fully Software-Compatible With C64x
    • Commercial and Automotive (Q or S suffix)Grades
    • Low-Power Device (L suffix)
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2 Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 × 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 × 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Additional C64x+™ Enhancements
      • Protected Mode Operation
      • Exceptions Support for Error Detection and Program Redirection
      • Hardware Support for Modulo Loop Auto-Focus Module Operation
  • C64x+ Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2 Increased Orthogonality
    • C64x+ Extensions
      • Compact 16-bit Instructions
      • Additional Instructions to Support Complex Multiplies
  • C64x+ L1/L2 Memory Architecture
    • 256K-Bit (32K-Byte) L1P Program RAM/Cache [Flexible Allocation]
    • 640K-Bit (80K-Byte) L1D Data RAM/Cache [Flexible Allocation]
    • 1M-Bit (128K-Byte) L2 Unified Mapped RAM/Cache [Flexible Allocation]
  • Endianess: Supports Both Little Endian and Big Endian
  • External Memory Interfaces (EMIFs)
    • 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8-V I/O)
      • Supports up to 333-MHz (data rate) bus and interfaces to DDR2-400 SDRAM
    • Asynchronous 16-Bit Wide EMIF (EMIFA) With up to 128M-Byte Address Reach
      • Flash Memory Interfaces
        • NOR (8-/16-Bit-Wide Data)
        • NAND (8-/16-Bit-Wide Data)
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit Watch Dog Timer
  • Two UARTs (One with RTS and CTS Flow Control)
  • Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • Two Multichannel Buffered Serial Ports (McBSPs)
    • I2S and TDM
    • AC97 Audio Codec Interface
    • SPI
    • Standard Voice Codec Interface (AIC12)
    • Telecom Interfaces - ST-Bus, H-100
    • 128 Channel Mode
  • Multichannel Audio Serial Port (McASP0)
    • Four Serializers and SPDIF (DIT) Mode
  • 16-Bit Host-Port Interface (HPI)
  • 32-Bit 33-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface
  • 10/100 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Supports Multiple Media Independent Interfaces (MII, RMII)
    • Management Data Input/Output (MDIO) Module
  • VLYNQ™ Interface (FPGA Interface)
  • Three Pulse Width Modulator (PWM) Outputs
  • On-Chip ROM Bootloader
  • Individual Power-Savings Modes
  • Flexible PLL Clock Generators
  • IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible
  • Up to 111 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
  • Packages:
    • 361-Pin Pb-Free PBGA Package (ZWT Suffix), 0.8-mm Ball Pitch
    • 376-Pin Plastic BGA Package (ZDU Suffix), 1.0-mm Ball Pitch
  • 0.09-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V and 1.8-V I/O, 1.2-V Internal (-7/-6/-5/-4/-Q6/-Q5/-Q4)
  • 3.3-V and 1.8-V I/O, 1.05-V Internal (-7/-6/-5/-4/-L/-Q5)
  • APPLICATIONS
    • Telecom
    • Audio
    • Industrial Applications
  • Community Reesources

All trademarks are the property of their respective owners.

  • High-Performance Digital Signal Processor (C6424)
    • 2.5-, 2-, 1.67, 1.43-ns Instruction Cycle Time
    • 400-, 500-, 600-MHz C64x+™ Clock Rate
    • Eight 32-Bit C64x+ Instructions/Cycle
    • 3200, 4000, 4800, 5600 MIPS
    • Fully Software-Compatible With C64x
    • Commercial and Automotive (Q or S suffix)Grades
    • Low-Power Device (L suffix)
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2 Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 × 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 × 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Additional C64x+™ Enhancements
      • Protected Mode Operation
      • Exceptions Support for Error Detection and Program Redirection
      • Hardware Support for Modulo Loop Auto-Focus Module Operation
  • C64x+ Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2 Increased Orthogonality
    • C64x+ Extensions
      • Compact 16-bit Instructions
      • Additional Instructions to Support Complex Multiplies
  • C64x+ L1/L2 Memory Architecture
    • 256K-Bit (32K-Byte) L1P Program RAM/Cache [Flexible Allocation]
    • 640K-Bit (80K-Byte) L1D Data RAM/Cache [Flexible Allocation]
    • 1M-Bit (128K-Byte) L2 Unified Mapped RAM/Cache [Flexible Allocation]
  • Endianess: Supports Both Little Endian and Big Endian
  • External Memory Interfaces (EMIFs)
    • 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8-V I/O)
      • Supports up to 333-MHz (data rate) bus and interfaces to DDR2-400 SDRAM
    • Asynchronous 16-Bit Wide EMIF (EMIFA) With up to 128M-Byte Address Reach
      • Flash Memory Interfaces
        • NOR (8-/16-Bit-Wide Data)
        • NAND (8-/16-Bit-Wide Data)
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit Watch Dog Timer
  • Two UARTs (One with RTS and CTS Flow Control)
  • Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • Two Multichannel Buffered Serial Ports (McBSPs)
    • I2S and TDM
    • AC97 Audio Codec Interface
    • SPI
    • Standard Voice Codec Interface (AIC12)
    • Telecom Interfaces - ST-Bus, H-100
    • 128 Channel Mode
  • Multichannel Audio Serial Port (McASP0)
    • Four Serializers and SPDIF (DIT) Mode
  • 16-Bit Host-Port Interface (HPI)
  • 32-Bit 33-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface
  • 10/100 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Supports Multiple Media Independent Interfaces (MII, RMII)
    • Management Data Input/Output (MDIO) Module
  • VLYNQ™ Interface (FPGA Interface)
  • Three Pulse Width Modulator (PWM) Outputs
  • On-Chip ROM Bootloader
  • Individual Power-Savings Modes
  • Flexible PLL Clock Generators
  • IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible
  • Up to 111 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
  • Packages:
    • 361-Pin Pb-Free PBGA Package (ZWT Suffix), 0.8-mm Ball Pitch
    • 376-Pin Plastic BGA Package (ZDU Suffix), 1.0-mm Ball Pitch
  • 0.09-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V and 1.8-V I/O, 1.2-V Internal (-7/-6/-5/-4/-Q6/-Q5/-Q4)
  • 3.3-V and 1.8-V I/O, 1.05-V Internal (-7/-6/-5/-4/-L/-Q5)
  • APPLICATIONS
    • Telecom
    • Audio
    • Industrial Applications
  • Community Reesources

All trademarks are the property of their respective owners.

The TMS320C64x+™ DSPs (including the TMS320C6424 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The C6424 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for digital signal processor applications. The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform. The C64x™ DSPs support added functionality and have an expanded instruction set from previous devices.

Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively.

With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in telecom, audio, and industrial applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732).

The C6424 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The C6424 core uses a two-level cache-based architecture. The Level 1 program memory/cache (L1P) consists of a 256K-bit memory space that can be configured as mapped memory or direct mapped cache, and the Level 1 data (L1D) consists of a 640K-bit memory space–384K-bit of which is mapped memory and 256K-bit of which can be configured as mapped memory or 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 1M-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a management data input/output (MDIO) module; a 4-bit transmit, 4-bit receive VLYNQ interface; an inter-integrated circuit (I2C) Bus interface; two multichannel buffered serial ports (McBSPs); a multichannel audio serial port (McASP0) with 4 serializers; 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; a user-configurable 16-bit host-port interface (HPI); up to 111-pins of general-purposeinput/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 2 UARTs with hardware handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; 1 peripheral component interconnect (PCI) [33 MHz]; and 2 glueless external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the C6424 and the network. The C6424 EMAC supports 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.

The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system.

The I2C and VLYNQ ports allow C6424 to easily control peripheral devices and/or communicate with host processors.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The C6424 has a complete set of development tools. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

The TMS320C64x+™ DSPs (including the TMS320C6424 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The C6424 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for digital signal processor applications. The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform. The C64x™ DSPs support added functionality and have an expanded instruction set from previous devices.

Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively.

With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in telecom, audio, and industrial applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732).

The C6424 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The C6424 core uses a two-level cache-based architecture. The Level 1 program memory/cache (L1P) consists of a 256K-bit memory space that can be configured as mapped memory or direct mapped cache, and the Level 1 data (L1D) consists of a 640K-bit memory space–384K-bit of which is mapped memory and 256K-bit of which can be configured as mapped memory or 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 1M-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a management data input/output (MDIO) module; a 4-bit transmit, 4-bit receive VLYNQ interface; an inter-integrated circuit (I2C) Bus interface; two multichannel buffered serial ports (McBSPs); a multichannel audio serial port (McASP0) with 4 serializers; 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; a user-configurable 16-bit host-port interface (HPI); up to 111-pins of general-purposeinput/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 2 UARTs with hardware handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; 1 peripheral component interconnect (PCI) [33 MHz]; and 2 glueless external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the C6424 and the network. The C6424 EMAC supports 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.

The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system.

The I2C and VLYNQ ports allow C6424 to easily control peripheral devices and/or communicate with host processors.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.

The C6424 has a complete set of development tools. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

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技术文档

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类型 项目标题 下载最新的英语版本 日期
* 数据表 TMS320C6424 Fixed-Point Digital Signal Processor 数据表 (Rev. D) 11 Jan 2010
* 勘误表 TMS320C6424/21 Digital Signal Processor Silicon Errata (Revs 1.3 1.2 1.1 & 1.0) (Rev. D) 12 Aug 2011
应用手册 如何将 CCS 3.x 工程迁移至最新的 Code Composer Studio™ (CCS) (Rev. A) 下载英文版本 (Rev.A) PDF | HTML 19 May 2021
用户指南 SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V) 01 Jun 2020
技术文章 Difficult to see. Always in motion is the future 04 Jan 2016
技术文章 Announcing the new entry-level Sitara processor 09 Dec 2015
技术文章 Automotive Surround View Technology trends 31 Aug 2015
应用手册 Plastic Ball Grid Array [PBGA] Application Note (Rev. B) 13 Aug 2015
技术文章 Where are DSPs used? What makes them so good at math? How do they work with Open APIs? 06 Aug 2015
应用手册 Using the TMS320C642x Bootloader (Rev. B) 23 Mar 2012
应用手册 TMS320C642x Power Consumption Summary (Rev. D) 17 Feb 2012
应用手册 Power Consumption Guide for the C66x 06 Oct 2011
用户指南 TMS320C642x DSP Inter-Integrated Circuit (I2C) Module User's Guide (Rev. D) 25 Mar 2011
用户指南 TMS320C642x DSP DDR2 Memory Controller User's Guide (Rev. B) 12 Jan 2011
用户指南 TMS320C642x DSP EMAC/MDIO User's Guide (Rev. C) 23 Dec 2010
用户指南 TMS320C642x DSP Pulse-Width Modulator (PWM) User's Guide (Rev. B) 05 Aug 2010
用户指南 TMS320C642x DSP 64-Bit Timer User's Guide (Rev. A) 03 Aug 2010
用户指南 TMS320C64x+ DSP Megamodule Reference Guide (Rev. K) 03 Aug 2010
用户指南 TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (Rev. J) 30 Jul 2010
用户指南 TMS320C642x DSP Peripheral Component Interconnect (PCI) User's Guide (Rev. C) 14 May 2010
用户指南 TMS320C642x DSP Universal Asynchronous Receiver/Transmitter (UART) User's Guide (Rev. C) 15 Dec 2009
用户指南 TMS320C642x DSP Asynchronous External Memory Interface User's Guide (Rev. B) 24 Feb 2009
用户指南 TMS320C64x+ DSP Cache User's Guide (Rev. B) 11 Feb 2009
应用手册 Implementing DDR2 PCB Layout on the TMS320C6424 DSP 16 Oct 2008
应用手册 12Vin C642x Power using Integrated-FET DCDC Converters and LDO 09 Oct 2008
应用手册 5Vin C642x Power using a PMIC (Multi-output DCDC Converter) 09 Oct 2008
应用手册 TMS320C6000 McBSP: UART (Rev. C) 09 Sep 2008
应用手册 EDMA v2.0 to EDMA v3.0 (EDMA3) Migration Guide (Rev. A) 21 Aug 2008
应用手册 Understanding TI’s PCB Routing Rule-Based DDR Timing Specification (Rev. A) 17 Jul 2008
用户指南 TMS320C642x DSP Host Port Interface (HPI) User's Guide (Rev. A) 16 Jul 2008
用户指南 TMS320C64x+ DSP Image/Video Processing Library (v2.0) Programmer's Reference (Rev. A) 05 May 2008
用户指南 TMS320C642x DSP General-Purpose Input/Output (GPIO) User's Guide (Rev. A) 18 Mar 2008
用户指南 TMS320C642x DSP Multichannel Audio Serial Port (McASP) User's Guide (Rev. C) 13 Mar 2008
用户指南 TMS320C64x+ DSP Little-Endian Library Programmer's Reference (Rev. B) 06 Mar 2008
用户指南 TMS320C642x DSP Enhanced DMA (EDMA) Controller User's Guide (Rev. A) 03 Mar 2008
用户指南 TMS320C642x DSP Power and Sleep Controller (PSC) User's Guide (Rev. A) 05 Feb 2008
用户指南 TMS320C642x DSP Phase-Locked Loop Controller (PLLC) User's Guide (Rev. B) 12 Dec 2007
应用手册 Using DMA with Framework Components for C64x+ (Rev. A) 29 Oct 2007
用户指南 TMS320C642x DSP VLYNQ Port User's Guide (Rev. B) 20 Sep 2007
用户指南 TMS320C642x DSP Multichannel Buffered Serial Port (McBSP) User's Guide (Rev. B) 17 Sep 2007
应用手册 TMS320C642x Pin Multiplexing Utility 09 Jul 2007
应用手册 Thermal Considerations Application Report 20 May 2007
用户指南 PBT5x Analog To Digital Converter Module 04 Mar 2007
用户指南 TMS320C64x+ DSP Big-Endian Library Programmer's Reference 10 Mar 2006
用户指南 TMS320C64x+ Image/Video Processing Library Programmer's Reference 10 Mar 2006
应用手册 TMS320C64x to TMS320C64x+ CPU Migration Guide (Rev. A) 20 Oct 2005
测试报告 Download: C64x+ Benchmarks (v1.00) 06 Jul 2005

设计和开发

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调试探针

TMDSEMU200-U — Spectrum Digital XDS200 USB 仿真器

Spectrum Digital XDS200 是最新 XDS200 系列 TI 处理器调试探针(仿真器)的首个模型。XDS200 系列拥有超低成本 XDS100 与高性能 XDS560v2 之间的低成本与高性能的完美平衡。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS 调试探针均支持内核和系统跟踪。

Spectrum Digital XDS200 通过 TI 20 引脚连接器(带有适合 TI 14 引脚、TI 10 引脚和 ARM 20 引脚的多个适配器)连接到目标板,而通过 USB2.0 高速连接 (480Mbps) 连接到主机 PC。要在主机 (...)

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TMDSEMU560V2STM-U — Blackhawk XDS560v2 系统跟踪 USB 仿真器

XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针(仿真器)的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件,通过捕获相关器件级信息,获得准确的总线性能活动和吞吐量,并对内核和外设进行电源管理。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS (...)

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TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 系统跟踪 USB 和以太网

XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针(仿真器)的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件,通过捕获相关器件级信息,获得准确的总线性能活动和吞吐量,并对内核和外设进行电源管理。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS (...)

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IDE、配置、编译器或调试器

CCSTUDIO Code Composer Studio 集成式开发环境 (IDE)

Code Composer Studio؜™ software is an integrated development environment (IDE) that supports TI's microcontroller (MCU) and embedded processor portfolios. Code Composer Studio software comprises a suite of tools used to develop and debug embedded applications. The software includes an (...)
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产品
汽车毫米波雷达传感器
AWR1243 76GHz 至 81GHz 高性能汽车类 MMIC AWR1443 集成 MCU 和硬件加速器的单芯片 76GHz 至 81GHz 汽车雷达传感器 AWR1642 集成 DSP 和 MCU 的单芯片 76GHz 至 81GHz 汽车雷达传感器 AWR1843 集成 DSP、MCU 和雷达加速器的单芯片 76GHz 至 81GHz 汽车雷达传感器 AWR1843AOP Single-chip 76-GHz to 81-GHz automotive radar sensor integrating antenna on package, DSP and MCU AWR2243 76GHz 至 81GHz 汽车类第二代高性能 MMIC AWR2944 适用于角雷达和远距离雷达的汽车类第二代 76GHz 至 81GHz 高性能 SoC AWR6443 Single-chip 60-GHz to 64-GHz automotive radar sensor integrating MCU and radar accelerator AWR6843 集成 DSP、MCU 和雷达加速器的单芯片 60GHz 至 64GHz 汽车雷达传感器 AWR6843AOP 集成封装天线、DSP 和 MCU 的单芯片 60GHz 至 64GHz 汽车雷达传感器
工业毫米波雷达传感器
IWR1443 集成 MCU 和硬件加速器的 76GHz 至 81GHz 单芯片毫米波传感器 IWR1642 集成 DSP 和 MCU 的 76GHz 至 81GHz 单芯片毫米波传感器 IWR1843 集成 DSP、MCU 和雷达加速器的 76GHz 至 81GHz 单芯片工业雷达传感器 IWR6443 集成 MCU 和硬件加速器的 60GHz 至 64GHz 单芯片毫米波传感器 IWR6843 集成有处理功能的 60GHz 至 64GHz 单芯片智能毫米波传感器 IWR6843AOP 具有集成封装天线 (AoP) 的单芯片 60GHz 至 64GHz 智能毫米波传感器
驱动程序或库

SPRC122 — C62x/C64x 快速运行时支持 (RTS) 库

C62x/64x FastRTS Library 是优化型浮点函数库,适用于使用 TMS320C62x 或 TMS320C64x 器件的 C 语言编程器。这些例程通常用于计算密集型实时应用,在这些应用中,提高执行速度至关重要。通过将当前的浮点库 (RTS) 函数替换为 FastRTS Library,可以在不重写现有代码的情况下大大加快执行速度。

该版本还包括 FastRTS Library 中可用函数子集的 C 语言实施。C 代码可让用户内联这些函数并获得更高性能。

特性

单精度和双精度数学函数 单精度和双精度转换函数
浮点加法 将浮点值转换为 32 位带符号整数值
将 32 位带符号整数值转换为浮点值
(...)
驱动程序或库

SPRC264 — TMS320C6000 图像库 (IMGLIB)

C5000/6000 Image Processing Library (IMGLIB) is an optimized image/video processing function library for C programmers. It includes C-callable general-purpose image/video processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
驱动程序或库

SPRC265 — TMS320C6000 DSP 库 (DSPLIB)

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
驱动程序或库

TELECOMLIB — 用于 TMS320C64x+ 和 TMS320C55x 处理器的电信和媒体库 - FAXLIB、VoLIB 和 AEC/AER

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)
仿真模型

C6424 ZWT IBIS Model (Rev. C)

SPRM240C.ZIP (267 KB) - IBIS Model
仿真模型

C6424 ZDU IBIS Model (Rev. B)

SPRM241B.ZIP (267 KB) - IBIS Model
仿真模型

C6424 ZDU BSDL Model (Rev. A)

SPRM250A.ZIP (10 KB) - BSDL Model
仿真模型

C6424 ZWT BSDL Model (Rev. A)

SPRM251A.ZIP (10 KB) - BSDL Model
设计工具

PROCESSORS-3P-SEARCH — Arm-based MPU, arm-based MCU and DSP third-party search tool

TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)
封装 引脚数 下载
BGA (ZDU) 376 了解详情
NFBGA (ZWT) 361 了解详情

订购和质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 认证摘要
  • 持续可靠性监测

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支持与培训

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