TMS320DM6437
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- High-Performance Digital Media Processor (DM6437)
- 2.5-, 2-, 1.67, 1.51-, 1.43-ns Instruction Cycle Time
- 400-, 500-, 600-, 660-, 700-MHz C64x+™ Clock Rate
- Eight 32-Bit C64x+ Instructions/Cycle
- 3200, 4000, 4800, 5280, 5600 MIPS
- Fully Software-Compatible With C64x
- Commercial and Automotive (Q or S suffix) Grades
- Low-Power Device (L suffix)
- VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word VLIW) TMS320C64x+™ DSP Core
- Eight Highly Independent Functional Units With VelociTI.2 Extensions:
- Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
- Two Multipliers Support Four 16 × 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 × 8-Bit Multiplies (16-Bit Results) per Clock Cycle
- Eight Highly Independent Functional Units With VelociTI.2 Extensions:
- Load-Store Architecture With Non-Aligned Support
- 64 32-Bit General-Purpose Registers
- Instruction Packing Reduces Code Size
- All Instructions Conditional
- Additional C64x+™ Enhancements
- Protected Mode Operation
- Exceptions Support for Error Detection and Program Redirection
- Hardware Support for Modulo Loop Auto-Focus Module Operation
- C64x+ Instruction Set Features
- Byte-Addressable (8-/16-/32-/64-Bit Data)
- 8-Bit Overflow Protection
- Bit-Field Extract, Set, Clear
- Normalization, Saturation, Bit-Counting
- VelociTI.2 Increased Orthogonality
- C64x+ Extensions
- Compact 16-bit Instructions
- Additional Instructions to Support Complex Multiplies
- C64x+ L1/L2 Memory Architecture
- 256K-Bit (32K-Byte) L1P Program RAM/Cache [Flexible Allocation]
- 640K-Bit (80K-Byte) L1D Data RAM/Cache [Flexible Allocation]
- 1M-Bit (128K-Byte) L2 Unified Mapped RAM/Cache [Flexible Allocation]
- Supports Little Endian Mode Only
- Video Processing Subsystem (VPSS)
- Front End Provides:
- CCD and CMOS Imager Interface
- BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
- Preview Engine for Real-Time Image Processing
- Glueless Interface to Common Video Decoders
- Histogram Module
- Auto-Exposure, Auto-White Balance and Auto-Focus Module
- Resize Engine
- Resize Images From 1/4× to 4×
- Separate Horizontal/Vertical Control
- Back End Provides:
- Hardware On-Screen Display (OSD)
- Four 54-MHz DACs for a Combination of
- Composite NTSC/PAL Video
- Luma/Chroma Separate Video (S-video)
- Component (YPbPr or RGB) Video (Progressive)
- Digital Output
- 8-/16-bit YUV or up to 24-Bit RGB
- HD Resolution
- Up to 2 Video Windows
- Front End Provides:
- External Memory Interfaces (EMIFs)
- 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8-V I/O)
- Supports up to 333-MHz (data rate) Bus and Interfaces With DDR2-400 SDRAM
- Asynchronous 8-Bit Wide EMIF (EMIFA) With up to 64M-Byte Address Reach
- Flash Memory Interfaces
- NOR (8-Bit-Wide Data)
- NAND (8-Bit-Wide Data)
- Flash Memory Interfaces
- 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8-V I/O)
- Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
- Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
- One 64-Bit Watch Dog Timer
- Two UARTs (One with RTS and CTS Flow Control)
- Master/Slave Inter-Integrated Circuit (I2C Bus×)
- Two Multichannel Buffered Serial Ports (McBSPs)
- I2S and TDM
- AC97 Audio Codec Interface
- SPI
- Standard Voice Codec Interface (AIC12)
- Telecom Interfaces - ST-Bus, H-100
- 128 Channel Mode
- Multichannel Audio Serial Port (McASP0)
- Four Serializers and SPDIF (DIT) Mode
- 16-Bit Host-Port Interface (HPI)
- High-End CAN Controller (HECC)
- 32-Bit 33-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface
- 10/100 Mb/s Ethernet MAC (EMAC)
- IEEE 802.3 Compliant
- Supports Media Independent Interface (MII)
- Management Data I/O (MDIO) Module
- VLYNQ™ Interface (FPGA Interface)
- Three Pulse Width Modulator (PWM) Outputs
- On-Chip ROM Bootloader
- Individual Power-Savings Modes
- Flexible PLL Clock Generators
- IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible
- Up to 111 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
- Packages:
- 361-Pin Pb-Free PBGA Package (ZWT Suffix), 0.8-mm Ball Pitch
- 376-Pin Plastic BGA Package (ZDU Suffix), 1.0-mm Ball Pitch
- 0.09-µm/6-Level Cu Metal Process (CMOS)
- 3.3-V and 1.8-V I/O, 1.2-V Internal (-7/-6/-5/-4/-L/-Q6/-5Q/-4Q)
- 3.3-V and 1.8-V I/O, 1.05-V Internal (-7/-6/-5/-4/-L/-Q5)
- Applications
- Digital Media
- Networked Media Encode/Decode
- Video Imaging
All trademarks are the property of their respective owners.
The TMS320C64x+™ DSPs (including the TMS320DM6437 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The DM6437 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform. The C64x™ DSPs support added functionality and have an expanded instruction set from previous devices.
Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively.
With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732).
The DM6437 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6437 core uses a two-level cache-based architecture. The Level 1 program memory/cache (L1P) consists of a 256K-bit memory space that can be configured as mapped memory or direct mapped cache, and the Level 1 data (L1D) consists of a 640K-bit memory space-384K-bit of which is mapped memory and 256K-bit of which can be configured as mapped memory or 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 1M-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.
The peripheral set includes: 2 configurable video ports; a 10/100 Mb/s Ethernet MAC (EMAC) with a management data input/output (MDIO) module; a 4-bit transmit, 4-bit receive VLYNQ interface; an inter-integrated circuit (I2C) Bus interface; two multichannel buffered serial ports (McBSPs); a multichannel audio serial port (McASP0) with 4 serializers; 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; a user-configurable 16-bit host-port interface (HPI); up to 111-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 2 UARTs with hardware handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; 1 high-end controller area network (CAN) controller [HECC]; 1 peripheral component interconnect (PCI) [33 MHz]; and 2 glueless external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2.
The DM6437 device includes a Video Processing Subsystem (VPSS) with two configurable video/imaging peripherals: 1 Video Processing Front-End (VPFE) input used for video capture, 1 Video Processing Back-End (VPBE) output.
The Video Processing Front-End (VPFE) is comprised of a CCD Controller (CCDC), a Preview Engine (Previewer), Histogram Module, Auto-Exposure/White Balance/Focus Module (H3A), and Resizer. The CCDC is capable of interfacing to common video decoders, CMOS sensors, and Charge Coupled Devices (CCDs). The Previewer is a real-time image processing engine that takes raw imager data from a CMOS sensor or CCD and converts from an RGB Bayer Pattern to YUV422. The Histogram and H3A modules provide statistical information on the raw color data for use by the DM6437. The Resizer accepts image data for separate horizontal and vertical resizing from 1/4x to 4x in increments of 256/N, where N is between 64 and 1024.
The Video Processing Back-End (VPBE) is comprised of an On-Screen Display Engine (OSD) and a Video Encoder (VENC). The OSD engine is capable of handling 2 separate video windows and 2 separate OSD windows. Other configurations include 2 video windows, 1 OSD window, and 1 attribute window allowing up to 8 levels of alpha blending. The VENC provides four analog DACs that run at 54 MHz, providing a means for composite NTSC/PAL video, S-Video, and/or Component video output. The VENC also provides up to 24 bits of digital output to interface to RGB888 devices. The digital output is capable of 8/16-bit BT.656 output and/or CCIR.601 with separate horizontal and vertical syncs.
The Ethernet Media Access Controller (EMAC) provides an efficient interface between the DM6437 and the network. The DM6437 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.
The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system.
The I2C and VLYNQ ports allow DM6437 to easily control peripheral devices and/or communicate with host processors.
The high-end controller area network (CAN) controller [HECC] module provides a network protocol in a harsh environment to communicate serially with other controllers, typically in automotive applications.
The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.
The DM6437 has a complete set of development tools. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code
No design support from TI available
This product does not have ongoing design support from TI for new projects, such as new content or software updates. If available, you will find relevant collateral, software and tools in the product folder. You can also search for archived information in the TI E2ETM support forums.
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所有 XDS 调试探针在所有具有嵌入式跟踪缓冲器 (ETB) 的 ARM 和 DSP 处理器中均支持内核和系统跟踪。对于引脚上的跟踪,需要 XDS560v2 PRO TRACE。
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XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件,通过捕获相关器件级信息,获得准确的总线性能活动和吞吐量,并对内核和外设进行电源管理。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS (...)
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DEMOAPP-DM6437 — 演示 - DM6437 应用示例和演示代码
- Click GET SOFTWARE to access Application Demo and Documentation, based on the DM6437 EVM (evaluation module).
SPRC122 — C62x/C64x 快速运行时支持 (RTS) 库
该版本还包括 FastRTS Library 中可用函数子集的 C 语言实施。C 代码可让用户内联这些函数并获得更高性能。
特性
单精度和双精度数学函数 | 单精度和双精度转换函数 |
浮点加法 | 将浮点值转换为 32 位带符号整数值 |
将 32 位带符号整数值转换为浮点值 | |
(...) |
TELECOMLIB — 用于 TMS320C64x+ 和 TMS320C55x 处理器的电信和媒体库 - FAXLIB、VoLIB 和 AEC/AER
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其他信息:
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- DSP 与 ARM 软件和硬件开发套件 - 所有可用的 SDK
- 如何将编解码器集成至 DVSDK
- DaVinci 和 OMAP 软件入门教程
- 基于 TI C64x+ 的器件的编解码器性能测量
- TI E2E™ 社区
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PROCESSORS-3P-SEARCH — 基于 Arm® 的 MPU、基于 Arm 的 MCU 和 DSP 第三方搜索工具
搜索工具按产品类型划分为以下类别:
- 工具包括 IDE/编译器、调试和跟踪、仿真和建模软件以及闪存编程器。
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- 应用软件是指应用特定的软件,包括在 TI 处理器上运行的中间件和库。
- SoM 是模块上系统解决方案
封装 | 引脚数 | 下载 |
---|---|---|
BGA (ZDU) | 376 | 了解详情 |
NFBGA (ZWT) | 361 | 了解详情 |
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