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  • High-Performance Digital Media Processor (TMS320DM642)
    • 2-, 1.67-, 1.39-ns Instruction Cycle Time
    • 500-, 600-, 720-MHz Clock Rate
    • Eight 32-Bit Instructions/Cycle
    • 4000, 4800, 5760 MIPS
    • Fully Software-Compatible With C64x™
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word VLIW) TMS320C64x™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2™ Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2™ Increased Orthogonality
  • L1/L2 Memory Architecture
    • 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped)
    • 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
    • 2M-Bit (256K-Byte) L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
  • Endianess: Little Endian, Big Endian
  • 64-Bit External Memory Interface (EMIF)
    • Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
    • 1024M-Byte Total Addressable External Memory Space
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • 10/100 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Media Independent Interface (MII)
    • 8 Independent Transmit (TX) Channels and 1 Receive (RX) Channel
  • Management Data Input/Output (MDIO)
  • Three Configurable Video Ports
    • Providing a Glueless I/F to Common Video Decoder and Encoder Devices
    • Supports Multiple Resolutions and Video Standards
  • VCXO Interpolated Control Port (VIC)
    • Supports Audio/Video Synchronization
  • Host-Port Interface (HPI) [32-/16-Bit]
  • 32-Bit/66-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface Conforms to PCI Specification 2.2
  • Multichannel Audio Serial Port (McASP)
    • Eight Serial Data Pins
    • Wide Variety of I2S and Similar Bit Stream Format
    • Integrated Digital Audio I/F Transmitter Supports S/PDIF, IEC60958-1, AES-3, CP-430 Formats
  • Inter-Integrated Circuit (I2C) Bus™
  • Two Multichannel Buffered Serial Ports
  • Three 32-Bit General-Purpose Timers
  • Sixteen General-Purpose I/O (GPIO) Pins
  • Flexible PLL Clock Generator
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • 548-Pin Ball Grid Array (BGA) Package (GDK and ZDK Suffixes), 0.8-mm Ball Pitch
  • 548-Pin Ball Grid Array (BGA) Package (GNZ and ZNZ Suffixes), 1.0-mm Ball Pitch
  • 0.13-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V I/O, 1.2-V Internal (-500)
  • 3.3-V I/O, 1.4-V Internal (A-500, A-600, -600, -720)

C64x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
TMS320C6000, and C6000 are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.

  • High-Performance Digital Media Processor (TMS320DM642)
    • 2-, 1.67-, 1.39-ns Instruction Cycle Time
    • 500-, 600-, 720-MHz Clock Rate
    • Eight 32-Bit Instructions/Cycle
    • 4000, 4800, 5760 MIPS
    • Fully Software-Compatible With C64x™
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word VLIW) TMS320C64x™ DSP Core
    • Eight Highly Independent Functional Units With VelociTI.2™ Extensions:
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2™ Increased Orthogonality
  • L1/L2 Memory Architecture
    • 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped)
    • 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
    • 2M-Bit (256K-Byte) L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
  • Endianess: Little Endian, Big Endian
  • 64-Bit External Memory Interface (EMIF)
    • Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
    • 1024M-Byte Total Addressable External Memory Space
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • 10/100 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Media Independent Interface (MII)
    • 8 Independent Transmit (TX) Channels and 1 Receive (RX) Channel
  • Management Data Input/Output (MDIO)
  • Three Configurable Video Ports
    • Providing a Glueless I/F to Common Video Decoder and Encoder Devices
    • Supports Multiple Resolutions and Video Standards
  • VCXO Interpolated Control Port (VIC)
    • Supports Audio/Video Synchronization
  • Host-Port Interface (HPI) [32-/16-Bit]
  • 32-Bit/66-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface Conforms to PCI Specification 2.2
  • Multichannel Audio Serial Port (McASP)
    • Eight Serial Data Pins
    • Wide Variety of I2S and Similar Bit Stream Format
    • Integrated Digital Audio I/F Transmitter Supports S/PDIF, IEC60958-1, AES-3, CP-430 Formats
  • Inter-Integrated Circuit (I2C) Bus™
  • Two Multichannel Buffered Serial Ports
  • Three 32-Bit General-Purpose Timers
  • Sixteen General-Purpose I/O (GPIO) Pins
  • Flexible PLL Clock Generator
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • 548-Pin Ball Grid Array (BGA) Package (GDK and ZDK Suffixes), 0.8-mm Ball Pitch
  • 548-Pin Ball Grid Array (BGA) Package (GNZ and ZNZ Suffixes), 1.0-mm Ball Pitch
  • 0.13-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V I/O, 1.2-V Internal (-500)
  • 3.3-V I/O, 1.4-V Internal (A-500, A-600, -600, -720)

C64x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
All trademarks are the property of their respective owners.
TMS320C6000, and C6000 are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.

The TMS320C64x™ DSPs (including the TMS320DM642 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320DM642 (DM642) device is based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.

With performance of up to 5760 million instructions per second (MIPS) at a clock rate of 720 MHz, the DM642 device offers cost-effective solutions to high-performance DSP programming challenges. The DM642 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x™ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs)- with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units include new instructions to accelerate the performance in video and imaging applications and extend the parallelism of the VelociTI™ architecture. The DM642 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2880 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 5760 MMACS. The DM642 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000™ DSP platform devices.

The DM642 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 2-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: three configurable video ports; a 10/100 Mb/s Ethernet MAC (EMAC); a management data input/output (MDIO) module; a VCXO interpolated control port (VIC); one multichannel buffered audio serial port (McASP0); an inter-integrated circuit (I2C) Bus module; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component interconnect (PCI); a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 64-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals.

The DM642 device has three configurable video port peripherals (VP0, VP1, and VP2). These video port peripherals provide a glueless interface to common video decoder and encoder devices. The DM642 video port peripherals support multiple resolutions and video standards (e. g., CCIR601, ITU-BT.656, BT.1120, SMPTE 125M, 260M, 274M, and 296M).

These three video port peripherals are configurable and can support either video capture and/or video display modes. Each video port consists of two channels - A and B with a 5120-byte capture/display buffer that is splittable between the two channels.

For more details on the Video Port peripherals, see the TMS320C64x Video Port/VXCO Interpolated Control (VIC) Port Reference Guide (literature number SPRU629).

The McASP0 port supports one transmit and one receive clock zone, with eight serial data pins which can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The DM642 has sufficient bandwidth to support all 8 serial data pins transmitting a 192-kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format.

In addition, the McASP0 transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields.

McASP0 also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range.

The VXCO interpolated control port (VIC) provides digital-to-analog conversion with resolution from 9-bits to up to 16-bits. The output of the VIC is a single bit interpolated D/A output. For more details on the VIC port, see the TMS320C64x Video Port/VXCO Interpolated Control (VIC) Port Reference Guide (literature number SPRU629).

The ethernet media access controller (EMAC) provides an efficient interface between the DM642 DSP core processor and the network. The DM642 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex, with hardware flow control and quality of service (QOS) support. The DM642 EMAC makes use of a custom interface to the DSP core that allows efficient data transmission and reception. For more details on the EMAC, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628).

The management data input/output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the DSP, the MDIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the DSP, allowing the DSP to poll the link status of the device without continuously performing costly MDIO accesses. For more details on the MDIO, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628).

The I2C0 port on the TMS320DM642 allows the DSP to easily control peripheral devices, boot from a serial EEPROM, and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices.

The TMS320C64x™ DSPs (including the TMS320DM642 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320DM642 (DM642) device is based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.

With performance of up to 5760 million instructions per second (MIPS) at a clock rate of 720 MHz, the DM642 device offers cost-effective solutions to high-performance DSP programming challenges. The DM642 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x™ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs)- with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units include new instructions to accelerate the performance in video and imaging applications and extend the parallelism of the VelociTI™ architecture. The DM642 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2880 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 5760 MMACS. The DM642 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000™ DSP platform devices.

The DM642 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 2-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: three configurable video ports; a 10/100 Mb/s Ethernet MAC (EMAC); a management data input/output (MDIO) module; a VCXO interpolated control port (VIC); one multichannel buffered audio serial port (McASP0); an inter-integrated circuit (I2C) Bus module; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component interconnect (PCI); a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 64-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals.

The DM642 device has three configurable video port peripherals (VP0, VP1, and VP2). These video port peripherals provide a glueless interface to common video decoder and encoder devices. The DM642 video port peripherals support multiple resolutions and video standards (e. g., CCIR601, ITU-BT.656, BT.1120, SMPTE 125M, 260M, 274M, and 296M).

These three video port peripherals are configurable and can support either video capture and/or video display modes. Each video port consists of two channels - A and B with a 5120-byte capture/display buffer that is splittable between the two channels.

For more details on the Video Port peripherals, see the TMS320C64x Video Port/VXCO Interpolated Control (VIC) Port Reference Guide (literature number SPRU629).

The McASP0 port supports one transmit and one receive clock zone, with eight serial data pins which can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The DM642 has sufficient bandwidth to support all 8 serial data pins transmitting a 192-kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format.

In addition, the McASP0 transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields.

McASP0 also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range.

The VXCO interpolated control port (VIC) provides digital-to-analog conversion with resolution from 9-bits to up to 16-bits. The output of the VIC is a single bit interpolated D/A output. For more details on the VIC port, see the TMS320C64x Video Port/VXCO Interpolated Control (VIC) Port Reference Guide (literature number SPRU629).

The ethernet media access controller (EMAC) provides an efficient interface between the DM642 DSP core processor and the network. The DM642 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex, with hardware flow control and quality of service (QOS) support. The DM642 EMAC makes use of a custom interface to the DSP core that allows efficient data transmission and reception. For more details on the EMAC, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628).

The management data input/output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the DSP, the MDIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the DSP, allowing the DSP to poll the link status of the device without continuously performing costly MDIO accesses. For more details on the MDIO, see the TMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide (literature number SPRU628).

The I2C0 port on the TMS320DM642 allows the DSP to easily control peripheral devices, boot from a serial EEPROM, and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices.

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This data sheet applies to both  TMS320DM642 and  TMS320DM642Q

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类型 项目标题 下载最新的英语版本 日期
* 数据表 TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor 数据表 (Rev. N) 12 Oct 2010
* 勘误表 TMS320DM642 DSP Silicon Errata, Silicon Revisions 2.0, 1.2, 1.1, 1.0 (Rev. K) 04 Feb 2010
技术文章 Difficult to see. Always in motion is the future 04 Jan 2016
技术文章 Announcing the new entry-level Sitara processor 09 Dec 2015
技术文章 Automotive Surround View Technology trends 31 Aug 2015
技术文章 Where are DSPs used? What makes them so good at math? How do they work with Open APIs? 06 Aug 2015
用户指南 Emulation and Trace Headers Technical Reference Manual (Rev. I) 09 Aug 2012
用户指南 TMS320C64x DSP Video Port/ VCXO Interpolated Control (VIC) Port Reference Guide (Rev. G) 12 Nov 2010
用户指南 TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (Rev. J) 30 Jul 2010
应用手册 Interfacing a CMOS Sensor to the TMS320DM642 Using Raw Capture Mode (Rev. A) 27 Jan 2010
用户指南 TMS320C6000 DSP Peripherals Overview Reference Guide (Rev. Q) 02 Jul 2009
用户指南 TMS320C6000 DSP Multichannel Audio Serial Port (McASP) Reference Guide (Rev. J) 20 Nov 2008
应用手册 TMS320DM642 to TMS32DM6467 Migration 17 Nov 2008
应用手册 Software Migration From TMS320DM642 to TMS320DM648/DM6437 19 Aug 2008
应用手册 TMS320C6000 EMIF-to-External SDRAM Interface (Rev. E) 04 Sep 2007
应用手册 TMS320DM642 to TMS320DM6437 Migration Guide 29 Jun 2007
应用手册 Migrating from TMS320DM642/3/1/0 to the TMS320DM648/7 Device 07 Jun 2007
应用手册 Thermal Considerations Application Report 20 May 2007
用户指南 TMS320C6000 DSP External Memory Interface (EMIF) Reference Guide (Rev. E) 11 Apr 2007
更多文献资料 TMS320C6000 DSP TCP/IP Stack Software (Rev. C) 04 Apr 2007
用户指南 TMS320C6000 DSP Inter-Integrated Circuit (I2C) Module Reference Guide (Rev. D) 26 Mar 2007
用户指南 TMS320C6000 DSP Peripheral Component Interconnect (PCI) Reference Guide (Rev. C) 25 Jan 2007
用户指南 TMS320C6000 DSP Multichannel Buffered Serial Port ( McBSP) Reference Guide (Rev. G) 14 Dec 2006
用户指南 TMS320C6000 DSP Enhanced Direct Memory Access (EDMA) Controller Reference Guide (Rev. C) 15 Nov 2006
用户指南 TMS320C64x DSP Two Level Internal Memory Reference Guide (Rev. C) 28 Feb 2006
用户指南 TMS320C6000 DSP Host-Post Interface (HPI) Reference Guide (Rev. C) 01 Jan 2006
用户指南 TMS320C6000 DSP 外设概述参考指南 (Rev. H) 下载最新的英文版本 (Rev.Q) 07 Nov 2005
应用手册 TMS320DM642 Hardware Designer's Resource Guide (Rev. A) 25 Oct 2005
应用手册 TMS320C64x to TMS320C64x+ CPU Migration Guide (Rev. A) 20 Oct 2005
更多文献资料 TMS320DM64x Digital Media Processors - Product Bulletin (Rev. C) 30 Aug 2005
用户指南 TMS320C6000 DSP Power-Down Logic and Modes Reference Guide (Rev. C) 01 Mar 2005
应用手册 TMS320DM64x Power Consumption Summary (Rev. F) 18 Feb 2005
用户指南 TMS320C6000 DSP 32-bit Timer Reference Guide (Rev. B) 25 Jan 2005
应用手册 Video Scaling Example on the DM642 EVM 27 Sep 2004
应用手册 Driver Examples on the DM642 EVM (Rev. A) 31 Aug 2004
应用手册 Use and Handling of Semiconductor Packages With ENIG Pad Finishes 31 Aug 2004
用户指南 TMS320C6000 Chip Support Library API Reference Guide (Rev. J) 13 Aug 2004
应用手册 JPEG Motion on the DM642 EVM (Rev. A) 16 Jul 2004
应用手册 JPEG Netcam on the DM642 EVM (Rev. A) 16 Jul 2004
应用手册 JPEG Netcam2 on the DM642 EVM (Rev. A) 16 Jul 2004
应用手册 JPEG Network on the DM642 EVM (Rev. A) 16 Jul 2004
应用手册 The TMS320DM642 Video Port Mini-Driver for TVP5146 and TVP5150 decoder 16 Jul 2004
应用手册 Interfacing an LCD Controller to a DM642 Video Port (Rev. B) 03 May 2004
应用手册 使用 DM642 DSP 和 THS8200 驱动器的高分辨率视频 (Rev. A) 03 May 2004
应用手册 TMS320C6000 Tools: Vector Table and Boot ROM Creation (Rev. D) 26 Apr 2004
应用手册 TMS320C6000 Board Design: Considerations for Debug (Rev. C) 21 Apr 2004
用户指南 TMS320C6000 DSP EMAC/MDIO Module Reference Guide (Rev. A) 26 Mar 2004
用户指南 TMS320C6000 DSP General-Purpose Input/Output (GPIO) Reference Guide (Rev. A) 25 Mar 2004
应用手册 TMS320C6000 McBSP Initialization (Rev. C) 08 Mar 2004
应用手册 TMS320C6000 EDMA IO Scheduling and Performance 05 Mar 2004
更多文献资料 Video/Imaging Benchmarks (Rev. A) 01 Mar 2004
更多文献资料 Video Security over IP (VSIP) Development Platform Product Bulletin 05 Nov 2003
应用手册 On-Screen-Display Driver Examples For DM642 EVM Demo Software Release Report 14 Oct 2003
应用手册 Adapting the SPRA904 Motion Detection Application Report to the DM642 EVM 10 Oct 2003
应用手册 An Audio Example Using Reference Frameworks on the DM642 EVM 31 Aug 2003
应用手册 Audio Demonstration on the DM642 EVM 31 Aug 2003
应用手册 Audio Echo on the DM642 EVM 31 Aug 2003
应用手册 H.263 Loop Back on the DM642 EVM 31 Aug 2003
应用手册 JPEG Loop Back on the DM642 EVM 31 Aug 2003
应用手册 MPEG-2 Encoder on the DM642 EVM 31 Aug 2003
应用手册 MPEG-2 High Definition Decoder on the DM642 EVM 31 Aug 2003
应用手册 MPEG-2 Loop Back on the DM642 EVM 31 Aug 2003
应用手册 The TMS320DM642 Video Port Mini-Driver (Rev. A) 14 Aug 2003
用户指南 TMS320C6000 DSP Designing for JTAG Emulation Reference Guide 31 Jul 2003
更多文献资料 TMS320DM64x Digital Media Development Tools Product Bulletin 31 Jul 2003
应用手册 A DSP/BIOS AIC23 Codec Device Driver for the TMS320DM642 EVM 30 Jun 2003
EVM 用户指南 TMS320DM642 EVM OSD FPGA User's Guide 26 Jun 2003
应用手册 TMS320DM642 EVM Daughtercard Specification Revision 1.0 25 Jun 2003
用户指南 TMS320C6000 DSP Cache User's Guide (Rev. A) 05 May 2003
应用手册 Using IBIS Models for Timing Analysis (Rev. A) 15 Apr 2003
用户指南 TMS320DM642 Technical Overview 13 Sep 2002
应用手册 TMS320C6000 McBSP Interface to an ST-BUS Device (Rev. B) 04 Jun 2002
应用手册 TMS320C6000 HPI to PCI Interfacing Using the PLX PCI9050 (Rev. C) 17 Apr 2002
应用手册 TMS320C6000 Board Design for JTAG (Rev. C) 02 Apr 2002
应用手册 TMS320C6000 EMIF to External Flash Memory (Rev. A) 13 Feb 2002
应用手册 Cache Usage in High-Performance DSP Applications with the TMS320C64x 13 Dec 2001
应用手册 Using a TMS320C6000 McBSP for Data Packing (Rev. A) 31 Oct 2001
应用手册 TMS320C6000 Enhanced DMA: Example Applications (Rev. A) 24 Oct 2001
应用手册 Interfacing theTMS320C6000 EMIFto a PCI Bus Using the AMCC S5933 PCI Controller (Rev. A) 30 Sep 2001
应用手册 TMS320C6000 Host Port to MC68360 Interface (Rev. A) 30 Sep 2001
应用手册 TMS320C6000 EMIF to External Asynchronous SRAM Interface (Rev. A) 31 Aug 2001
应用手册 TMS320C6000 Host Port to the i80960 Microprocessors Interface (Rev. A) 31 Aug 2001
应用手册 Using the TMS320C6000 McBSP as a High Speed Communication Port (Rev. A) 31 Aug 2001
应用手册 TMS320C6000 System Clock Circuit Example (Rev. A) 15 Aug 2001
应用手册 TMS320C6000 McBSP to Voice Band Audio Processor (VBAP) Interface (Rev. A) 23 Jul 2001
应用手册 TMS320C6000 McBSP: AC'97 Codec Interface (TLV320AIC27) (Rev. A) 10 Jul 2001
应用手册 TMS320C6000 McBSP: Interface to SPI ROM (Rev. C) 30 Jun 2001
应用手册 TMS320C6000 Host Port to MPC860 Interface (Rev. A) 21 Jun 2001
应用手册 TMS320C6000 McBSP: IOM-2 Interface (Rev. A) 21 May 2001
用户指南 TMS320C64x Technical Overview (Rev. B) 30 Jan 2001
应用手册 Circular Buffering on TMS320C6000 (Rev. A) 12 Sep 2000
应用手册 TMS320C6000 McBSP as a TDM Highway (Rev. A) 11 Sep 2000
应用手册 TMS320C6000 u-Law and a-Law Companding with Software or the McBSP 02 Feb 2000
应用手册 General Guide to Implement Logarithmic and Exponential Operations on Fixed-Point 31 Jan 2000
应用手册 TMS320C6000 C Compiler: C Implementation of Intrinsics 07 Dec 1999
应用手册 TMS320C6000 McBSP: I2S Interface 08 Sep 1999

设计和开发

如需其他信息或资源,请查看下方列表,点击标题即可进入详情页面。

调试探针

TMDSEMU200-U — Spectrum Digital XDS200 USB 仿真器

Spectrum Digital XDS200 是最新 XDS200 系列 TI 处理器调试探针(仿真器)的首个模型。XDS200 系列拥有超低成本 XDS100 与高性能 XDS560v2 之间的低成本与高性能的完美平衡。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS 调试探针均支持内核和系统跟踪。

Spectrum Digital XDS200 通过 TI 20 引脚连接器(带有适合 TI 14 引脚、TI 10 引脚和 ARM 20 引脚的多个适配器)连接到目标板,而通过 USB2.0 高速连接 (480Mbps) 连接到主机 PC。要在主机 (...)

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调试探针

TMDSEMU560V2STM-U — Blackhawk XDS560v2 系统跟踪 USB 仿真器

XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针(仿真器)的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件,通过捕获相关器件级信息,获得准确的总线性能活动和吞吐量,并对内核和外设进行电源管理。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS (...)

TI.com 無法提供
调试探针

TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 系统跟踪 USB 和以太网

XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针(仿真器)的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件,通过捕获相关器件级信息,获得准确的总线性能活动和吞吐量,并对内核和外设进行电源管理。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS (...)

TI.com 無法提供
驱动程序或库

FAXLIB 用于 C66x、C64x+ 和 C55x 处理器的传真库 (FAXLIB)

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

支持的产品和硬件

支持的产品和硬件

产品
基于 Arm 的处理器
66AK2G12 高性能多核 DSP+Arm - 1 个 Arm A15 内核、1 个 C66x DSP 内核
数字信号处理器 (DSP)
DM505 适用于视觉分析的 SoC,采用 15mm 封装 SM320C6201-EP 增强型产品 C6201 定点 DSP SM320C6415 军用级 C64x 定点 DSP SM320C6415-EP 增强型产品 C6415 定点 DSP SM320C6424-EP 增强型产品 C6424 定点 DSP SM320C6455-EP 增强型产品 C6455 定点 DSP SM320C6472-HIREL 高可靠性产品 6 核 C6472 定点 DSP SM320C6678-HIREL 高可靠性产品高性能 8 核 C6678 定点和浮点 DSP SM320C6701 用于军事应用的单核 C67x 浮点 DSP - 高达 167MHz SM320C6701-EP 增强型产品 C6701 浮点 DSP SM320C6711D-EP 增强型产品 C6711D 浮点 DSP SM320C6712D-EP 增强型产品 C6712D DSP SM320C6713B-EP 增强型产品 C6713 浮点 DSP SM320C6727B 军用级 C6727B 浮点 DSP SM320C6727B-EP 增强型产品 C6727 浮点 DSP SM320DM642-HIREL 高可靠性产品数字媒体 DM642 DSP SM32C6416T-EP 增强型产品 C6416T 定点 DSP SMJ320C6201B 军用定点数字信号处理器 SMJ320C6203 军用级 C62x 定点 DSP - 陶瓷封装 SMJ320C6415 军用级 C64x 定点 DSP - 陶瓷封装 SMJ320C6701 军用级 C67x 浮点 DSP - 陶瓷封装 SMJ320C6701-SP 航天级 C6701 浮点 DSP - 抗辐射 V 类、采用陶瓷封装 SMV320C6727B-SP 航天级 C6727B 浮点 DSP - 抗辐射 V 类、采用陶瓷封装 TMS320C5517 低功耗 C55x 定点 DSP- 高达 200MHz、USB、LCD 接口、FFT HWA、SAR ADC TMS320C5532 低功耗 C55x 定点 DSP- 高达 100MHz TMS320C5533 低功耗 C55x 定点 DSP- 高达 100MHz、USB TMS320C5534 低功耗 C55x 定点 DSP- 高达 100MHz、USB、LCD 接口 TMS320C5535 低功耗 C55x 定点 DSP- 高达 100MHz、USB、LCD 接口、FFT HWA、SAR ADC TMS320C6201 定点数字信号处理器 TMS320C6202 定点数字信号处理器 TMS320C6202B C62x 定点 DSP- 高达 300MHz、384KB TMS320C6203B C62x 定点 DSP- 高达 300MHz、896KB TMS320C6204 定点数字信号处理器 TMS320C6205 定点数字信号处理器 TMS320C6211B C62x 定点 DSP- 高达 167MHz TMS320C6411 C64x 定点 DSP- 高达 300MHz、McBSP TMS320C6414 C64x 定点 DSP- 高达 720MHz、McBSP TMS320C6415 C64x 定点 DSP- 高达 720MHz、McBSP、PCI TMS320C6416 C64x 定点 DSP- 高达 720MHz、McBSP、PCI、VCP/TCP TMS320C6421Q C64x+ 定点 DSP- 高达 600MHz、8 位 EMIFA、16 位 DDR2 TMS320C6424Q C64x+ 定点 DSP- 高达 600MHz、16/8 位 EMIFA、32/16 位 DDR2 TMS320C6454 C64x+ 定点 DSP - 高达 1GHz、64 位 EMIFA、32/16 位 DDR2、1Gbps 以太网 TMS320C6457 通信基础设施数字信号处理器 TMS320C6701 C67x 浮点 DSP- 高达 167MHz、McBSP TMS320C6711D C67x 浮点 DSP- 高达 250MHz、McBSP、32 位 EMIFA TMS320C6712D C67x 浮点 DSP- 高达 150MHz、McBSP、16 位 EMIFA TMS320C6720 C67x 浮点 DSP - 200MHz、McASP、16 位 EMIFA TMS320C6722B C67x 浮点 DSP- 高达 250MHz、McASP、16 位 EMIFA TMS320C6726B C67x 浮点 DSP- 高达 266MHz、McASP、16 位 EMIFA TMS320C6727 C67x 浮点 DSP- 高达 250MHz、McASP、32 位 EMIFA TMS320C6727B C67x 浮点 DSP- 高达 350MHz、McASP、32 位 EMIFA TMS320C6743 低功耗 C674x 浮点 DSP- 375MHz TMS320C6745 低功耗 C674x 浮点 DSP- 456MHz、QFP TMS320C6747 低功耗 C674x 浮点 DSP- 456MHz、PBGA TMS320DM642Q 视频/成像定点数字信号处理器 TMS320DM6431Q 数字媒体处理器,性能高达 2400MIPS、300MHz 时钟速率 TMS320DM6435Q 数字媒体处理器,性能高达 4800MIPS、600MHz 时钟速率、1 个 McASP、1 个 McBSP TMS320DM6437Q 数字媒体处理器,性能高达 4800MIPS、600MHz 时钟速率、1 个 McASP、2 个 McBSP TMS320DM6441 达芬奇数字媒体片上系统 TMS320DM6467T 数字媒体片上系统 TMS320DM647 数字媒体处理器
下载选项
驱动程序或库

AEC-AER 用于 TI C64x+、C674x、C55x 和 Cortex(tm)A8 处理器的回声抵消/消除 - 即刻可得

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

支持的产品和硬件

支持的产品和硬件

产品
基于 Arm 的处理器
66AK2G12 高性能多核 DSP+Arm - 1 个 Arm A15 内核、1 个 C66x DSP 内核
数字信号处理器 (DSP)
DM505 适用于视觉分析的 SoC,采用 15mm 封装 SM320C6201-EP 增强型产品 C6201 定点 DSP SM320C6415 军用级 C64x 定点 DSP SM320C6415-EP 增强型产品 C6415 定点 DSP SM320C6424-EP 增强型产品 C6424 定点 DSP SM320C6455-EP 增强型产品 C6455 定点 DSP SM320C6472-HIREL 高可靠性产品 6 核 C6472 定点 DSP SM320C6678-HIREL 高可靠性产品高性能 8 核 C6678 定点和浮点 DSP SM320C6701 用于军事应用的单核 C67x 浮点 DSP - 高达 167MHz SM320C6701-EP 增强型产品 C6701 浮点 DSP SM320C6711D-EP 增强型产品 C6711D 浮点 DSP SM320C6712D-EP 增强型产品 C6712D DSP SM320C6713B-EP 增强型产品 C6713 浮点 DSP SM320C6727B 军用级 C6727B 浮点 DSP SM320C6727B-EP 增强型产品 C6727 浮点 DSP SM320DM642-HIREL 高可靠性产品数字媒体 DM642 DSP SM32C6416T-EP 增强型产品 C6416T 定点 DSP SMJ320C6201B 军用定点数字信号处理器 SMJ320C6203 军用级 C62x 定点 DSP - 陶瓷封装 SMJ320C6415 军用级 C64x 定点 DSP - 陶瓷封装 SMJ320C6701 军用级 C67x 浮点 DSP - 陶瓷封装 SMJ320C6701-SP 航天级 C6701 浮点 DSP - 抗辐射 V 类、采用陶瓷封装 SMV320C6727B-SP 航天级 C6727B 浮点 DSP - 抗辐射 V 类、采用陶瓷封装 TMS320C5517 低功耗 C55x 定点 DSP- 高达 200MHz、USB、LCD 接口、FFT HWA、SAR ADC TMS320C5532 低功耗 C55x 定点 DSP- 高达 100MHz TMS320C5533 低功耗 C55x 定点 DSP- 高达 100MHz、USB TMS320C5534 低功耗 C55x 定点 DSP- 高达 100MHz、USB、LCD 接口 TMS320C5535 低功耗 C55x 定点 DSP- 高达 100MHz、USB、LCD 接口、FFT HWA、SAR ADC TMS320C6201 定点数字信号处理器 TMS320C6202 定点数字信号处理器 TMS320C6202B C62x 定点 DSP- 高达 300MHz、384KB TMS320C6203B C62x 定点 DSP- 高达 300MHz、896KB TMS320C6204 定点数字信号处理器 TMS320C6205 定点数字信号处理器 TMS320C6211B C62x 定点 DSP- 高达 167MHz TMS320C6411 C64x 定点 DSP- 高达 300MHz、McBSP TMS320C6414 C64x 定点 DSP- 高达 720MHz、McBSP TMS320C6415 C64x 定点 DSP- 高达 720MHz、McBSP、PCI TMS320C6416 C64x 定点 DSP- 高达 720MHz、McBSP、PCI、VCP/TCP TMS320C6421Q C64x+ 定点 DSP- 高达 600MHz、8 位 EMIFA、16 位 DDR2 TMS320C6424Q C64x+ 定点 DSP- 高达 600MHz、16/8 位 EMIFA、32/16 位 DDR2 TMS320C6454 C64x+ 定点 DSP - 高达 1GHz、64 位 EMIFA、32/16 位 DDR2、1Gbps 以太网 TMS320C6457 通信基础设施数字信号处理器 TMS320C6701 C67x 浮点 DSP- 高达 167MHz、McBSP TMS320C6711D C67x 浮点 DSP- 高达 250MHz、McBSP、32 位 EMIFA TMS320C6712D C67x 浮点 DSP- 高达 150MHz、McBSP、16 位 EMIFA TMS320C6720 C67x 浮点 DSP - 200MHz、McASP、16 位 EMIFA TMS320C6722B C67x 浮点 DSP- 高达 250MHz、McASP、16 位 EMIFA TMS320C6726B C67x 浮点 DSP- 高达 266MHz、McASP、16 位 EMIFA TMS320C6727 C67x 浮点 DSP- 高达 250MHz、McASP、32 位 EMIFA TMS320C6727B C67x 浮点 DSP- 高达 350MHz、McASP、32 位 EMIFA TMS320C6743 低功耗 C674x 浮点 DSP- 375MHz TMS320C6745 低功耗 C674x 浮点 DSP- 456MHz、QFP TMS320C6747 低功耗 C674x 浮点 DSP- 456MHz、PBGA TMS320DM642Q 视频/成像定点数字信号处理器 TMS320DM6431Q 数字媒体处理器,性能高达 2400MIPS、300MHz 时钟速率 TMS320DM6435Q 数字媒体处理器,性能高达 4800MIPS、600MHz 时钟速率、1 个 McASP、1 个 McBSP TMS320DM6437Q 数字媒体处理器,性能高达 4800MIPS、600MHz 时钟速率、1 个 McASP、2 个 McBSP TMS320DM6441 达芬奇数字媒体片上系统 TMS320DM6467T 数字媒体片上系统 TMS320DM647 数字媒体处理器
下载选项
驱动程序或库

VOLIB 用于 C66x、C64x+ 和 C55x 处理器的音频库 (VoLIB)

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)

支持的产品和硬件

支持的产品和硬件

产品
基于 Arm 的处理器
66AK2G12 高性能多核 DSP+Arm - 1 个 Arm A15 内核、1 个 C66x DSP 内核
数字信号处理器 (DSP)
DM505 适用于视觉分析的 SoC,采用 15mm 封装 SM320C6201-EP 增强型产品 C6201 定点 DSP SM320C6415 军用级 C64x 定点 DSP SM320C6415-EP 增强型产品 C6415 定点 DSP SM320C6424-EP 增强型产品 C6424 定点 DSP SM320C6455-EP 增强型产品 C6455 定点 DSP SM320C6472-HIREL 高可靠性产品 6 核 C6472 定点 DSP SM320C6678-HIREL 高可靠性产品高性能 8 核 C6678 定点和浮点 DSP SM320C6701 用于军事应用的单核 C67x 浮点 DSP - 高达 167MHz SM320C6701-EP 增强型产品 C6701 浮点 DSP SM320C6711D-EP 增强型产品 C6711D 浮点 DSP SM320C6712D-EP 增强型产品 C6712D DSP SM320C6713B-EP 增强型产品 C6713 浮点 DSP SM320C6727B 军用级 C6727B 浮点 DSP SM320C6727B-EP 增强型产品 C6727 浮点 DSP SM320DM642-HIREL 高可靠性产品数字媒体 DM642 DSP SM32C6416T-EP 增强型产品 C6416T 定点 DSP SMJ320C6201B 军用定点数字信号处理器 SMJ320C6203 军用级 C62x 定点 DSP - 陶瓷封装 SMJ320C6415 军用级 C64x 定点 DSP - 陶瓷封装 SMJ320C6701 军用级 C67x 浮点 DSP - 陶瓷封装 SMJ320C6701-SP 航天级 C6701 浮点 DSP - 抗辐射 V 类、采用陶瓷封装 SMV320C6727B-SP 航天级 C6727B 浮点 DSP - 抗辐射 V 类、采用陶瓷封装 TMS320C5517 低功耗 C55x 定点 DSP- 高达 200MHz、USB、LCD 接口、FFT HWA、SAR ADC TMS320C5532 低功耗 C55x 定点 DSP- 高达 100MHz TMS320C5533 低功耗 C55x 定点 DSP- 高达 100MHz、USB TMS320C5534 低功耗 C55x 定点 DSP- 高达 100MHz、USB、LCD 接口 TMS320C5535 低功耗 C55x 定点 DSP- 高达 100MHz、USB、LCD 接口、FFT HWA、SAR ADC TMS320C6201 定点数字信号处理器 TMS320C6202 定点数字信号处理器 TMS320C6202B C62x 定点 DSP- 高达 300MHz、384KB TMS320C6203B C62x 定点 DSP- 高达 300MHz、896KB TMS320C6204 定点数字信号处理器 TMS320C6205 定点数字信号处理器 TMS320C6211B C62x 定点 DSP- 高达 167MHz TMS320C6411 C64x 定点 DSP- 高达 300MHz、McBSP TMS320C6414 C64x 定点 DSP- 高达 720MHz、McBSP TMS320C6415 C64x 定点 DSP- 高达 720MHz、McBSP、PCI TMS320C6416 C64x 定点 DSP- 高达 720MHz、McBSP、PCI、VCP/TCP TMS320C6421Q C64x+ 定点 DSP- 高达 600MHz、8 位 EMIFA、16 位 DDR2 TMS320C6424Q C64x+ 定点 DSP- 高达 600MHz、16/8 位 EMIFA、32/16 位 DDR2 TMS320C6454 C64x+ 定点 DSP - 高达 1GHz、64 位 EMIFA、32/16 位 DDR2、1Gbps 以太网 TMS320C6457 通信基础设施数字信号处理器 TMS320C6701 C67x 浮点 DSP- 高达 167MHz、McBSP TMS320C6711D C67x 浮点 DSP- 高达 250MHz、McBSP、32 位 EMIFA TMS320C6712D C67x 浮点 DSP- 高达 150MHz、McBSP、16 位 EMIFA TMS320C6720 C67x 浮点 DSP - 200MHz、McASP、16 位 EMIFA TMS320C6722B C67x 浮点 DSP- 高达 250MHz、McASP、16 位 EMIFA TMS320C6726B C67x 浮点 DSP- 高达 266MHz、McASP、16 位 EMIFA TMS320C6727 C67x 浮点 DSP- 高达 250MHz、McASP、32 位 EMIFA TMS320C6727B C67x 浮点 DSP- 高达 350MHz、McASP、32 位 EMIFA TMS320C6743 低功耗 C674x 浮点 DSP- 375MHz TMS320C6745 低功耗 C674x 浮点 DSP- 456MHz、QFP TMS320C6747 低功耗 C674x 浮点 DSP- 456MHz、PBGA TMS320DM642Q 视频/成像定点数字信号处理器 TMS320DM6431Q 数字媒体处理器,性能高达 2400MIPS、300MHz 时钟速率 TMS320DM6435Q 数字媒体处理器,性能高达 4800MIPS、600MHz 时钟速率、1 个 McASP、1 个 McBSP TMS320DM6437Q 数字媒体处理器,性能高达 4800MIPS、600MHz 时钟速率、1 个 McASP、2 个 McBSP TMS320DM6441 达芬奇数字媒体片上系统 TMS320DM6467T 数字媒体片上系统 TMS320DM647 数字媒体处理器
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SPRC090 — TMS320C6000 芯片支持库

芯片支持库 (CSL) 提供了一个应用程序编程接口 (API),用于配置和控制 DSP 片上外设,以实现易用性、各种 C6000 器件间的兼容性以及硬件抽象。通过本身的标准性和可移植性,可缩短开发时间。特性部分中列出的功能专为以下器件设计:C6201、C6202、C6203、C6204、C6205、C6211、C6410、C6412、C6413、C6414、C6415、C6416、C6418、C6701、C6711、C6712、C6713、DA610、DM640、DM641 和 DM642。

特性

模块名称外设说明
高速缓存高速缓存
DAT与器件无关的数据复制/填充
DMA直接存储器访问
EDMA (...)
驱动程序或库

SPRC122 — C62x/C64x 快速运行时支持 (RTS) 库

C62x/64x FastRTS Library 是优化型浮点函数库,适用于使用 TMS320C62x 或 TMS320C64x 器件的 C 语言编程器。这些例程通常用于计算密集型实时应用,在这些应用中,提高执行速度至关重要。通过将当前的浮点库 (RTS) 函数替换为 FastRTS Library,可以在不重写现有代码的情况下大大加快执行速度。

该版本还包括 FastRTS Library 中可用函数子集的 C 语言实施。C 代码可让用户内联这些函数并获得更高性能。

特性

单精度和双精度数学函数 单精度和双精度转换函数
浮点加法 将浮点值转换为 32 位带符号整数值
将 32 位带符号整数值转换为浮点值
(...)
仿真模型

DM642 GDK/GNZ IBIS Model DM642 GDK/GNZ IBIS Model

仿真模型

DM642 GDK BSDL Model DM642 GDK BSDL Model

仿真模型

DM642 GNZ BSDL Model DM642 GNZ BSDL Model

设计工具

PROCESSORS-3P-SEARCH Arm-based MPU, arm-based MCU and DSP third-party search tool

TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)
封装 引脚数 下载
FCBGA (ZDK) 548 了解详情
FCBGA (ZNZ) 548 了解详情

订购和质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 认证摘要
  • 持续可靠性监测

支持与培训

视频