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参数

DSP 1 C64x On-chip L2 cache/RAM 1024 KB Total on-chip memory (KB) 1056 Serial I/O McBSP SPI 3 Operating temperature range (C) -40 to 105, -55 to 105 Rating HiRel Enhanced Product open-in-new 查找其它 C6000 浮点 DSP

封装|引脚|尺寸

FCBGA (GLZ) 532 529 mm² 23 x 23 open-in-new 查找其它 C6000 浮点 DSP

特性

  • Highest-Performance Fixed-Point Digital Signal Processors (DSPs)
    • 2-ns Instruction Cycle Time
    • 500-MHz Clock Rate
    • Eight 32-Bit Instructions/Cycle
    • 28 Operations/Cycle
    • 4000 MIPS
    • Fully Software Compatible With C62x™
    • C6414/15/16 Devices Pin Compatible
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very Long Instruction Word
    (VLIW) TMS320C64x™ DSP Core
    • Eight Highly Independent Functional Units With
      VelociTI.2 Extensions With Six ALUs and Two Multipliers
    • Nonaligned Load-Store Architecture
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2 Increased Orthogonality
  • Viterbi Decoder Coprocessor (VCP) (C6416)
    • Supports Over 500 7.95-Kbps Adaptive Multi-Rate (AMR)
    • Programmable Code Parameters
  • Turbo Decoder Coprocessor (TCP) (C6416)
    • Supports up to Six 2-Mbps 3GPP (6 Iterations)
    • Programmable Turbo Code and Decoding Parameters
  • L1/L2 Memory Architecture
    • 128K-Bit (16K-Byte) L1P Program Cache
    • 128K-Bit (16K-Byte) L1D Data Cache
    • 8M-Bit (1024K-Byte) L2 Unified Mapped RAM/Cache
  • Two External Memory Interfaces (EMIFs) for 1280M-Byte Addressable External Memory
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • Host-Port Interface (HPI)
    • User-Configurable Bus Width (32/16 Bit)
  • 32-Bit/33-MHz, 3.3-V PCI Master/Slave Interface Conforms to PCI Specification 2.2 (C6415/C6416)
    • Three PCI Bus Address Registers
    • Four-Wire Serial EEPROM Interface
    • PCI Interrupt Request Under DSP Program Control
    • DSP Interrupt Via PCI I/O Cycle
  • Three Multichannel Buffered Serial Ports (McBSPs)
    • Direct Interface to T1/E1, MVIP, SCSA Framers
    • Up to 256 Channels Each
    • ST-Bus-Switching, AC97-Compatible
    • Serial Peripheral Interface (SPI) Compatible (Motorola)
  • Three 32-Bit General-Purpose Timers
  • Universal Test and Operations Physical Layer
    (PHY) Interface for ATM (UTOPIA) (C6415/C6416)
    • UTOPIA Level 2 Slave ATM Controller
    • 8-Bit Transmit and Receive Operations up to 50 MHz per Direction
    • User-Defined Cell Format up to 64 Bytes
  • Sixteen General-Purpose I/O (GPIO) Pins
  • Flexible Phase-Locked Loop (PLL) Clock Generator
  • IEEE-1149.1 (JTAG(1) Boundary-Scan-Compatible
  • 532-Pin Ball Grid Array (BGA) Package (GLZ Suffix), 0.8-mm Ball Pitch
  • 0.13-µm/6-Level Metal Process (CMOS)
  • 3.3-V I/Os, 1.25-V Internal (500 MHz)
  • SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS
    • Controlled Baseline
    • One Assembly/Test Site
    • One Fabrication Site
    • Available in A-Version (–40°C/105°C) and
      S-Version (–55°C/105°C) Temperature Ranges(2)
    • Extended Product Life Cycle
    • Extended Product-Change Notification
    • Product Traceability

(1) IEEE Std 1149.1-1990 Standard Test-Access Port and Boundary Scan Architecture
(2) S-Version currently available for C6415 only. Additional custom temperature ranges available upon request.
(3) Throughout the remainder of this document, the SM320C6414-EP, SM320C6415-EP, and SM320C6416-EP are referred to as SM320C64x or C64x where generic and, where specific, their individual full device part numbers are used or abbreviated as C6414, C6415, or C6416, respectively.
(4) These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix "A" in front of a signal name indicates it is an EMIFA signal whereas a prefix "B" in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted from the signal name.

open-in-new 查找其它 C6000 浮点 DSP

描述

The TMS320C64x™ DSPs (including the SM320C6414-EP, SM320C6415-EP, and SM320C6416-EP devices) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The SM320C64x™ (C64x™) device is based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.

With performance of up to 4000 million instructions per second (MIPS) at a clock rate of 500 MHz, the C64x devices offer cost-effective solutions to high-performance DSP programming challenges. The C64x DSPs possess the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units – 2 multipliers for a 32-bit result and 6 arithmetic logic units (ALUs) – with VelociTI.2 extensions. The VelociTI.2 extensions in the eight functional units include new instructions to accelerate the performance in key applications and extend the parallelism of the VelociTI architecture. The C64x can produce four 32-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. The C64x DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices.

The C6416 device has two high-performance embedded coprocessors [Viterbi decoder coprocessor (VCP) and turbo decoder coprocessor (TCP)] that significantly speed up channel-decoding operations on chip. The VCP operating at CPU clock divided-by-4 can decode over 500 7.95-Kbps adaptive multi-rate (AMR) (K = 9, R = 1/3) voice channels. The VCP supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 1/2, 1/3, and 1/4, and flexible polynomials, while generating hard decisions or soft decisions. The TCP operating at CPU clock divided-by-2 can decode up to 36 384-Kbps or 6 2-Mbps turbo encoded channels (assuming iterations). The TCP implements the max*log-map algorithm and is designed to support all polynomials and rates required by Third-Generation Partnership Projects (3GPP and 3GPP2), with fully programmable frame length and turbo interleaver. Decoding parameters, such as the number of iterations and stopping criteria, are also programmable. Communications between the VCP/TCP and the CPU are carried out through the EDMA controller.

The C64x uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The level 1 program (L1P) cache is a 128K-bit direct-mapped cache and the level 1 data (L1D) cache is a 128K-bit 2-way set-associative cache. The level 2 memory/cache (L2) consists of an 8M-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory or combinations of cache (up to 256K bytes) and mapped memory. The peripheral set includes 3 multichannel buffered serial ports (McBSPs), an 8-bit universal test and operations PHY interface for asynchronous transfer mode (ATM) slave (UTOPIA slave) port (C6415/C6416 only), 3 32-bit general-purpose timers, a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32), a peripheral component interconnect (PCI) (C6415/C6416 only), a general-purpose input/output port (GPIO) with 16 GPIO pins, and two glueless external memory interfaces (64-bit EMIFA and 16-bit EMIFB), both of which are capable of interfacing to synchronous and asynchronous memories and peripherals.

The C64x has a complete set of development tools that includes an advanced C compiler with C64x-specific enhancements, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.(3)(4)

open-in-new 查找其它 C6000 浮点 DSP
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技术文档

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类型 标题 下载最新的英文版本 发布
* 数据表 SM320C6414-EP, SM320C6415-EP, SM320C6416-EP 数据表 2008年 9月 19日
* 勘误表 TMS320C6414/C6415/C6416 Silicon Errata (Silicon Rev. 1.0,1.01,1.02,1.03,1.1,2.0) 2007年 8月 1日
VID SM320C6415-EP VID V6204609 2016年 6月 21日
应用手册 Power Consumption Guide for the C66x 2011年 10月 6日
应用手册 TMS320C6415 Hardware Designer's Resource Guide 2005年 10月 22日

设计与开发

有关其他条款或所需资源,请点击下面的任何链接来查看详情页面。

软件开发

调试探测 下载
Blackhawk XDS560v2 系统跟踪 USB 仿真器
TMDSEMU560V2STM-U XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针(仿真器)的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件,通过捕获相关器件级信息,获得准确的总线性能活动和吞吐量,并对内核和外设进行电源管理。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS 调试探针均支持内核和系统跟踪。

Blackhawk XDS560v2 System Trace 通过 MIPI HSPT 60 引脚连接器(带有适合 TI 14 引脚、TI 20 引脚和 ARM 20 (...)

995
特性

XDS560v2 是 XDS560 系列高性能 TI 处理器调试探针(仿真器)的最新型号。XDS560v2 具有整个系列中最快的速度和最多的功能,对于 TI 微控制器、处理器和无线连接微控制器的调试来说,它是最全面的解决方案。

XDS560v2 是 XDS560 调试探针系列中最先提供系统跟踪 (STM) 功能的一款,这种类型的跟踪可以通过捕获系统事件(例如处理内核的状态、内部总线和外设)来监控整个设备。大多数 XDS560v2 模型还提供系统引脚跟踪模式,在这种模式中,系统跟踪数据被送到 XDS560v2 内的外部存储器缓冲区 (128MB),因此能够捕获大量系统事件。系统引脚跟踪数据连接需要通过额外的接线连接 JTAG 连接器。

在 XDS560 调试探针系列中,XDS560v2 PRO TRACE 是提供内核引脚跟踪功能(指令和数据)的第二代产品,这种跟踪可以捕获内核执行的所有指令并将其发送到 XDS560v2 PRO TRACE 内的外部存储器缓冲区 (1GB)。内核引脚跟踪并不干扰系统的实时行为,而且可以捕获更多的指令。内核引脚跟踪数据连接需要通过额外的接线连接 JTAG 连接器。

为了支持所有类型的引脚跟踪(指令和系统),XDS560v2 的所有型号都提供标准的 60 引脚 MIPI HSPT 连接器作为与目标之间的主要 JTAG 连接。此外,所有型号都提供针对 TI 和 ARM 标准 JTAG 连接器的模块化目标适配器(提供的适配器因型号而异)。

XDS560v2 支持传统的 IEEE1149.1 (JTAG) 仿真和 IEEE1149.7 (cJTAG),运行时的 JTAG 接口电平为 1.2V 至 +4.1V。

与传统 JTAG 相比,紧凑 JTAG (cJTAG) 有巨大的进步;因为它仅需使用两个引脚即可支持所有功能,可用于某些指定的 TI 无线连接微控制器中。

所有 XDS560v2 (...)

调试探测 下载
Spectrum Digital XDS560v2 系统跟踪 USB 和以太网
TMDSEMU560V2STM-UE XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针(仿真器)的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件,通过捕获相关器件级信息,获得准确的总线性能活动和吞吐量,并对内核和外设进行电源管理。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS 调试探针均支持内核和系统跟踪。

Spectrum Digital XDS560v2 System Trace 通过 MIPI HSPT 60 引脚连接器(适合 TI 14 引脚、TI 20 引脚、ARM 20 引脚和 TI 60 (...)

1495
特性

XDS560v2 是 XDS560 系列高性能 TI 处理器调试探针(仿真器)的最新型号。XDS560v2 具有整个系列中最快的速度和最多的功能,对于 TI 微控制器、处理器和无线连接微控制器的调试来说,它是最全面的解决方案。

XDS560v2 是 XDS560 调试探针系列中最先提供系统跟踪 (STM) 功能的一款,这种类型的跟踪可以通过捕获系统事件(例如处理内核的状态、内部总线和外设)来监控整个设备。大多数 XDS560v2 模型还提供系统引脚跟踪模式,在这种模式中,系统跟踪数据被送到 XDS560v2 内的外部存储器缓冲区 (128MB),因此能够捕获大量系统事件。系统引脚跟踪数据连接需要通过额外的接线连接 JTAG 连接器。

在 XDS560 调试探针系列中,XDS560v2 PRO TRACE 是提供内核引脚跟踪功能(指令和数据)的第二代产品,这种跟踪可以捕获内核执行的所有指令并将其发送到 XDS560v2 PRO TRACE 内的外部存储器缓冲区 (1GB)。内核引脚跟踪并不干扰系统的实时行为,而且可以捕获更多的指令。内核引脚跟踪数据连接需要通过额外的接线连接 JTAG 连接器。

为了支持所有类型的引脚跟踪(指令和系统),XDS560v2 的所有型号都提供标准的 60 引脚 MIPI HSPT 连接器作为与目标之间的主要 JTAG 连接。此外,所有型号都提供针对 TI 和 ARM 标准 JTAG 连接器的模块化目标适配器(提供的适配器因型号而异)。

XDS560v2 支持传统的 IEEE1149.1 (JTAG) 仿真和 IEEE1149.7 (cJTAG),运行时的 JTAG 接口电平为 1.2V 至 +4.1V。

与传统 JTAG 相比,紧凑 JTAG (cJTAG) 有巨大的进步;因为它仅需使用两个引脚即可支持所有功能,可用于某些指定的 TI 无线连接微控制器中。

所有 XDS560v2 (...)

驱动程序和库 下载
TMS320C6000 DSP 库 (DSPLIB)
SPRC265 TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
特性

Optimized DSP routines including functions for:

  • Adaptive filtering
  • Correlation
  • FFT
  • Filtering and convolution: FIR, biquad, IIR, convolution
  • Math: Dot products, max value, min value, etc.
  • Matrix operations
驱动程序和库 下载
IDE、配置、编译器和调试器 下载
C6000 代码生成工具 - 编译器
C6000-CGT — TI C6000 C/C++ 编译器和汇编语言工具支持开发适用于 TI C6000 数字信号处理器平台的应用,包括 C66x 多核处理器、C674x 和 C64x+ 单核数字信号处理器。
特性
  • 在 v8.3.0 和更高版本的 C6000 代码生成工具中提供:
    • 支持 C++14 标准 ISO/IEC 14882:2014(不再支持 C++03)
  • 在 v8.2.0 和更高版本的 C6000 代码生成工具中提供:
    • 将浮点值转换为无符号字符或短整型字符时,不再生成 RTS 库调用
    • 提高了 OpenCL-C 矢量类型的性能
  • 在 v8.1.0 和更高版本的 C6000 代码生成工具中提供:
    • 编译 OpenCL-C 内核时,缩短了编译时间,减小了内存使用量

TI 编译器支持

TI 拥有一个快速响应的活跃 E2E™ 社区,该社区为 TI 编译器提供了支持。

CAD/CAE 符号

封装 引脚 下载
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