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DSP 1 C64x DSP MHz (Max) 500 CPU 32-/64-bit Operating system DSP/BIOS Rating HiRel Enhanced Product Operating temperature range (C) -40 to 105, -55 to 105
DSP 1 C64x DSP MHz (Max) 500 CPU 32-/64-bit Operating system DSP/BIOS Rating HiRel Enhanced Product Operating temperature range (C) -40 to 105, -55 to 105
FCBGA (GLZ) 532 529 mm² 23 x 23
  • Highest-Performance Fixed-Point Digital Signal Processors (DSPs)
    • 2-ns Instruction Cycle Time
    • 500-MHz Clock Rate
    • Eight 32-Bit Instructions/Cycle
    • 28 Operations/Cycle
    • 4000 MIPS
    • Fully Software Compatible With C62x™
    • C6414/15/16 Devices Pin Compatible
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very Long Instruction Word
    (VLIW) TMS320C64x™ DSP Core
    • Eight Highly Independent Functional Units With
      VelociTI.2 Extensions With Six ALUs and Two Multipliers
    • Nonaligned Load-Store Architecture
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2 Increased Orthogonality
  • Viterbi Decoder Coprocessor (VCP) (C6416)
    • Supports Over 500 7.95-Kbps Adaptive Multi-Rate (AMR)
    • Programmable Code Parameters
  • Turbo Decoder Coprocessor (TCP) (C6416)
    • Supports up to Six 2-Mbps 3GPP (6 Iterations)
    • Programmable Turbo Code and Decoding Parameters
  • L1/L2 Memory Architecture
    • 128K-Bit (16K-Byte) L1P Program Cache
    • 128K-Bit (16K-Byte) L1D Data Cache
    • 8M-Bit (1024K-Byte) L2 Unified Mapped RAM/Cache
  • Two External Memory Interfaces (EMIFs) for 1280M-Byte Addressable External Memory
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • Host-Port Interface (HPI)
    • User-Configurable Bus Width (32/16 Bit)
  • 32-Bit/33-MHz, 3.3-V PCI Master/Slave Interface Conforms to PCI Specification 2.2 (C6415/C6416)
    • Three PCI Bus Address Registers
    • Four-Wire Serial EEPROM Interface
    • PCI Interrupt Request Under DSP Program Control
    • DSP Interrupt Via PCI I/O Cycle
  • Three Multichannel Buffered Serial Ports (McBSPs)
    • Direct Interface to T1/E1, MVIP, SCSA Framers
    • Up to 256 Channels Each
    • ST-Bus-Switching, AC97-Compatible
    • Serial Peripheral Interface (SPI) Compatible (Motorola)
  • Three 32-Bit General-Purpose Timers
  • Universal Test and Operations Physical Layer
    (PHY) Interface for ATM (UTOPIA) (C6415/C6416)
    • UTOPIA Level 2 Slave ATM Controller
    • 8-Bit Transmit and Receive Operations up to 50 MHz per Direction
    • User-Defined Cell Format up to 64 Bytes
  • Sixteen General-Purpose I/O (GPIO) Pins
  • Flexible Phase-Locked Loop (PLL) Clock Generator
  • IEEE-1149.1 (JTAG(1) Boundary-Scan-Compatible
  • 532-Pin Ball Grid Array (BGA) Package (GLZ Suffix), 0.8-mm Ball Pitch
  • 0.13-µm/6-Level Metal Process (CMOS)
  • 3.3-V I/Os, 1.25-V Internal (500 MHz)
  • SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS
    • Controlled Baseline
    • One Assembly/Test Site
    • One Fabrication Site
    • Available in A-Version (–40°C/105°C) and
      S-Version (–55°C/105°C) Temperature Ranges(2)
    • Extended Product Life Cycle
    • Extended Product-Change Notification
    • Product Traceability

(1) IEEE Std 1149.1-1990 Standard Test-Access Port and Boundary Scan Architecture
(2) S-Version currently available for C6415 only. Additional custom temperature ranges available upon request.
(3) Throughout the remainder of this document, the SM320C6414-EP, SM320C6415-EP, and SM320C6416-EP are referred to as SM320C64x or C64x where generic and, where specific, their individual full device part numbers are used or abbreviated as C6414, C6415, or C6416, respectively.
(4) These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix "A" in front of a signal name indicates it is an EMIFA signal whereas a prefix "B" in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted from the signal name.

  • Highest-Performance Fixed-Point Digital Signal Processors (DSPs)
    • 2-ns Instruction Cycle Time
    • 500-MHz Clock Rate
    • Eight 32-Bit Instructions/Cycle
    • 28 Operations/Cycle
    • 4000 MIPS
    • Fully Software Compatible With C62x™
    • C6414/15/16 Devices Pin Compatible
  • VelociTI.2™ Extensions to VelociTI™ Advanced Very Long Instruction Word
    (VLIW) TMS320C64x™ DSP Core
    • Eight Highly Independent Functional Units With
      VelociTI.2 Extensions With Six ALUs and Two Multipliers
    • Nonaligned Load-Store Architecture
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
  • Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • VelociTI.2 Increased Orthogonality
  • Viterbi Decoder Coprocessor (VCP) (C6416)
    • Supports Over 500 7.95-Kbps Adaptive Multi-Rate (AMR)
    • Programmable Code Parameters
  • Turbo Decoder Coprocessor (TCP) (C6416)
    • Supports up to Six 2-Mbps 3GPP (6 Iterations)
    • Programmable Turbo Code and Decoding Parameters
  • L1/L2 Memory Architecture
    • 128K-Bit (16K-Byte) L1P Program Cache
    • 128K-Bit (16K-Byte) L1D Data Cache
    • 8M-Bit (1024K-Byte) L2 Unified Mapped RAM/Cache
  • Two External Memory Interfaces (EMIFs) for 1280M-Byte Addressable External Memory
  • Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
  • Host-Port Interface (HPI)
    • User-Configurable Bus Width (32/16 Bit)
  • 32-Bit/33-MHz, 3.3-V PCI Master/Slave Interface Conforms to PCI Specification 2.2 (C6415/C6416)
    • Three PCI Bus Address Registers
    • Four-Wire Serial EEPROM Interface
    • PCI Interrupt Request Under DSP Program Control
    • DSP Interrupt Via PCI I/O Cycle
  • Three Multichannel Buffered Serial Ports (McBSPs)
    • Direct Interface to T1/E1, MVIP, SCSA Framers
    • Up to 256 Channels Each
    • ST-Bus-Switching, AC97-Compatible
    • Serial Peripheral Interface (SPI) Compatible (Motorola)
  • Three 32-Bit General-Purpose Timers
  • Universal Test and Operations Physical Layer
    (PHY) Interface for ATM (UTOPIA) (C6415/C6416)
    • UTOPIA Level 2 Slave ATM Controller
    • 8-Bit Transmit and Receive Operations up to 50 MHz per Direction
    • User-Defined Cell Format up to 64 Bytes
  • Sixteen General-Purpose I/O (GPIO) Pins
  • Flexible Phase-Locked Loop (PLL) Clock Generator
  • IEEE-1149.1 (JTAG(1) Boundary-Scan-Compatible
  • 532-Pin Ball Grid Array (BGA) Package (GLZ Suffix), 0.8-mm Ball Pitch
  • 0.13-µm/6-Level Metal Process (CMOS)
  • 3.3-V I/Os, 1.25-V Internal (500 MHz)
  • SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS
    • Controlled Baseline
    • One Assembly/Test Site
    • One Fabrication Site
    • Available in A-Version (–40°C/105°C) and
      S-Version (–55°C/105°C) Temperature Ranges(2)
    • Extended Product Life Cycle
    • Extended Product-Change Notification
    • Product Traceability

(1) IEEE Std 1149.1-1990 Standard Test-Access Port and Boundary Scan Architecture
(2) S-Version currently available for C6415 only. Additional custom temperature ranges available upon request.
(3) Throughout the remainder of this document, the SM320C6414-EP, SM320C6415-EP, and SM320C6416-EP are referred to as SM320C64x or C64x where generic and, where specific, their individual full device part numbers are used or abbreviated as C6414, C6415, or C6416, respectively.
(4) These C64x devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix "A" in front of a signal name indicates it is an EMIFA signal whereas a prefix "B" in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted from the signal name.

The TMS320C64x™ DSPs (including the SM320C6414-EP, SM320C6415-EP, and SM320C6416-EP devices) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The SM320C64x™ (C64x™) device is based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.

With performance of up to 4000 million instructions per second (MIPS) at a clock rate of 500 MHz, the C64x devices offer cost-effective solutions to high-performance DSP programming challenges. The C64x DSPs possess the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units – 2 multipliers for a 32-bit result and 6 arithmetic logic units (ALUs) – with VelociTI.2 extensions. The VelociTI.2 extensions in the eight functional units include new instructions to accelerate the performance in key applications and extend the parallelism of the VelociTI architecture. The C64x can produce four 32-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. The C64x DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices.

The C6416 device has two high-performance embedded coprocessors [Viterbi decoder coprocessor (VCP) and turbo decoder coprocessor (TCP)] that significantly speed up channel-decoding operations on chip. The VCP operating at CPU clock divided-by-4 can decode over 500 7.95-Kbps adaptive multi-rate (AMR) (K = 9, R = 1/3) voice channels. The VCP supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 1/2, 1/3, and 1/4, and flexible polynomials, while generating hard decisions or soft decisions. The TCP operating at CPU clock divided-by-2 can decode up to 36 384-Kbps or 6 2-Mbps turbo encoded channels (assuming iterations). The TCP implements the max*log-map algorithm and is designed to support all polynomials and rates required by Third-Generation Partnership Projects (3GPP and 3GPP2), with fully programmable frame length and turbo interleaver. Decoding parameters, such as the number of iterations and stopping criteria, are also programmable. Communications between the VCP/TCP and the CPU are carried out through the EDMA controller.

The C64x uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The level 1 program (L1P) cache is a 128K-bit direct-mapped cache and the level 1 data (L1D) cache is a 128K-bit 2-way set-associative cache. The level 2 memory/cache (L2) consists of an 8M-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory or combinations of cache (up to 256K bytes) and mapped memory. The peripheral set includes 3 multichannel buffered serial ports (McBSPs), an 8-bit universal test and operations PHY interface for asynchronous transfer mode (ATM) slave (UTOPIA slave) port (C6415/C6416 only), 3 32-bit general-purpose timers, a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32), a peripheral component interconnect (PCI) (C6415/C6416 only), a general-purpose input/output port (GPIO) with 16 GPIO pins, and two glueless external memory interfaces (64-bit EMIFA and 16-bit EMIFB), both of which are capable of interfacing to synchronous and asynchronous memories and peripherals.

The C64x has a complete set of development tools that includes an advanced C compiler with C64x-specific enhancements, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.(3)(4)

The TMS320C64x™ DSPs (including the SM320C6414-EP, SM320C6415-EP, and SM320C6416-EP devices) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The SM320C64x™ (C64x™) device is based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.

With performance of up to 4000 million instructions per second (MIPS) at a clock rate of 500 MHz, the C64x devices offer cost-effective solutions to high-performance DSP programming challenges. The C64x DSPs possess the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units – 2 multipliers for a 32-bit result and 6 arithmetic logic units (ALUs) – with VelociTI.2 extensions. The VelociTI.2 extensions in the eight functional units include new instructions to accelerate the performance in key applications and extend the parallelism of the VelociTI architecture. The C64x can produce four 32-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. The C64x DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices.

The C6416 device has two high-performance embedded coprocessors [Viterbi decoder coprocessor (VCP) and turbo decoder coprocessor (TCP)] that significantly speed up channel-decoding operations on chip. The VCP operating at CPU clock divided-by-4 can decode over 500 7.95-Kbps adaptive multi-rate (AMR) (K = 9, R = 1/3) voice channels. The VCP supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 1/2, 1/3, and 1/4, and flexible polynomials, while generating hard decisions or soft decisions. The TCP operating at CPU clock divided-by-2 can decode up to 36 384-Kbps or 6 2-Mbps turbo encoded channels (assuming iterations). The TCP implements the max*log-map algorithm and is designed to support all polynomials and rates required by Third-Generation Partnership Projects (3GPP and 3GPP2), with fully programmable frame length and turbo interleaver. Decoding parameters, such as the number of iterations and stopping criteria, are also programmable. Communications between the VCP/TCP and the CPU are carried out through the EDMA controller.

The C64x uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The level 1 program (L1P) cache is a 128K-bit direct-mapped cache and the level 1 data (L1D) cache is a 128K-bit 2-way set-associative cache. The level 2 memory/cache (L2) consists of an 8M-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory or combinations of cache (up to 256K bytes) and mapped memory. The peripheral set includes 3 multichannel buffered serial ports (McBSPs), an 8-bit universal test and operations PHY interface for asynchronous transfer mode (ATM) slave (UTOPIA slave) port (C6415/C6416 only), 3 32-bit general-purpose timers, a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32), a peripheral component interconnect (PCI) (C6415/C6416 only), a general-purpose input/output port (GPIO) with 16 GPIO pins, and two glueless external memory interfaces (64-bit EMIFA and 16-bit EMIFB), both of which are capable of interfacing to synchronous and asynchronous memories and peripherals.

The C64x has a complete set of development tools that includes an advanced C compiler with C64x-specific enhancements, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.(3)(4)

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技术文档

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类型 标题 下载最新的英文版本 日期
* 数据表 SM320C6414-EP, SM320C6415-EP, SM320C6416-EP 数据表 (Rev. D) 2008年 9月 19日
* 勘误表 TMS320C6414/C6415/C6416 Silicon Errata (Silicon Rev. 1.0,1.01,1.02,1.03,1.1,2.0) (Rev. T) 2007年 8月 1日
* VID SM320C6415-EP VID V6204609 2016年 6月 21日
技术文章 Bringing the next evolution of machine learning to the edge 2018年 11月 27日
技术文章 How quality assurance on the Processor SDK can improve software scalability 2018年 8月 22日
技术文章 Clove: Low-Power video solutions based on Sitara™ AM57x processors 2016年 7月 21日
技术文章 TI's new DSP Benchmark Site 2016年 2月 8日
应用手册 Power Consumption Guide for the C66x 2011年 10月 6日
应用手册 TMS320C6415 Hardware Designer's Resource Guide (Rev. A) 2005年 10月 22日

设计与开发

有关其他条款或所需资源,请点击下面的任何链接来查看详情页面。

调试探针

TMDSEMU560V2STM-U — Blackhawk XDS560v2 系统跟踪 USB 仿真器

XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针(仿真器)的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件,通过捕获相关器件级信息,获得准确的总线性能活动和吞吐量,并对内核和外设进行电源管理。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS 调试探针均支持内核和系统跟踪。

Blackhawk XDS560v2 System Trace 通过 MIPI HSPT 60 引脚连接器(带有适合 TI 14 引脚、TI 20 引脚和 ARM 20 (...)

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数量限制: 1
调试探针

TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 系统跟踪 USB 和以太网

XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针(仿真器)的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件,通过捕获相关器件级信息,获得准确的总线性能活动和吞吐量,并对内核和外设进行电源管理。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS 调试探针均支持内核和系统跟踪。

Spectrum Digital XDS560v2 System Trace 通过 MIPI HSPT 60 引脚连接器(适合 TI 14 引脚、TI 20 引脚、ARM 20 引脚和 TI 60 (...)

现货
数量限制: 1
驱动程序或库

SPRC265 — TMS320C6000 DSP 库 (DSPLIB)

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
驱动程序或库

TELECOMLIB — 用于 TMS320C64x+ 和 TMS320C55x 处理器的电信和媒体库 - FAXLIB、VoLIB 和 AEC/AER

设计工具

PROCESSORS-3P-SEARCH — Arm-based MPU, arm-based MCU and DSP third-party search tool

TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)
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FCBGA (GLZ) 532 了解详情

订购与质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/FIT 估算
  • 材料成分
  • 认证摘要
  • 持续可靠性监测

支持与培训

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