产品详细信息

DSP 1 C64x DSP MHz (Max) 513, 594, 810 CPU 32-/64-bit Operating system DSP/BIOS, Integrity, Linux, Neutrino, PrOS, Windows Embedded CE Ethernet MAC 10/100 Rating Catalog Operating temperature range (C) 0 to 85, -40 to 105
DSP 1 C64x DSP MHz (Max) 513, 594, 810 CPU 32-/64-bit Operating system DSP/BIOS, Integrity, Linux, Neutrino, PrOS, Windows Embedded CE Ethernet MAC 10/100 Rating Catalog Operating temperature range (C) 0 to 85, -40 to 105
NFBGA (ZWT) 361 256 mm² 16 x 16
  • High-Performance Digital Media SoC
    • 513-, 594-, 810-MHz C64x+™ Clock Rates
    • 256.5-, 297-, 405-MHz ARM926EJ-S™ Clock Rates
    • Eight 32-Bit C64x+ Instructions/Cycle
    • 4104, 4752, 6480 C64x+ MIPS
    • Fully Software-Compatible With C64x / ARM9™
    • Extended Temperature Devices Available
  • Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
    • Eight Highly Independent Functional Units
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Additional C64x+™ Enhancements
      • Protected Mode Operation
      • Exceptions Support for Error Detection and Program Redirection
      • Hardware Support for Modulo Loop Operation
  • C64x+ Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • Compact 16-Bit Instructions
    • Additional Instructions to Support Complex Multiplies
  • C64x+ L1/L2 Memory Architecture
    • 32K-Byte L1P Program RAM/Cache (Direct Mapped)
    • 80K-Byte L1D Data RAM/Cache (2-Way Set-Associative)
    • 64K-Byte L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
  • ARM926EJ-S Core
    • Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets
    • DSP Instruction Extensions and Single Cycle MAC
    • ARM® Jazelle®: Technology
    • EmbeddedICE-RT™ Logic for Real-Time Debug
  • ARM9 Memory Architecture
    • 16K-Byte Instruction Cache
    • 8K-Byte Data Cache
    • 16K-Byte RAM
    • 8K-Byte ROM
  • Embedded Trace Buffer™ (ETB11™) With 4KB Memory for ARM9 Debug
  • Endianness: Little Endian for ARM and DSP
  • Video Imaging Co-Processor (VICP)
  • Video Processing Subsystem
    • Front End Provides:
      • CCD and CMOS Imager Interface
      • BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
      • Preview Engine for Real-Time Image Processing
      • Glueless Interface to Common Video Decoders
      • Histogram Module
      • Auto-Exposure, Auto-White Balance and Auto-Focus Module
      • Resize Engine Resize
        • Images From 1/4x to 4x
        • Separate Horizontal/Vertical Control
    • Back End Provides:
      • Hardware On-Screen Display (OSD)
      • Four 54-MHz DACs for a Combination of
        • Composite NTSC/PAL Video
        • Luma/Chroma Separate Video (S-video)
        • Component (YPbPr or RGB) Video (Progressive)
      • Digital Output
        • 8-/16-bit YUV or up to 24-Bit RGB
        • HD Resolution
        • Up to 2 Video Windows
  • External Memory Interfaces (EMIFs)
    • 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8-V I/O)
      • Up to 167-MHz Controller (A-513, -594)
      • Up to 189-MHz Controller (-810)
    • Asynchronous 16-Bit-Wide EMIF (EMIFA) With 128M-Byte Address Reach
      • Flash Memory Interfaces
        • NOR (8-/16-Bit-Wide Data)
        • NAND (8-/16-Bit-Wide Data)
  • Flash Card Interfaces
    • Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO)
    • Compact Flash Controller With True IDE Mode
    • SmartMedia
  • Enhanced Direct-Memory-Access (EDMA3) Controller (64 Independent Channels)
  • Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit Watch Dog Timer
  • Three UARTs (One with RTS and CTS Flow Control)
  • One Serial Peripheral Interface (SPI) With Two Chip-Selects
  • Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • Audio Serial Port (ASP)
    • I2S
    • AC97 Audio Codec Interface
    • Standard Voice Codec Interface (AIC12)
  • 10/100 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Media Independent Interface (MII)
  • VLYNQ™ Interface (FPGA Interface)
  • Host Port Interface (HPI) with 16-Bit Multiplexed Address/Data
  • USB Port With Integrated 2.0 PHY
    • USB 2.0 High-/Full-Speed (480-Mbps) Client
    • USB 2.0 High-/Full-/Low-Speed Host (Mini-Host, Supporting One External Device)
  • Three Pulse Width Modulator (PWM) Outputs
  • On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash or UART
  • ATA/ATAPI I/F (ATA/ATAPI-6 Specification)
  • Individual Power-Saving Modes for ARM/DSP
  • Flexible PLL Clock Generators
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • Up to 71 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
  • 361-Pin Pb-Free BGA Package(ZWT Suffix), 0.8-mm Ball Pitch
  • 0.09-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V and 1.8-V I/O, 1.2-V Internal (513, 594)
  • 3.3-V and 1.8-V I/O, 1.2-V DAC and USB, 1.3-V Internal (810 only)
  • Applications:
    • Digital Media
    • Networked Media Encode/Decode
    • Video Imaging

All other trademarks are the property of their respective owners

  • High-Performance Digital Media SoC
    • 513-, 594-, 810-MHz C64x+™ Clock Rates
    • 256.5-, 297-, 405-MHz ARM926EJ-S™ Clock Rates
    • Eight 32-Bit C64x+ Instructions/Cycle
    • 4104, 4752, 6480 C64x+ MIPS
    • Fully Software-Compatible With C64x / ARM9™
    • Extended Temperature Devices Available
  • Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
    • Eight Highly Independent Functional Units
      • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
      • Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
    • Load-Store Architecture With Non-Aligned Support
    • 64 32-Bit General-Purpose Registers
    • Instruction Packing Reduces Code Size
    • All Instructions Conditional
    • Additional C64x+™ Enhancements
      • Protected Mode Operation
      • Exceptions Support for Error Detection and Program Redirection
      • Hardware Support for Modulo Loop Operation
  • C64x+ Instruction Set Features
    • Byte-Addressable (8-/16-/32-/64-Bit Data)
    • 8-Bit Overflow Protection
    • Bit-Field Extract, Set, Clear
    • Normalization, Saturation, Bit-Counting
    • Compact 16-Bit Instructions
    • Additional Instructions to Support Complex Multiplies
  • C64x+ L1/L2 Memory Architecture
    • 32K-Byte L1P Program RAM/Cache (Direct Mapped)
    • 80K-Byte L1D Data RAM/Cache (2-Way Set-Associative)
    • 64K-Byte L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation)
  • ARM926EJ-S Core
    • Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets
    • DSP Instruction Extensions and Single Cycle MAC
    • ARM® Jazelle®: Technology
    • EmbeddedICE-RT™ Logic for Real-Time Debug
  • ARM9 Memory Architecture
    • 16K-Byte Instruction Cache
    • 8K-Byte Data Cache
    • 16K-Byte RAM
    • 8K-Byte ROM
  • Embedded Trace Buffer™ (ETB11™) With 4KB Memory for ARM9 Debug
  • Endianness: Little Endian for ARM and DSP
  • Video Imaging Co-Processor (VICP)
  • Video Processing Subsystem
    • Front End Provides:
      • CCD and CMOS Imager Interface
      • BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface
      • Preview Engine for Real-Time Image Processing
      • Glueless Interface to Common Video Decoders
      • Histogram Module
      • Auto-Exposure, Auto-White Balance and Auto-Focus Module
      • Resize Engine Resize
        • Images From 1/4x to 4x
        • Separate Horizontal/Vertical Control
    • Back End Provides:
      • Hardware On-Screen Display (OSD)
      • Four 54-MHz DACs for a Combination of
        • Composite NTSC/PAL Video
        • Luma/Chroma Separate Video (S-video)
        • Component (YPbPr or RGB) Video (Progressive)
      • Digital Output
        • 8-/16-bit YUV or up to 24-Bit RGB
        • HD Resolution
        • Up to 2 Video Windows
  • External Memory Interfaces (EMIFs)
    • 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8-V I/O)
      • Up to 167-MHz Controller (A-513, -594)
      • Up to 189-MHz Controller (-810)
    • Asynchronous 16-Bit-Wide EMIF (EMIFA) With 128M-Byte Address Reach
      • Flash Memory Interfaces
        • NOR (8-/16-Bit-Wide Data)
        • NAND (8-/16-Bit-Wide Data)
  • Flash Card Interfaces
    • Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO)
    • Compact Flash Controller With True IDE Mode
    • SmartMedia
  • Enhanced Direct-Memory-Access (EDMA3) Controller (64 Independent Channels)
  • Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
  • One 64-Bit Watch Dog Timer
  • Three UARTs (One with RTS and CTS Flow Control)
  • One Serial Peripheral Interface (SPI) With Two Chip-Selects
  • Master/Slave Inter-Integrated Circuit (I2C Bus™)
  • Audio Serial Port (ASP)
    • I2S
    • AC97 Audio Codec Interface
    • Standard Voice Codec Interface (AIC12)
  • 10/100 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Media Independent Interface (MII)
  • VLYNQ™ Interface (FPGA Interface)
  • Host Port Interface (HPI) with 16-Bit Multiplexed Address/Data
  • USB Port With Integrated 2.0 PHY
    • USB 2.0 High-/Full-Speed (480-Mbps) Client
    • USB 2.0 High-/Full-/Low-Speed Host (Mini-Host, Supporting One External Device)
  • Three Pulse Width Modulator (PWM) Outputs
  • On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash or UART
  • ATA/ATAPI I/F (ATA/ATAPI-6 Specification)
  • Individual Power-Saving Modes for ARM/DSP
  • Flexible PLL Clock Generators
  • IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
  • Up to 71 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
  • 361-Pin Pb-Free BGA Package(ZWT Suffix), 0.8-mm Ball Pitch
  • 0.09-µm/6-Level Cu Metal Process (CMOS)
  • 3.3-V and 1.8-V I/O, 1.2-V Internal (513, 594)
  • 3.3-V and 1.8-V I/O, 1.2-V DAC and USB, 1.3-V Internal (810 only)
  • Applications:
    • Digital Media
    • Networked Media Encode/Decode
    • Video Imaging

All other trademarks are the property of their respective owners

The TMS320DM6446 (also referenced as DM6446) leverages TI's DaVinci™ technology to meet the networked media encode and decode application processing needs of next-generation embedded devices.

The DM6446 enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution.

The dual-core architecture of the DM6446 provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C64x+™ DSP core and an ARM926EJ-S core.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core incorporates: A coprocessor 15 (CP15) and protection module Data and program Memory Management Units (MMUs) with table look-aside buffers. Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT).

The TMS320C64x+™ DSPs are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. It is based on an enhanced version of the second-generation high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSP cores an excellent choice for digital media applications. The C64x is a code-compatible member of the C6000™ DSP platform. The TMS320C64x+ DSP is an enhancement of the C64x+™ DSP with added functionality and an expanded instruction set.

Any reference to the C64x™ DSP or C64x™ CPU also applies, unless otherwise noted, to the C64x+™ DSP and C64x+™ CPU, respectively.

With performance of up to 6480 million instructions per second (MIPS) at a clock rate of 810 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units--two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 3240 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 6480 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732).

The DM6446 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6446 core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the Level 1 data cache (L1D) is a 640K-bit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 512K-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes: 2 configurable video ports; a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; an inter-integrated circuit (I2C) Bus interface; one audio serial port (ASP); 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; up to 71-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UARTs with hardware handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; and 2 external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2.

The DM6446 device includes a Video Processing Subsystem (VPSS) with two configurable video/imaging peripherals: 1 Video Processing Front-End (VPFE) input used for video capture, 1 Video Processing Back-End (VPBE) output with imaging co-processor (VICP) used for display.

The Video Processing Front-End (VPFE) is comprised of a CCD Controller (CCDC), a Preview Engine (Previewer), Histogram Module, Auto-Exposure/White Balance/Focus Module (H3A), and Resizer. The CCDC is capable of interfacing to common video decoders, CMOS sensors, and Charge Coupled Devices (CCDs). The Previewer is a real-time image processing engine that takes raw imager data from a CMOS sensor or CCD and converts from an RGB Bayer Pattern to YUV4:2:2. The Histogram and H3A modules provide statistical information on the raw color data for use by the DM6446. The Resizer accepts image data for separate horizontal and vertical resizing from 1/4x to 4x in increments of 256/N, where N is between 64 and 1024.

The Video Processing Back-End (VPBE) is comprised of an On-Screen Display Engine (OSD) and a Video Encoder (VENC). The OSD engine is capable of handling 2 separate video windows and 2 separate OSD windows. Other configurations include 2 video windows, 1 OSD window, and 1 attribute window allowing up to 8 levels of alpha blending. The VENC provides four analog DACs that run at 54 MHz, providing a means for composite NTSC/PAL video, S-Video, and/or Component video output. The VENC also provides up to 24 bits of digital output to interface to RGB888 devices. The digital output is capable of 8/16-bit BT.656 output and/or CCIR.601 with separate horizontal and vertical syncs.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the DM644x and the network. The DM6446 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.

The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the ARM, the MDIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the ARM, allowing the ARM to poll the link status of the device without continuously performing costly MDIO accesses.

The HPI, I2C, SPI, USB2.0, and VLYNQ ports allow DM6446 to easily control peripheral devices and/or communicate with host processors. The DM6446 also provides multimedia card support, MMC/SD, with SDIO support.

The DM6446 also includes a Video/Imaging Co-processor (VICP) to offload many video and imaging processing tasks from the DSP core, making more DSP MIPS available for common video and imaging algorithms. For more information on the VICP enhanced codecs, such as H.264 and MPEG4, please contact your nearest TI sales representative.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides listed in Section 2.8.3.1, Related Documentation From Texas Instruments.

The DM6446 has a complete set of development tools for both the ARM and DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

The TMS320DM6446 (also referenced as DM6446) leverages TI's DaVinci™ technology to meet the networked media encode and decode application processing needs of next-generation embedded devices.

The DM6446 enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, high processing performance, and long battery life through the maximum flexibility of a fully integrated mixed processor solution.

The dual-core architecture of the DM6446 provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C64x+™ DSP core and an ARM926EJ-S core.

The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.

The ARM core incorporates: A coprocessor 15 (CP15) and protection module Data and program Memory Management Units (MMUs) with table look-aside buffers. Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT).

The TMS320C64x+™ DSPs are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. It is based on an enhanced version of the second-generation high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSP cores an excellent choice for digital media applications. The C64x is a code-compatible member of the C6000™ DSP platform. The TMS320C64x+ DSP is an enhancement of the C64x+™ DSP with added functionality and an expanded instruction set.

Any reference to the C64x™ DSP or C64x™ CPU also applies, unless otherwise noted, to the C64x+™ DSP and C64x+™ CPU, respectively.

With performance of up to 6480 million instructions per second (MIPS) at a clock rate of 810 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units--two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 3240 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 6480 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732).

The DM6446 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6446 core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 256K-bit direct mapped cache and the Level 1 data cache (L1D) is a 640K-bit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 512K-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two.

The peripheral set includes: 2 configurable video ports; a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; an inter-integrated circuit (I2C) Bus interface; one audio serial port (ASP); 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; up to 71-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UARTs with hardware handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; and 2 external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2.

The DM6446 device includes a Video Processing Subsystem (VPSS) with two configurable video/imaging peripherals: 1 Video Processing Front-End (VPFE) input used for video capture, 1 Video Processing Back-End (VPBE) output with imaging co-processor (VICP) used for display.

The Video Processing Front-End (VPFE) is comprised of a CCD Controller (CCDC), a Preview Engine (Previewer), Histogram Module, Auto-Exposure/White Balance/Focus Module (H3A), and Resizer. The CCDC is capable of interfacing to common video decoders, CMOS sensors, and Charge Coupled Devices (CCDs). The Previewer is a real-time image processing engine that takes raw imager data from a CMOS sensor or CCD and converts from an RGB Bayer Pattern to YUV4:2:2. The Histogram and H3A modules provide statistical information on the raw color data for use by the DM6446. The Resizer accepts image data for separate horizontal and vertical resizing from 1/4x to 4x in increments of 256/N, where N is between 64 and 1024.

The Video Processing Back-End (VPBE) is comprised of an On-Screen Display Engine (OSD) and a Video Encoder (VENC). The OSD engine is capable of handling 2 separate video windows and 2 separate OSD windows. Other configurations include 2 video windows, 1 OSD window, and 1 attribute window allowing up to 8 levels of alpha blending. The VENC provides four analog DACs that run at 54 MHz, providing a means for composite NTSC/PAL video, S-Video, and/or Component video output. The VENC also provides up to 24 bits of digital output to interface to RGB888 devices. The digital output is capable of 8/16-bit BT.656 output and/or CCIR.601 with separate horizontal and vertical syncs.

The Ethernet Media Access Controller (EMAC) provides an efficient interface between the DM644x and the network. The DM6446 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support.

The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the ARM, the MDIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the ARM, allowing the ARM to poll the link status of the device without continuously performing costly MDIO accesses.

The HPI, I2C, SPI, USB2.0, and VLYNQ ports allow DM6446 to easily control peripheral devices and/or communicate with host processors. The DM6446 also provides multimedia card support, MMC/SD, with SDIO support.

The DM6446 also includes a Video/Imaging Co-processor (VICP) to offload many video and imaging processing tasks from the DSP core, making more DSP MIPS available for common video and imaging algorithms. For more information on the VICP enhanced codecs, such as H.264 and MPEG4, please contact your nearest TI sales representative.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides listed in Section 2.8.3.1, Related Documentation From Texas Instruments.

The DM6446 has a complete set of development tools for both the ARM and DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

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Limited design support from TI available

This product has limited design support from TI for existing projects. If available, you will find relevant collateral, software and tools in the product folder. For existing designs using this product, you can request support in the TI E2ETM support forums, but limited support is available for this product.

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类型 项目标题 下载最新的英语版本 日期
* 数据表 TMS320DM6446 Digital Media System-on-Chip 数据表 (Rev. H) 30 Sep 2010
* 勘误表 TMS320DM6446 Digital Media SoC Silicon Errata (Silicon Revs 2.1, 1.3, 1.2 & 1.1) (Rev. N) 23 Jul 2010
应用手册 高速接口布局指南 (Rev. I) PDF | HTML 14 Apr 2022
技术文章 Difficult to see. Always in motion is the future 04 Jan 2016
技术文章 Announcing the new entry-level Sitara processor 09 Dec 2015
技术文章 Automotive Surround View Technology trends 31 Aug 2015
技术文章 Where are DSPs used? What makes them so good at math? How do they work with Open APIs? 06 Aug 2015
应用手册 构建小型嵌入式Linux 内核示例 (Rev. A) 下载英文版本 (Rev.A) 30 Jul 2013
应用手册 USB 2.0 板载设计及布线指南 (Rev. A) 下载最新的英文版本 (Rev.I) PDF | HTML 26 Jul 2013
用户指南 TMS320C6000 Assembly Language Tools v 7.3 User's Guide (Rev. W) 21 Aug 2012
用户指南 TMS320C6000 Optimizing Compiler v 7.3 User's Guide (Rev. U) 21 Aug 2012
用户指南 Emulation and Trace Headers Technical Reference Manual (Rev. I) 09 Aug 2012
应用手册 Power Consumption Guide for the C66x 06 Oct 2011
用户指南 TMS320DM644x DMSoC 64-bit Timer User's Guide 01 Aug 2011
用户指南 TMS320C6000 Programmer's Guide (Rev. K) 11 Jul 2011
用户指南 TMS320DM644x DMSoC Inter-Integrated Circuit (I2C) Peripheral User's Guide (Rev. F) 25 Mar 2011
用户指南 TMS320DM644x DMSoC Video Processing Back End (VPBE) User's Guide (Rev. D) 27 Jan 2011
用户指南 TMS320DM644x DMSoC DDR2 Memory Controller User's Guide (Rev. E) 12 Jan 2011
用户指南 TMS320DM644x DMSoC EMAC/MDIO Module User's Guide (Rev. B) 23 Dec 2010
用户指南 TMS320DM644x DMSoC Video Processing Front End (VPFE) User's Guide (Rev. H) 25 Aug 2010
用户指南 TMS320DM644x DMSoC General-Purpose Input/Output (GPIO) User's Guide (Rev. A) 19 Aug 2010
应用手册 TMS320DM6446/3 Power Consumption Summary (Rev. B) 16 Aug 2010
用户指南 TMS320DM644x DMSoC Pulse-Width Modulator (PWM) User's Guide (Rev. A) 06 Aug 2010
用户指南 TMS320C64x+ DSP Megamodule Reference Guide (Rev. K) 03 Aug 2010
用户指南 TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (Rev. J) 30 Jul 2010
用户指南 TMS320DM644x DMSoC ARM Subsystem Reference Guide (Rev. C) 21 Jul 2010
应用手册 TMS320C6472 Serial RapidIO Implementation Guidelines 20 Jul 2010
应用手册 TMS320DM6446AZWT to TMX320DM6446AZWT8 Migration Guide 20 Jul 2010
用户指南 TMS320DM644x DMSoC Univesal Serial Bus (USB) Controller User's Guide (Rev. G) 02 Jun 2010
用户指南 TMS320C6000 Assembly Language Tools v 7.0 User's Guide (Rev. S) 18 Mar 2010
用户指南 TMS320C6000 Optimizing Compiler v 7.0 User's Guide (Rev. Q) 18 Mar 2010
应用手册 TMS320DM64xx USB Compliance Checklist (Rev. A) 10 Mar 2010
应用手册 Running a TMS320C64x+ Codec Across TMS320C64x+ Based DSP Platforms 24 Sep 2009
应用手册 Booting and Flashing via the DaVinci TMS320DM644x Serial Interface (Rev. A) 10 Sep 2009
应用手册 LSP 2.00 DaVinci Linux Drivers (Rev. A) 08 Jul 2009
应用手册 常用对象文件格式 (COFF) 15 Apr 2009
应用手册 Color Scan Conversion 03 Apr 2009
用户指南 TMS320DM644x DMSoC Asynchronous External Memory Interface User's Guide (Rev. C) 24 Feb 2009
用户指南 TMS320DM644x DMSoC Host Port Interface (HPI) User's Guide (Rev. B) 22 Feb 2009
用户指南 TMS320C64x+ DSP Cache User's Guide (Rev. B) 11 Feb 2009
应用手册 De-Interlacing and YUV 4:2:2 to 4:2:0 Conversion on DM6446 Using the Resizer (Rev. B) 17 Dec 2008
应用手册 Booting DaVinci EVM from NAND Flash (Rev. A) 15 Dec 2008
应用手册 5 VIN solution using DCDC Controllers, a LDO, and a Digitally Prog. Sequencer 24 Nov 2008
应用手册 TMS320DM646x to TMS320DM6467 Migration 17 Nov 2008
白皮书 See the difference:DSPs in medical imaging 31 Oct 2008
应用手册 EDMA v2.0 to EDMA v3.0 (EDMA3) Migration Guide (Rev. A) 21 Aug 2008
更多文献资料 达芬奇技术概述手册 (Rev. B) 下载英文版本 (Rev.B) 12 Aug 2008
应用手册 Understanding the Davinci Preview Engine (Rev. A) 23 Jul 2008
应用手册 Understanding TI’s PCB Routing Rule-Based DDR Timing Specification (Rev. A) 17 Jul 2008
应用手册 Understanding the Davinci Resizer (Rev. B) 17 Jul 2008
应用手册 Implementing DDR2 PCB Layout on the DM644x DMSoC (Rev. G) 16 Jun 2008
用户指南 TMS320DM644x DMSoC Multimedia Card (MMC)/Secure Digital (SD) Card Controller UG (Rev. D) 27 May 2008
用户指南 TMS320C6000 Assembly Language Tools v 6.1 User's Guide (Rev. Q) 15 May 2008
用户指南 TMS320C6000 Optimizing Compiler v 6.1 User's Guide (Rev. O) 15 May 2008
用户指南 TMS320C64x+ DSP Image/Video Processing Library (v2.0) Programmer's Reference (Rev. A) 05 May 2008
应用手册 TMS320DM644x Thermal Considerations (Rev. A) 23 Apr 2008
应用手册 TMS320DM6441 Power Consumption Summary Application Report 08 Apr 2008
用户指南 TMS320DM644x DMSoC Universal Asynchronous Receiver/Transmitter (UART) UG (Rev. A) 08 Apr 2008
用户指南 TMS320C64x+ DSP Little-Endian Library Programmer's Reference (Rev. B) 06 Mar 2008
应用手册 Creating a TMS320DM6446 Audio Encode Example Using XDC Tools (Rev. A) 26 Feb 2008
用户指南 TMS320DM644x DMSoC Enhanced Direct Memory Access (EDMA) Controller User's Guide (Rev. D) 25 Feb 2008
应用手册 Building GStreamer 11 Jan 2008
应用手册 TMS320DM6446 to TMS320DM6437 Migration Guide 05 Nov 2007
应用手册 Changing the DVEVM Memory Map 26 Sep 2007
用户指南 TMS320DM644x DMSoC VLYNQ Port User's Guide (Rev. A) 20 Sep 2007
用户指南 TMS320DM644x DMSoC Audio Serial Port (ASP) User's Guide (Rev. B) 17 Sep 2007
应用手册 Motion JPEG Demo on TMS320DM6446 (Rev. A) 11 Sep 2007
应用手册 Running Demo via ddd on the DVEVM 30 Jul 2007
应用手册 Using Static IP Between Linux Host and the DVEVM 30 Jul 2007
应用手册 CF Support on the DVEVM 25 Jul 2007
应用手册 Host USB Support on the DVEVM 20 Jul 2007
应用手册 Decode Demo for the DaVinci DVEVM/DVSDK 1.2 (Rev. A) 27 Jun 2007
应用手册 Digital Video Using DaVinci SoC 27 Jun 2007
应用手册 Encode Demo for the DaVinci DVEVM/DVSDK 1.2 (Rev. A) 27 Jun 2007
应用手册 EncodeDecode Demo for the DaVinci DVEVM/DVSDK 1.2 (Rev. A) 27 Jun 2007
应用手册 Measuring Video Quality With the TMS320DM6446 DVSDK 08 May 2007
用户指南 TMS320DM644x DMSoC Peripherals Overview Reference Guide (Rev. C) 18 Apr 2007
更多文献资料 TMS320C6000 DSP TCP/IP Stack Software (Rev. C) 04 Apr 2007
EVM 用户指南 TMS320DM644x DVEVM Windows CE v5.0 BSP Codec Engine Binary User’s Guide 23 Mar 2007
EVM 用户指南 TMS320DM644x DVEVM Windows CE v5.0 BSP Codec Engine User’s Guide 23 Mar 2007
更多文献资料 DaVinci Technology - Digital Video Innovation Product Bulletin (Rev. D) 13 Feb 2007
更多文献资料 Overview of DaVinci™ TMS320DM644x Digital Media Portfolio (Rev. B) 13 Feb 2007
用户指南 TMS320DM644x DMSoC Serial Peripheral Interface (SPI) User's Guide (Rev. A) 07 Feb 2007
应用手册 DaVinci Technology Background and Specifications (Rev. A) 04 Jan 2007
应用手册 mona 21 Dec 2006
更多文献资料 Ingenient Portable Media Player 14 Nov 2006
更多文献资料 Universal IP Player Solution from ATEME 02 Nov 2006
应用手册 DaVinci System Benchmarking 28 Sep 2006
更多文献资料 DaVinci Benchmarks Product Bulletin (Rev. A) 12 Sep 2006
应用手册 TMS320TCI648x Bootloader 06 Jul 2006
用户指南 TMS320C64x+ DSP Big-Endian Library Programmer's Reference 10 Mar 2006
用户指南 TMS320C64x+ Image/Video Processing Library Programmer's Reference 10 Mar 2006
应用手册 EDMA v3.0 (EDMA3) Migration Guide for TMS320DM644x DMSoC 03 Dec 2005
用户指南 TMS320DM644x DMSoC ATA Controller User's Guide 03 Dec 2005
用户指南 TMS320DM644x DMSoC DSP Subsystem Reference Guide 03 Dec 2005
应用手册 TMS320C64x to TMS320C64x+ CPU Migration Guide (Rev. A) 20 Oct 2005

设计和开发

如需其他信息或资源,请查看下方列表,点击标题即可进入详情页面。

调试探针

TMDSADP — 自适应时钟 JTAG 仿真适配器

TMDSADP1420 适配器 – 可将带有 14 引脚本机连接器的 TI 和第三方 XDS510 和 XDS560 类仿真器连接到带有紧凑型 (CTI) 20 引脚接头的 TMDXEVM6446 或客户电路板上。该适配器可改善信号完整性、转换电压,并可以选择提供自适应时钟。

TMDSADP1414 – 可将 TI 和第三方 XDS510 和 XDS560 类 14 引脚仿真器连接到带有 14 引脚 JTAG 接头的定制客户电路板。TMDSADP1414 适配器可改善信号完整性、转换电压,并可以选择提供自适应时钟。它与 TI 和第三方 XDS510 和 XDS560 (...)

调试探针

TMDSEMU200-U — Spectrum Digital XDS200 USB 仿真器

Spectrum Digital XDS200 是最新 XDS200 系列 TI 处理器调试探针(仿真器)的首个模型。XDS200 系列拥有超低成本 XDS100 与高性能 XDS560v2 之间的低成本与高性能的完美平衡。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS 调试探针均支持内核和系统跟踪。

Spectrum Digital XDS200 通过 TI 20 引脚连接器(带有适合 TI 14 引脚、TI 10 引脚和 ARM 20 引脚的多个适配器)连接到目标板,而通过 USB2.0 高速连接 (480Mbps) 连接到主机 PC。要在主机 (...)

TI.com 無法提供
调试探针

TMDSEMU560V2STM-U — Blackhawk XDS560v2 系统跟踪 USB 仿真器

XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针(仿真器)的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件,通过捕获相关器件级信息,获得准确的总线性能活动和吞吐量,并对内核和外设进行电源管理。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS (...)

TI.com 無法提供
调试探针

TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 系统跟踪 USB 和以太网

XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针(仿真器)的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件,通过捕获相关器件级信息,获得准确的总线性能活动和吞吐量,并对内核和外设进行电源管理。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS (...)

TI.com 無法提供
软件编解码器

DM644XCODECS 用于 DM644x 的编解码器 - 软件和文档

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into audio, video and voice applications. Click GET SOFTWARE button (above) to access the most recent, tested codec versions available. Datasheets and Release Notes (...)

支持的产品和硬件

支持的产品和硬件

产品
数字信号处理器 (DSP)
SM320DM6446-HIREL 高可靠性产品数字媒体 DM6446 处理器 TMS320DM6441 达芬奇数字媒体片上系统 TMS320DM6443 达芬奇数字媒体片上系统 TMS320DM6446 达芬奇数字媒体片上系统
下载选项
软件开发套件 (SDK)

LINUXDVSDK-DV — Linux 数字视频软件开发套件 (DVSDK) v2x/v3x - 达芬奇数字媒体处理器

2010 年 10 月生效 - Linux DVSDK v4 已发布。对于上面未列出的 DaVinci™ 器件,请在 TI.com 上搜索您的器件型号;此产品页面将提供指向您当前 DVSDK 的链接。

借助 Linux™ 数字视频软件开发套件 (DVSDK),DaVinci 系统集成人员能快速开发可在 DaVinci 系列不同器件间轻松移植的 Linux 多媒体应用。每个 DVSDK 都包含一套预先测试的操作系统、应用框架和具有示例程序的编解码器库,这些示例程序演示了从外设流入和流出音频和视频数据的实时解码和编码过程。对于配备 DSP 内核的 DaVinci 器件,DVSDK (...)

应用软件和框架

TMDMFP — 多媒体框架产品 (MFP) - 编解码器引擎,框架组件和 xDAIS

Multimedia Framework Products (MFP)

A major advantage of programmable DSPs over fixed-function devices is their ability to accelerate multiple multimedia functions in a single device. TI multimedia framework products are designed to enable users to easily share a DSP between algorithms by handling (...)

驱动程序或库

SPRC122 — C62x/C64x 快速运行时支持 (RTS) 库

C62x/64x FastRTS Library 是优化型浮点函数库,适用于使用 TMS320C62x 或 TMS320C64x 器件的 C 语言编程器。这些例程通常用于计算密集型实时应用,在这些应用中,提高执行速度至关重要。通过将当前的浮点库 (RTS) 函数替换为 FastRTS Library,可以在不重写现有代码的情况下大大加快执行速度。

该版本还包括 FastRTS Library 中可用函数子集的 C 语言实施。C 代码可让用户内联这些函数并获得更高性能。

特性

单精度和双精度数学函数 单精度和双精度转换函数
浮点加法 将浮点值转换为 32 位带符号整数值
将 32 位带符号整数值转换为浮点值
(...)
驱动程序或库

SPRC831 — 视频影像协处理器 (VICP) 信号处理库

德州仪器 (TI) VICP 信号处理库是高度优化的软件算法的集合,它在 VICP 硬件加速器上运行。该库使应用开发人员能够有效地利用 VICP 性能,而无需将宝贵时间花在开发用于加速器的软件上。具有成熟的可用性和性能优化算法,VICP 信号处理库能够显著降低应用开发时间。DSP 上的自由 MIPS 使应用开发人员能够将更多差异化功能包含在最终应用中。

VICP 硬件加速器是一个并行 MAC 引擎。通过执行各种计算密集型任务,该加速器能够非常有效地提高 DSP 的性能,这完全归功于它的灵活架构。

VICP 支持各种算法以便能提供其它 DSP 资源
  • 矩阵运算/阵列运算:
    • (...)
驱动程序或库

TELECOMLIB — 用于 TMS320C64x+ 和 TMS320C55x 处理器的电信和媒体库 - FAXLIB、VoLIB 和 AEC/AER

Voice Library - VoLIB provides components that, together, facilitate the development of the signal processing chain for Voice over IP applications such as infrastructure, enterprise, residential gateways and IP phones. Together with optimized implementations of ITU-T voice codecs, that can be (...)
软件编解码器

C64XPLUSCODECS — 编解码器 - 视频和语音 - 基于 C64x+ 的器件(OMAP35x、C645x、C647x、DM646、DM644x 和 DM643x)

TI 编解码器免费提供,附带生产许可且现在可供下载。全部经过生产测试,可轻松地集成到音频、视频和语音应用中 单击“获取软件”按钮(上方),以获取经过测试的最新编解码器版本。该页面及每个安装程序中都包含有数据表和发布说明。

 

 

其它信息:

软件编解码器

TMDXDAISXDM — eXpressDSP 算法标准 – xDAIS 开发者套件和 xDM

xDAIS and xDM

The eXpressDSP™ Algorithm Interoperability Standard (xDAIS) and the eXpressDSP Digital Media (xDM) standard fully leverage the ability of DSPs to perform a wide range of multimedia functions on a single device. eXpressDSP compliance is achieved by adhering to these standards. To (...)

仿真模型

DM6446 ZWT IBIS Model (Rev. C)

SPRM202C.ZIP (112 KB) - IBIS Model
仿真模型

DM6446 ZWT BSDL Model

SPRM203.ZIP (10 KB) - BSDL Model
仿真模型

DM6446 ZWT BSDL version 2.1 Model (Rev. A)

SPRM325A.ZIP (8 KB) - BSDL Model
仿真模型

DM6446_DDR2 ZWT IBIS Model

SPRM450.ZIP (50 KB) - IBIS Model
设计工具

PROCESSORS-3P-SEARCH — Arm-based MPU, arm-based MCU and DSP third-party search tool

TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)
封装 引脚数 下载
NFBGA (ZWT) 361 了解详情

订购和质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 认证摘要
  • 持续可靠性监测

推荐产品可能包含与 TI 此产品相关的参数、评估模块或参考设计。

支持与培训

视频