TMS320C6414T
- Highest-Performance Fixed-Point DSPs
- 1.67-/1.39-/1.17-/1-ns Instruction Cycle
- 600-/720-/850-MHz, 1-GHz Clock Rate
- Eight 32-Bit Instructions/Cycle
- Twenty-Eight Operations/Cycle
- 4800, 5760, 6800, 8000 MIPS
- Fully Software-Compatible With C62x™
- C6414/15/16 Devices Pin-Compatible
- Extended Temperature Devices Available
- VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core
- Eight Highly Independent Functional Units With VelociTI.2™ Extensions:
- Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
- Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
- Non-Aligned Load-Store Architecture
- 64 32-Bit General-Purpose Registers
- Instruction Packing Reduces Code Size
- All Instructions Conditional
- Eight Highly Independent Functional Units With VelociTI.2™ Extensions:
- Instruction Set Features
- Byte-Addressable (8-/16-/32-/64-Bit Data)
- 8-Bit Overflow Protection
- Bit-Field Extract, Set, Clear
- Normalization, Saturation, Bit-Counting
- VelociTI.2™ Increased Orthogonality
- VCP [C6416T Only]
- Supports Over 833 7.95-Kbps AMR
- Programmable Code Parameters
- TCP [C6416T Only]
- Supports up to 10 2-Mbps or 60 384-Kbps 3GPP (6 Iterations)
- Programmable Turbo Code and Decoding Parameters
- L1/L2 Memory Architecture
- 128K-Bit (16K-Byte) L1P Program Cache(Direct Mapped)
- 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
- 8M-Bit (1024K-Byte) L2 Unified Mapped RAM/Cache (Flexible Allocation)
- Two External Memory Interfaces (EMIFs)
- One 64-Bit (EMIFA), One 16-Bit (EMIFB)
- Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
- 1280M-Byte Total Addressable External Memory Space
- Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
- Host-Port Interface (HPI)
- User-Configurable Bus Width (32-/16-Bit)
- 32-Bit/33-MHz, 3.3-V PCI Master/Slave Interface Conforms to PCI Specification 2.2 [C6415T/C6416T]
- Three PCI Bus Address Registers:
Prefetchable Memory
Non-Prefetchable Memory I/O - Four-Wire Serial EEPROM Interface
- PCI Interrupt Request Under DSP Program Control
- DSP Interrupt Via PCI I/O Cycle
- Three PCI Bus Address Registers:
- Three Multichannel Buffered Serial Ports
- Direct Interface to T1/E1, MVIP, SCSA Framers
- Up to 256 Channels Each
- ST-Bus-Switching-, AC97-Compatible
- Serial Peripheral Interface (SPI) Compatible (Motorola™)
- Three 32-Bit General-Purpose Timers
- UTOPIA [C6415T/C6416T]
- UTOPIA Level 2 Slave ATM Controller
- 8-Bit Transmit and Receive Operations up to 50 MHz per Direction
- User-Defined Cell Format up to 64 Bytes
- Sixteen General-Purpose I/O (GPIO) Pins
- Flexible PLL Clock Generator
- IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
- 532-Pin Ball Grid Array (BGA) Package (GLZ and ZLZ Suffixes), 0.8-mm Ball Pitch
- 0.09-µm/7-Level Cu Metal Process (CMOS)
- 3.3-V I/Os, 1.1-V Internal (600 MHz)
- 3.3-V I/Os, 1.2-V Internal (720/850 MHZ, 1 GHz)
C62x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
C62x, VelociTI.2, VelociTI, and TMS320C64x are trademarks of Texas Instruments.
Motorla is a registered trademark of the Motorola, Inc.
The TMS320C64x™ DSPs (including the TMS320C6414T, TMS320C6415T, and TMS320C6416T devices) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320C64x™ (C64x™) device is based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas Instruments (TI), making these DSPs an excellent choice for wireless infrastructure applications. The C64x™ is a code-compatible member of the C6000™ DSP platform.
With performance of up to 8000 million instructions per second (MIPS) at a clock rate of 1 GHz, the C64x devices offer cost-effective solutions to high-performance DSP programming challenges. The C64x™ DSPs possess the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x. DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional unitstwo multipliers for a 32-bit result and six arithmetic logic units (ALUs) with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units include new instructions to accelerate the performance in key applications and extend the parallelism of the VelociTI™ architecture. The C64x can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 4000 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 8000 MMACS. The C64x DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000™ DSP platform devices.
The C6416T device has two high-performance embedded coprocessors [Viterbi Decoder Coprocessor (VCP) and Turbo Decoder Coprocessor (TCP)] that significantly speed up channel-decoding operations on-chip. The VCP operating at CPU clock divided-by-4 can decode over 833 7.95-Kbps adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels. The VCP supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 1/2, 1/3, and 1/4, and flexible polynomials, while generating hard decisions or soft decisions. The TCP operating at CPU clock divided-by-2 can decode up to sixty 384-Kbps or ten 2-Mbps turbo encoded channels (assuming 6 iterations). The TCP implements the max*log-map algorithm and is designed to support all polynomials and rates required by Third-Generation Partnership Projects (3GPP and 3GPP2), with fully programmable frame length and turbo interleaver. Decoding parameters such as the number of iterations and stopping criteria are also programmable. Communications between the VCP/TCP and the CPU are carried out through the EDMA controller.
The C64x uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 8-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory or combinations of cache (up to 256K bytes) and mapped memory. The peripheral set includes three multichannel buffered serial ports (McBSPs); an 8-bit Universal Test and Operations PHY Interface for Asynchronous Transfer Mode (ATM) Slave [UTOPIA Slave] port [C6415T/C6416T only]; three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component interconnect (PCI) [C6415T/C6416T only]; a general-purpose input/output port (GPIO) with 16 GPIO pins; and two glueless external memory interfaces (64-bit EMIFA and 16-bit EMIFB), both of which are capable of interfacing to synchronous and asynchronous memories and peripherals.
The C64x has a complete set of development tools which includes: an advanced C compiler with C64x-specific enhancements, an assembly optimizer to simplify programming and scheduling, and a Windows. debugger interface for visibility into source code execution.
TMS320C6000, C64x, and C6000 are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft
Corporation.
Other trademarks are the property of their respective owners.
Throughout the remainder of this document, the TMS320C6414T, TMS320C6415T, and TMS320C6416T shall be referred to as TMS320C64x or C64x where generic, and where specific, their individual full device part numbers will be used or abbreviated as C6414T, C6415T, or C6416T.
These C64x™ devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix "A" in front of a signal name indicates it is an EMIFA signal whereas a prefix "B" in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted from the signal name.
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技术文档
类型 | 标题 | 下载最新的英语版本 | 日期 | |||
---|---|---|---|---|---|---|
* | 数据表 | TMS320C6414T, TMS320C6415T, TMS320C6416T Fixed-Point Digital Signal Processors 数据表 (Rev. M) | 2009年 4月 6日 | |||
* | 勘误表 | TMS320C6414T/C6415T/C6416T DSPs Silicon Errata (Silicon Revision 2.0, 1.0) (Rev. J) | 2012年 7月 26日 | |||
应用手册 | 如何将 CCS 3.x 工程迁移至最新的 Code Composer Studio™ (CCS) (Rev. A) | 英语版 (Rev.A) | PDF | HTML | 2021年 5月 19日 | ||
用户指南 | Emulation and Trace Headers Technical Reference Manual (Rev. I) | 2012年 8月 9日 | ||||
应用手册 | Introduction to TMS320C6000 DSP Optimization | 2011年 10月 6日 | ||||
应用手册 | Migrating from TMS320C6416/15/14 to TMS320C6416T/15T/14T (Rev. B) | 2008年 2月 22日 | ||||
应用手册 | TMS320C6414T/15T/16T Power Consumption Summary (Rev. A) | 2008年 2月 18日 | ||||
产品概述 | TMS320C6000 DSP TCP/IP Stack Software (Rev. C) | 2007年 4月 4日 | ||||
应用手册 | TMS320C6000 EDMA IO Scheduling and Performance | 2004年 3月 5日 | ||||
应用手册 | TMS320C64x DSP Host Port Interface (HPI) Performance | 2003年 10月 24日 |
设计和开发
如需其他信息或资源,请点击以下任一标题进入详情页面查看(如有)。
TMDSEMU560V2STM-U — XDS560™ 软件 v2 系统跟踪 USB 调试探针
XDS560v2 是 XDS560™ 系列调试探针中性能非常出色的产品,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。请注意,它不支持串行线调试 (SWD)。
所有 XDS 调试探针在所有具有嵌入式跟踪缓冲器 (ETB) 的 ARM 和 DSP 处理器中均支持内核和系统跟踪。对于引脚上的跟踪,需要 XDS560v2 PRO TRACE。
XDS560v2 通过 MIPI HSPT 60 引脚连接器(带有多个用于 TI 14 引脚、TI 20 引脚和 ARM 20 引脚的适配器)连接到目标板,并通过 USB2.0 高速 (480Mbps) (...)
TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 系统跟踪 USB 和以太网
XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针(仿真器)的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。
XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件,通过捕获相关器件级信息,获得准确的总线性能活动和吞吐量,并对内核和外设进行电源管理。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS (...)
SPRC122 — C62x/C64x Fast Run-Time Support Library
The C62x/64x FastRTS Library is an optimized, floating-point function library for C programmers using either TMS320C62x or TMS320C64x devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By replacing the current (...)
支持的产品和硬件
产品
数字信号处理器 (DSP)
SPRC264 — TMS320C6000 图像库 (IMGLIB)
SPRC265 — TMS320C6000 DSP 库 (DSPLIB)
TELECOMLIB — 用于 TMS320C64x+ 和 TMS320C55x 处理器的电信和媒体库 - FAXLIB、VoLIB 和 AEC/AER
CCSTUDIO — Code Composer Studio 集成式开发环境 (IDE)
Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It is comprised of a rich suite of tools used to build, debug, analyze and optimize embedded applications. Code Composer Studio is available across Windows®, Linux® and macOS® platforms.
(...)
支持的产品和硬件
此设计资源支持这些类别中的大部分产品。
查看产品详情页,验证是否能提供支持。
-
parametric-filter 数字信号处理器 (DSP) -
parametric-filter 基于 Arm 的处理器 -
parametric-filter MSP430 微控制器 -
parametric-filter C2000 实时微控制器 -
parametric-filter 基于 Arm 的微控制器 -
parametric-filter 信号调节器 -
parametric-filter 毫米波雷达传感器 -
parametric-filter Zigbee 产品 -
parametric-filter Wi-Fi 产品 -
parametric-filter Thread 产品 -
parametric-filter 其他无线技术 -
parametric-filter 低于 1GHz 产品 -
parametric-filter 多协议产品 -
parametric-filter 蓝牙产品 -
parametric-filter 数字电源隔离式控制器
封装 | 引脚 | CAD 符号、封装和 3D 模型 |
---|---|---|
FCBGA (CLZ) | 532 | Ultra Librarian |
FCBGA (GLZ) | 532 | Ultra Librarian |
订购和质量
- RoHS
- REACH
- 器件标识
- 引脚镀层/焊球材料
- MSL 等级/回流焊峰值温度
- MTBF/时基故障估算
- 材料成分
- 鉴定摘要
- 持续可靠性监测
- 制造厂地点
- 封装厂地点
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