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DSP 6 C64x+ DSP MHz (Max) 700 CPU 32-/64-bit Operating system DSP/BIOS Ethernet MAC 10/100/1000 Rating Military Operating temperature range (C) -40 to 100
DSP 6 C64x+ DSP MHz (Max) 700 CPU 32-/64-bit Operating system DSP/BIOS Ethernet MAC 10/100/1000 Rating Military Operating temperature range (C) -40 to 100
FCBGA (GTZ) 737 576 mm² 24 x 24
  • Six On-Chip TMS320C64x+ Megamodules
  • Endianess: Little Endian, Big Endian
  • C64x+ Megamodule Main Features:
    • High-Performance, Fixed-Point TMS320C64x+ DSP
    • 500/625/700 MHz
    • Eight 32-Bit Instructions/Cycle
    • 4000 MIPS/MMACS (16-Bits) at 500 MHz
    • Dedicated SPLOOP Instruction
    • Compact Instructions (16-Bit)
    • Instruction Set Enhancements
    • Exception Handling
    • L1/L2 Memory Architecture:
      • 256K-Bit (32K-Byte) L1P Program RAM/Cache
        [Direct Mapped, Flexible Allocation]
      • 256K-Bit (32K-Byte) L1D RAM/Cache
        [2-Way Set-Associative, Flexible Allocation]
      • 4.75M-Bit (608K-Byte) L2 Unified Mapped RAM/Cache
        [4-Way Set-Associative, Flexible Allocation]
      • L1P Memory Controller
      • L1D Memory Controller
      • L2 Memory Controller
    • Time Stamp Counter
    • One 64-Bit General-Purpose/Watchdog Timer
  • Shared Peripherals and Interfaces
    • EDMA Controller (64 Independent Channels)
    • Shared Memory Architecture
      • Shared L2 Memory Controller
      • 768K-Byte of RAM
      • Boot ROM
    • Three Telecom Serial Interface Ports (TSIPs)
      • Each TSIP is 8 Links of 8 Mbps per Direction
    • 32-Bit DDR2 Memory Controller (DDR2-533 SDRAM)
      • 256 M-Byte × 2 Addressable Memory Space
    • Two 1x Serial RapidIO® Links, v1.2 Compliant
      • 1.25-, 2.5-, 3.125-Gbps Link Rates
      • Message Passing, DirectIO Support, Error Management
        Extensions, and Congestion Control
      • IEEE 1149.6 Compliant I/Os
    • UTOPIA
      • UTOPIA Level 2 Slave ATM Controller
      • 8/16-Bit Transmit and Receive Operations up to
        50 MHz per Direction
      • User-Defined Cell Format up to 64 Bytes
    • Two 10/100/1000 Mb/s Ethernet MACs (EMACs)
      • Both EMACs are IEEE 802.3 Compliant
      • EMAC0 Supports:
        • MII, RMII, SS-SMII, GMII, and RGMII
        • 8 Independent Transmit (TX) Channels
        • 8 Independent Receive (RX) Channels
      • EMAC1 Supports:
        • RMII, SS-SMII and RGMII
        • 8 Independent Transmit (TX) Channels
        • 8 Independent Receive (RX) Channels
      • Both EMACs (EMAC0 and EMAC1) Share MDIO Interface
    • 16-Bit Host-Port Interface (HPI)
    • One Inter-Integrated Circuit (I2C) Bus
    • Six Shared 64-Bit General-Purpose Timers
  • System PLL and PLL Controller
  • Secondary PLL and PLL Controller, Dedicated to EMAC
  • Third PLL and PLL Controller Dedicated to DDR2 Memory Controller
  • 16 General-Purpose I/O (GPIO) Pins
  • IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible
  • 737-Pin Ball Gird Array (BGA) Package (ZTZ/GTZ Suffix),
    0.8-mm Ball Pitch
  • 0.09-µm/7-Level Cu Metal Process (CMOS)
  • 3.3-, 1.8-, 1.5-, 1.2-V I/O Supplies
  • 1.0-/1.1-, 1.2-V Core Supplies
  • Commercial Temperature [0°C to 85°C]
  • Extended Temperature [–40°C to 100°C]
  • Only 625-MHz Device Offered in GTZ Package

  • Six On-Chip TMS320C64x+ Megamodules
  • Endianess: Little Endian, Big Endian
  • C64x+ Megamodule Main Features:
    • High-Performance, Fixed-Point TMS320C64x+ DSP
    • 500/625/700 MHz
    • Eight 32-Bit Instructions/Cycle
    • 4000 MIPS/MMACS (16-Bits) at 500 MHz
    • Dedicated SPLOOP Instruction
    • Compact Instructions (16-Bit)
    • Instruction Set Enhancements
    • Exception Handling
    • L1/L2 Memory Architecture:
      • 256K-Bit (32K-Byte) L1P Program RAM/Cache
        [Direct Mapped, Flexible Allocation]
      • 256K-Bit (32K-Byte) L1D RAM/Cache
        [2-Way Set-Associative, Flexible Allocation]
      • 4.75M-Bit (608K-Byte) L2 Unified Mapped RAM/Cache
        [4-Way Set-Associative, Flexible Allocation]
      • L1P Memory Controller
      • L1D Memory Controller
      • L2 Memory Controller
    • Time Stamp Counter
    • One 64-Bit General-Purpose/Watchdog Timer
  • Shared Peripherals and Interfaces
    • EDMA Controller (64 Independent Channels)
    • Shared Memory Architecture
      • Shared L2 Memory Controller
      • 768K-Byte of RAM
      • Boot ROM
    • Three Telecom Serial Interface Ports (TSIPs)
      • Each TSIP is 8 Links of 8 Mbps per Direction
    • 32-Bit DDR2 Memory Controller (DDR2-533 SDRAM)
      • 256 M-Byte × 2 Addressable Memory Space
    • Two 1x Serial RapidIO® Links, v1.2 Compliant
      • 1.25-, 2.5-, 3.125-Gbps Link Rates
      • Message Passing, DirectIO Support, Error Management
        Extensions, and Congestion Control
      • IEEE 1149.6 Compliant I/Os
    • UTOPIA
      • UTOPIA Level 2 Slave ATM Controller
      • 8/16-Bit Transmit and Receive Operations up to
        50 MHz per Direction
      • User-Defined Cell Format up to 64 Bytes
    • Two 10/100/1000 Mb/s Ethernet MACs (EMACs)
      • Both EMACs are IEEE 802.3 Compliant
      • EMAC0 Supports:
        • MII, RMII, SS-SMII, GMII, and RGMII
        • 8 Independent Transmit (TX) Channels
        • 8 Independent Receive (RX) Channels
      • EMAC1 Supports:
        • RMII, SS-SMII and RGMII
        • 8 Independent Transmit (TX) Channels
        • 8 Independent Receive (RX) Channels
      • Both EMACs (EMAC0 and EMAC1) Share MDIO Interface
    • 16-Bit Host-Port Interface (HPI)
    • One Inter-Integrated Circuit (I2C) Bus
    • Six Shared 64-Bit General-Purpose Timers
  • System PLL and PLL Controller
  • Secondary PLL and PLL Controller, Dedicated to EMAC
  • Third PLL and PLL Controller Dedicated to DDR2 Memory Controller
  • 16 General-Purpose I/O (GPIO) Pins
  • IEEE-1149.1 (JTAG™) Boundary-Scan-Compatible
  • 737-Pin Ball Gird Array (BGA) Package (ZTZ/GTZ Suffix),
    0.8-mm Ball Pitch
  • 0.09-µm/7-Level Cu Metal Process (CMOS)
  • 3.3-, 1.8-, 1.5-, 1.2-V I/O Supplies
  • 1.0-/1.1-, 1.2-V Core Supplies
  • Commercial Temperature [0°C to 85°C]
  • Extended Temperature [–40°C to 100°C]
  • Only 625-MHz Device Offered in GTZ Package

The SM320C6472 device is a Texas Instruments next-generation fixed-point digital signal processor (DSP) targeting high-performance computing applications, including high-end industrial, mission-critical, high-end image and video, communication, media gateways, and remote access servers. This device was designed with these applications in mind. A common key requirement of these applications is the availability of large on-chip memories to handle vast amounts of data during processing. With 768K-Byte of shared RAM and 608K-Byte local L2 RAM per C64x+ Megamodule, the SM320C6472 device can eliminate the need for external memory, thereby reducing system power dissipation and system cost and optimizing board density.

The SM320C6472 device has six optimized TMS320C64x+™ megamodules, which combine high performance with the lowest power dissipation per port. The TMS320C6472 device includes three different speeds: 500 MHz, 625 MHz, and 700 MHz. The C64x+ megamodules are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The C64x+ megamodule is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making devices like SM320C6472 an excellent choice for applications including video and telecom infrastructure, imaging/medical, and wireless infrastructure (WI). The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform.

The C64x+ megamodule core employs eight functional units, two register files, and two data paths. Like the earlier C6000 devices, two of these eight functional units are multipliers or .M units. Each C64x+ megamodule core .M unit doubles the multiply throughput versus the C64x core by performing four 16-bit x 16-bit multiply-accumulates (MACs) every clock cycle. Thus, eight 16-bit x 16-bit MACs can be executed every cycle on the C64x+ core. At a 500-MHz clock rate, this means 4000 16-bit MMACs can occur every second. Moreover, each multiplier on the C64x+ megamodule core can compute one 32-bit x 32-bit MAC or four 8-bit x 8-bit MACs every clock cycle.

The C64x+ megamodule integrates a large amount of on-chip memory organized as a two-level memory system. The level-1 (L1) program and data memories on this C64x+ megamodule are 32KB each. This memory can be configured as mapped RAM, cache, or some combination of the two. When configured as cache, L1 program (L1P) is a direct mapped cache where as L1 data (L1D) is a two-way set associative cache. The level 2 (L2) memory is shared between program and data space and is 608K-Byte in size. L2 memory can also be configured as mapped RAM, cache, or some combination of the two. The C64x+ megamodule also has a 32-bit peripheral configuration (CFG) port, an internal DMA (IDMA) controller, a system component with reset/boot control, interrupt/exception control, a power-down control, and a free-running 32-bit timer for time stamp.

The peripheral set includes: three Telecom Serial Interface Port (TSIPs); an 16/8 bit Universal Test and Operations PHY Interface for Asynchronous Transfer Mode (ATM) Slave [UTOPIA Slave] port; two 10/100/1000 Ethernet media access controllers (EMACs), which provide an efficient interface between the C6472 DSP core processor and the network; a management data input/output (MDIO) module (shared by both EMACs) that continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system; a Serial RapidIO® with two 1x lanes and support for packet forwarding; a 32-bit DDR2 SDRAM interface; 12 64-bit general-purpose timers; an inter-integrated circuit bus module (I2C); 16 general-purpose input/output ports (GPIO) with programmable interrupt/event generation modes; and a 16-bit multiplexed host-port interface (HPI16).

The C6472 device has a complete set of development tools which includes: a C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

The SM320C6472 device is a Texas Instruments next-generation fixed-point digital signal processor (DSP) targeting high-performance computing applications, including high-end industrial, mission-critical, high-end image and video, communication, media gateways, and remote access servers. This device was designed with these applications in mind. A common key requirement of these applications is the availability of large on-chip memories to handle vast amounts of data during processing. With 768K-Byte of shared RAM and 608K-Byte local L2 RAM per C64x+ Megamodule, the SM320C6472 device can eliminate the need for external memory, thereby reducing system power dissipation and system cost and optimizing board density.

The SM320C6472 device has six optimized TMS320C64x+™ megamodules, which combine high performance with the lowest power dissipation per port. The TMS320C6472 device includes three different speeds: 500 MHz, 625 MHz, and 700 MHz. The C64x+ megamodules are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The C64x+ megamodule is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making devices like SM320C6472 an excellent choice for applications including video and telecom infrastructure, imaging/medical, and wireless infrastructure (WI). The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform.

The C64x+ megamodule core employs eight functional units, two register files, and two data paths. Like the earlier C6000 devices, two of these eight functional units are multipliers or .M units. Each C64x+ megamodule core .M unit doubles the multiply throughput versus the C64x core by performing four 16-bit x 16-bit multiply-accumulates (MACs) every clock cycle. Thus, eight 16-bit x 16-bit MACs can be executed every cycle on the C64x+ core. At a 500-MHz clock rate, this means 4000 16-bit MMACs can occur every second. Moreover, each multiplier on the C64x+ megamodule core can compute one 32-bit x 32-bit MAC or four 8-bit x 8-bit MACs every clock cycle.

The C64x+ megamodule integrates a large amount of on-chip memory organized as a two-level memory system. The level-1 (L1) program and data memories on this C64x+ megamodule are 32KB each. This memory can be configured as mapped RAM, cache, or some combination of the two. When configured as cache, L1 program (L1P) is a direct mapped cache where as L1 data (L1D) is a two-way set associative cache. The level 2 (L2) memory is shared between program and data space and is 608K-Byte in size. L2 memory can also be configured as mapped RAM, cache, or some combination of the two. The C64x+ megamodule also has a 32-bit peripheral configuration (CFG) port, an internal DMA (IDMA) controller, a system component with reset/boot control, interrupt/exception control, a power-down control, and a free-running 32-bit timer for time stamp.

The peripheral set includes: three Telecom Serial Interface Port (TSIPs); an 16/8 bit Universal Test and Operations PHY Interface for Asynchronous Transfer Mode (ATM) Slave [UTOPIA Slave] port; two 10/100/1000 Ethernet media access controllers (EMACs), which provide an efficient interface between the C6472 DSP core processor and the network; a management data input/output (MDIO) module (shared by both EMACs) that continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system; a Serial RapidIO® with two 1x lanes and support for packet forwarding; a 32-bit DDR2 SDRAM interface; 12 64-bit general-purpose timers; an inter-integrated circuit bus module (I2C); 16 general-purpose input/output ports (GPIO) with programmable interrupt/event generation modes; and a 16-bit multiplexed host-port interface (HPI16).

The C6472 device has a complete set of development tools which includes: a C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

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* 数据表 Fixed-Point Digital Signal Processor. 数据表 (Rev. B) 2010年 10月 7日
技术文章 Bringing the next evolution of machine learning to the edge 2018年 11月 27日
技术文章 How quality assurance on the Processor SDK can improve software scalability 2018年 8月 22日
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应用手册 Power Consumption Guide for the C66x 2011年 10月 6日

设计与开发

有关其他条款或所需资源,请点击下面的任何链接来查看详情页面。

调试探针

TMDSEMU200-U — Spectrum Digital XDS200 USB 仿真器

Spectrum Digital XDS200 是最新 XDS200 系列 TI 处理器调试探针(仿真器)的首个模型。XDS200 系列拥有超低成本 XDS100 与高性能 XDS560v2 之间的低成本与高性能的完美平衡。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS 调试探针均支持内核和系统跟踪。

Spectrum Digital XDS200 通过 TI 20 引脚连接器(带有适合 TI 14 引脚、TI 10 引脚和 ARM 20 引脚的多个适配器)连接到目标板,而通过 USB2.0 高速连接 (480Mbps) 连接到主机 PC。要在主机 PC 上运行,还需要 Code Composer Studio™ IDE 许可证。

(...)

现货
数量限制: 3
调试探针

TMDSEMU560V2STM-U — Blackhawk XDS560v2 系统跟踪 USB 仿真器

XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针(仿真器)的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件,通过捕获相关器件级信息,获得准确的总线性能活动和吞吐量,并对内核和外设进行电源管理。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS 调试探针均支持内核和系统跟踪。

Blackhawk XDS560v2 System Trace 通过 MIPI HSPT 60 引脚连接器(带有适合 TI 14 引脚、TI 20 引脚和 ARM 20 (...)

现货
数量限制: 1
调试探针

TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 系统跟踪 USB 和以太网

XDS560v2 System Trace 是 XDS560v2 系列高性能 TI 处理器调试探针(仿真器)的第一种型号。XDS560v2 是 XDS 系列调试探针中性能最高的一款,同时支持传统 JTAG 标准 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。

XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件,通过捕获相关器件级信息,获得准确的总线性能活动和吞吐量,并对内核和外设进行电源管理。此外,对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器,所有 XDS 调试探针均支持内核和系统跟踪。

Spectrum Digital XDS560v2 System Trace 通过 MIPI HSPT 60 引脚连接器(适合 TI 14 引脚、TI 20 引脚、ARM 20 引脚和 TI 60 (...)

现货
数量限制: 1
驱动程序或库

SPRC265 — TMS320C6000 DSP 库 (DSPLIB)

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
驱动程序或库

TELECOMLIB — 用于 TMS320C64x+ 和 TMS320C55x 处理器的电信和媒体库 - FAXLIB、VoLIB 和 AEC/AER

IDE、配置、编译器或调试器

CCSTUDIO-KEYSTONE — 适用于多核处理器的 Code Composer Studio (CCS) 集成开发环境 (IDE)

下载最新 Code Composer Studio 版本

Code Composer Studio™ - 用于包括 KeyStone 处理器在内的多核 DSP 和 ARM 的集成开发环境

 

  • CCS 最新版本 - 单击下面可以下载指定主机平台的 CCSv6。
  • 其他下载 - 有关完整下载的列表,请访问 CCS 下载站点
  • 免费使用 CCS - 将生成免费许可证,支持使用低成本的 XDS100 调试探针或带有板载调试探针的电路板。还为全功能评估许可证提供 90 天的延长期。

 

Windows        Linux     

Code Composer Studio 是一种集成开发环境 (IDE),支持 TI 的微控制器和嵌入式处理器产品系列。Code Composer Studio 包含一整套用于开发和调试嵌入式应用的工具。它包含了用于优化的 C/C++ 编译器、源码编辑器、项目构建环境、调试器、描述器以及多种其他功能。直观的 IDE 提供了单个用户界面,可帮助您完成应用开发流程的每个步骤。熟悉的工具和界面使用户能够比以前更快地入手。Code Composer Studio 将 Eclipse 软件框架的优点和 TI 先进的嵌入式调试功能相结合,为嵌入式开发人员提供了一个引人注目、功能丰富的开发环境。

其他信息

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设计工具

PROCESSORS-3P-SEARCH — Arm-based MPU, arm-based MCU and DSP third-party search tool

TI has partnered with companies to offer a wide range of software, tools, and SOMs using TI processors to accelerate your path to production. Download this search tool to quickly browse our third-party solutions and find the right third-party to meet your needs. The software, tools and modules (...)
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FCBGA (GTZ) 737 了解详情

订购与质量

包含信息:
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/FIT 估算
  • 材料成分
  • 认证摘要
  • 持续可靠性监测

支持与培训

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