SLAU847F October   2022  â€“ March 2026 MSPM0L1105 , MSPM0L1106 , MSPM0L1116 , MSPM0L1117 , MSPM0L1227 , MSPM0L1227-Q1 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346 , MSPM0L2116 , MSPM0L2117 , MSPM0L2227 , MSPM0L2227-Q1 , MSPM0L2228 , MSPM0L2228-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation
    5.     Support Resources
    6.     Trademarks
  3. 1 Architecture
    1. 1.1 Architecture Overview
    2. 1.2 Bus Organization
    3. 1.3 Platform Memory Map
      1. 1.3.1 Code Region
      2. 1.3.2 SRAM Region
      3. 1.3.3 Peripheral Region
      4. 1.3.4 Subsystem Region
      5. 1.3.5 System PPB Region
    4. 1.4 Boot Configuration
      1. 1.4.1 Configuration Memory (NONMAIN)
        1. 1.4.1.1 CRC-Backed Configuration Data
        2. 1.4.1.2 16-bit Pattern Match for Critical Fields
      2. 1.4.2 Boot Configuration Routine (BCR)
        1. 1.4.2.1 Serial Wire Debug Related Policies
          1. 1.4.2.1.1 SWD Security Level 0
          2. 1.4.2.1.2 SWD Security Level 1
          3. 1.4.2.1.3 SWD Security Level 2
        2. 1.4.2.2 SWD Mass Erase and Factory Reset Commands
        3. 1.4.2.3 Flash Memory Protection and Integrity Related Policies
          1. 1.4.2.3.1 Locking the Application (MAIN) Flash Memory
          2. 1.4.2.3.2 Locking the Configuration (NONMAIN) Flash Memory
          3. 1.4.2.3.3 Static Write Protection NONMAIN Fields
        4. 1.4.2.4 Application CRC Verification
        5. 1.4.2.5 Fast Boot
        6. 1.4.2.6 Bootstrap Loader (BSL) Enable/Disable Policy
          1. 1.4.2.6.1 BSL Enable
      3. 1.4.3 Bootstrap Loader (BSL)
        1. 1.4.3.1 GPIO Invoke
        2. 1.4.3.2 Bootstrap Loader (BSL) Security Policies
          1. 1.4.3.2.1 BSL Access Password
          2. 1.4.3.2.2 BSL Read-out Policy
          3. 1.4.3.2.3 BSL Security Alert Policy
        3. 1.4.3.3 Application Version
        4. 1.4.3.4 BSL Triggered Mass Erase and Factory Reset
      4. 1.4.4 NONMAIN Layout Types
      5. 1.4.5 NONMAIN_TYPEA Registers
      6. 1.4.6 NONMAIN_TYPEC Registers
      7. 1.4.7 NONMAIN_TYPEE Registers
    5. 1.5 Factory Constants
      1. 1.5.1 FACTORYREGION Layout Types
      2. 1.5.2 FACTORYREGION_TYPEA Registers
      3. 1.5.3 FACTORYREGION_TYPEC Registers
      4. 1.5.4 FACTORYREGION_TYPED Registers
      5. 1.5.5 FACTORYREGION_TYPEE Registers
  4. 2 PMCU
    1. 2.1 PMCU Overview
      1. 2.1.1 Power Domains
      2. 2.1.2 Operating Modes
        1. 2.1.2.1 RUN Mode
        2. 2.1.2.2 SLEEP Mode
        3. 2.1.2.3 STOP Mode
        4. 2.1.2.4 STANDBY Mode
        5. 2.1.2.5 SHUTDOWN Mode
        6. 2.1.2.6 Supported Functionality by Operating Mode
        7. 2.1.2.7 Suspended Low-Power Mode Operation
    2. 2.2 Power Management (PMU)
      1. 2.2.1 Power Supply
      2. 2.2.2 Core Regulator
      3. 2.2.3 Supply Supervisors
        1. 2.2.3.1 Power-on Reset (POR)
        2. 2.2.3.2 Brownout Reset (BOR)
        3. 2.2.3.3 POR and BOR Behavior During Supply Changes
      4. 2.2.4 Bandgap Reference
      5. 2.2.5 VBOOST for Analog Muxes
      6. 2.2.6 Peripheral Enable
        1. 2.2.6.1 Automatic Peripheral Disable in Low Power Modes
    3. 2.3 Clock Module (CKM)
      1. 2.3.1 Oscillators
        1. 2.3.1.1 Internal Low-Frequency Oscillator (LFOSC)
        2. 2.3.1.2 Internal System Oscillator (SYSOSC)
          1. 2.3.1.2.1 SYSOSC Gear Shift
          2. 2.3.1.2.2 SYSOSC Frequency
          3. 2.3.1.2.3 SYSOSC Frequency Correction Loop
            1. 2.3.1.2.3.1 SYSOSC FCL in External Resistor Mode (ROSC)
            2. 2.3.1.2.3.2 SYSOSC FCL in Internal Resistor Mode
          4. 2.3.1.2.4 SYSOSC User Trim Procedure
          5. 2.3.1.2.5 Disabling SYSOSC
        3. 2.3.1.3 Low Frequency Crystal Oscillator (LFXT)
        4. 2.3.1.4 LFCLK_IN (Digital Clock)
        5. 2.3.1.5 High Frequency Crystal Oscillator (HFXT)
        6. 2.3.1.6 HFCLK_IN (Digital clock)
      2. 2.3.2 Clocks
        1. 2.3.2.1  MCLK (Main Clock) Tree
        2. 2.3.2.2  CPUCLK (Processor Clock)
        3. 2.3.2.3  ULPCLK (Low-Power Clock)
        4. 2.3.2.4  MFCLK (Middle Frequency Clock)
        5. 2.3.2.5  MFPCLK (Middle Frequency Precision Clock)
        6. 2.3.2.6  LFCLK (Low-Frequency Clock)
        7. 2.3.2.7  HFCLK (High-Frequency External Clock)
        8. 2.3.2.8  HSCLK (High Speed Clock)
        9. 2.3.2.9  ADCCLK (ADC Sample Period Clock)
        10. 2.3.2.10 CANCLK (CAN-FD Functional Clock)
        11. 2.3.2.11 RTCCLK (RTC Clock)
        12. 2.3.2.12 External Clock Output (CLK_OUT)
        13. 2.3.2.13 Direct Clock Connections for Infrastructure
      3. 2.3.3 Clock Tree
        1. 2.3.3.1 Peripheral Clock Source Selection
      4. 2.3.4 Clock Monitors
        1. 2.3.4.1 LFCLK Monitor
        2. 2.3.4.2 MCLK Monitor
        3. 2.3.4.3 Startup Monitors
          1. 2.3.4.3.1 LFOSC Startup Monitor
          2. 2.3.4.3.2 LFXT Startup Monitor
          3. 2.3.4.3.3 HFCLK Startup Monitor
          4. 2.3.4.3.4 HSCLK Status
      5. 2.3.5 Frequency Clock Counter (FCC)
        1. 2.3.5.1 Using the FCC
        2. 2.3.5.2 FCC Frequency Computation and Accuracy
    4. 2.4 System Controller (SYSCTL)
      1. 2.4.1  Resets and Device Initialization
        1. 2.4.1.1 Reset Levels
          1. 2.4.1.1.1 Power-on Reset (POR) Reset Level
          2. 2.4.1.1.2 Brownout Reset (BOR) Reset Level
          3. 2.4.1.1.3 Boot Reset (BOOTRST) Reset Level
          4. 2.4.1.1.4 System Reset (SYSRST) Reset Level
          5. 2.4.1.1.5 CPU-only Reset (CPURST) Reset Level
        2. 2.4.1.2 Initial Conditions After Power-Up
        3. 2.4.1.3 NRST Pin
        4. 2.4.1.4 SWD Pins
        5. 2.4.1.5 Generating Resets in Software
        6. 2.4.1.6 Reset Cause
        7. 2.4.1.7 Peripheral Reset Control
        8. 2.4.1.8 Boot Fail Handling
      2. 2.4.2  Operating Mode Selection
      3. 2.4.3  Asynchronous Fast Clock Requests
      4. 2.4.4  SRAM Write Protection
      5. 2.4.5  Flash Wait States
      6. 2.4.6  Flash Bank Address Swap
      7. 2.4.7  Shutdown Mode Handling (if present)
      8. 2.4.8  Configuration Lockout
      9. 2.4.9  System Status
      10. 2.4.10 Error Handling
      11. 2.4.11 SYSCTL Events
        1. 2.4.11.1 CPU Interrupt Event (CPU_INT)
        2. 2.4.11.2 Nonmaskable Interrupt Event (NMI)
    5. 2.5 SYSCTL Layout Types
    6. 2.6 SYSCTL_TYPEA Registers
    7. 2.7 SYSCTL_TYPEB Registers
    8. 2.8 SYSCTL_TYPEC Registers
    9. 2.9 Quick Start Reference
      1. 2.9.1 Default Device Configuration
      2. 2.9.2 Leveraging MFCLK
      3. 2.9.3 Optimizing Power Consumption in STOP Mode
      4. 2.9.4 Optimizing Power Consumption in STANDBY Mode
      5. 2.9.5 Increasing MCLK Precision
      6. 2.9.6 High Speed Clock (SYSPLL, HFCLK) Handling in Low-Power Modes
      7. 2.9.7 Optimizing for Lowest Wakeup Latency
      8. 2.9.8 Optimizing for Lowest Peak Current in RUN/SLEEP Mode
  5. 3 CPU
    1. 3.1 Overview
    2. 3.2 Arm Cortex-M0+ CPU
      1. 3.2.1 CPU Register File
      2. 3.2.2 Stack Behavior
      3. 3.2.3 Execution Modes and Privilege Levels
      4. 3.2.4 Address Space and Supported Data Sizes
    3. 3.3 Interrupts and Exceptions
      1. 3.3.1 Peripheral Interrupts (IRQs)
        1. 3.3.1.1 Nested Vectored Interrupt Controller (NVIC)
        2. 3.3.1.2 Interrupt Groups
        3. 3.3.1.3 Wake Up Controller (WUC)
      2. 3.3.2 Interrupt and Exception Table
      3. 3.3.3 Processor Lockup Scenario
    4. 3.4 CPU Peripherals
      1. 3.4.1 System Control Block (SCB)
      2. 3.4.2 System Tick Timer (SysTick)
    5. 3.5 Read-Only Memory (ROM)
    6. 3.6 CPUSS Registers
    7. 3.7 WUC Registers
  6. 4 SECURITY
    1. 4.1 Overview
      1. 4.1.1 Secure Boot
      2. 4.1.2 Customer Secure Code (CSC)
    2. 4.2 Boot and Startup Sequence
      1. 4.2.1 CSC Programming Overview
    3. 4.3 Secure Key Storage
    4. 4.4 Flash Memory Protection
      1. 4.4.1 Bank Swapping
      2. 4.4.2 Write Protection
      3. 4.4.3 Read-Execute Protection
      4. 4.4.4 IP Protection
      5. 4.4.5 Data Bank Protection
      6. 4.4.6 Hardware Monotonic Counter
    5. 4.5 SRAM Protection
    6. 4.6 SECURITY Registers
  7. 5 Direct Memory Access (DMA)
    1. 5.1 DMA Overview
    2. 5.2 DMA Operation
      1. 5.2.1  Addressing Modes
      2. 5.2.2  Channel Types
      3. 5.2.3  Transfer Modes
        1. 5.2.3.1 Single Transfer
        2. 5.2.3.2 Block Transfer
        3. 5.2.3.3 Repeated Single Transfer
        4. 5.2.3.4 Repeated Block Transfer
        5. 5.2.3.5 Stride Mode
      4. 5.2.4  Extended Modes
        1. 5.2.4.1 Fill Mode
        2. 5.2.4.2 Table Mode
      5. 5.2.5  Initiating DMA Transfers
      6. 5.2.6  Stopping DMA Transfers
      7. 5.2.7  Channel Priorities
      8. 5.2.8  Burst Block Mode
      9. 5.2.9  Using DMA with System Interrupts
      10. 5.2.10 DMA Controller Interrupts
      11. 5.2.11 DMA Trigger Event Status
      12. 5.2.12 DMA Operating Mode Support
        1. 5.2.12.1 Transfer in RUN Mode
        2. 5.2.12.2 Transfer in SLEEP Mode
        3. 5.2.12.3 Transfer in STOP Mode
        4. 5.2.12.4 Transfers in STANDBY Mode
      13. 5.2.13 DMA Address and Data Errors
      14. 5.2.14 Interrupt and Event Support
    3. 5.3 DMA Registers
  8. 6 NVM (Flash)
    1. 6.1 NVM Overview
      1. 6.1.1 Key Features
      2. 6.1.2 System Components
      3. 6.1.3 Terminology
    2. 6.2 Flash Memory Bank Organization
      1. 6.2.1 Banks
      2. 6.2.2 Flash Memory Regions
      3. 6.2.3 Addressing
        1. 6.2.3.1 Flash Memory Map
      4. 6.2.4 Memory Organization Examples
    3. 6.3 Flash Controller
      1. 6.3.1 Overview of Flash Controller Commands
      2. 6.3.2 NOOP Command
      3. 6.3.3 PROGRAM Command
        1. 6.3.3.1 Program Bit Masking Behavior
        2. 6.3.3.2 Programming Less Than One Flash Word
        3. 6.3.3.3 Target Data Alignment (Devices with Single Flash Word Programming Only)
        4. 6.3.3.4 Target Data Alignment (Devices With Multiword Programming)
        5. 6.3.3.5 Executing a PROGRAM Operation
      4. 6.3.4 ERASE Command
        1. 6.3.4.1 Erase Sector Masking Behavior
        2. 6.3.4.2 Executing an ERASE Operation
      5. 6.3.5 READVERIFY Command
        1. 6.3.5.1 Executing a READVERIFY Operation
      6. 6.3.6 BLANKVERIFY Command
        1. 6.3.6.1 Executing a BLANKVERIFY Operation
      7. 6.3.7 Command Diagnostics
        1. 6.3.7.1 Command Status
        2. 6.3.7.2 Address Translation
        3. 6.3.7.3 Pulse Counts
      8. 6.3.8 Overriding the System Address With a Bank ID, Region ID, and Bank Address
      9. 6.3.9 FLASHCTL Events
        1. 6.3.9.1 CPU Interrupt Event Publisher
    4. 6.4 Write Protection
      1. 6.4.1 Write Protection Resolution
      2. 6.4.2 Static Write Protection
      3. 6.4.3 Dynamic Write Protection
        1. 6.4.3.1 Configuring Protection for the MAIN Region
        2. 6.4.3.2 Configuring Protection for the NONMAIN Region
    5. 6.5 Read Interface
      1. 6.5.1 Bank Address Swapping
    6. 6.6 FLASHCTL Registers
  9. 7 Events
    1. 7.1 Events Overview
      1. 7.1.1 Event Publisher
      2. 7.1.2 Event Subscriber
      3. 7.1.3 Event Fabric Routing
        1. 7.1.3.1 CPU Interrupt Event Route (CPU_INT)
        2. 7.1.3.2 DMA Trigger Event Route (DMA_TRIGx)
        3. 7.1.3.3 Generic Event Route (GEN_EVENTx)
      4. 7.1.4 Event Routing Map
      5. 7.1.5 Event Propagation Latency
    2. 7.2 Events Operation
      1. 7.2.1 CPU Interrupt
      2. 7.2.2 DMA Trigger
      3. 7.2.3 Peripheral to Peripheral Event
      4. 7.2.4 Extended Module Description Register
      5. 7.2.5 Using Event Registers
        1. 7.2.5.1 Event Registers
        2. 7.2.5.2 Configuring Events
        3. 7.2.5.3 Responding to CPU Interrupts in Application Software
        4. 7.2.5.4 Hardware Event Handling
  10. 8 IOMUX
    1. 8.1 IOMUX Overview
      1. 8.1.1 IO Types and Analog Sharing
    2. 8.2 IOMUX Operation
      1. 8.2.1 Peripheral Function (PF) Assignment
      2. 8.2.2 Logic High to Hi-Z Conversion
      3. 8.2.3 Logic Inversion
      4. 8.2.4 SHUTDOWN Mode Wakeup Logic
      5. 8.2.5 Pullup/Pulldown Resistors
      6. 8.2.6 Drive Strength Control
      7. 8.2.7 Hysteresis and Logic Level Control
    3. 8.3 IOMUX Registers
  11. 9 General-Purpose Input/Output (GPIO)
    1. 9.1 GPIO Overview
    2. 9.2 GPIO Operation
      1. 9.2.1 GPIO Ports
      2. 9.2.2 GPIO Read/Write Interface
      3. 9.2.3 GPIO Input Glitch Filtering and Synchronization
      4. 9.2.4 GPIO Fast Wake
      5. 9.2.5 GPIO DMA Interface
      6. 9.2.6 Event Publishers and Subscribers
    3. 9.3 GPIO Registers
  12. 10AES
    1. 10.1 AES Overview
      1. 10.1.1 AESADV Performance
    2. 10.2 AESADV Operation
      1. 10.2.1 Loading the Key
      2. 10.2.2 Writing Input Data
      3. 10.2.3 Reading Output Data
      4. 10.2.4 Operation Descriptions
        1. 10.2.4.1 Single Block Operation
        2. 10.2.4.2 Electronic Codebook (ECB) Mode
          1. 10.2.4.2.1 ECB Encryption
          2. 10.2.4.2.2 ECB Decryption
        3. 10.2.4.3 Cipher Block Chaining (CBC) Mode
          1. 10.2.4.3.1 CBC Encryption
          2. 10.2.4.3.2 CBC Decryption
        4. 10.2.4.4 Output Feedback (OFB) Mode
          1. 10.2.4.4.1 OFB Encryption
          2. 10.2.4.4.2 OFB Decryption
        5. 10.2.4.5 Cipher Feedback (CFB) Mode
          1. 10.2.4.5.1 CFB Encryption
          2. 10.2.4.5.2 CFB Decryption
        6. 10.2.4.6 Counter (CTR) Mode
          1. 10.2.4.6.1 CTR Encryption
          2. 10.2.4.6.2 CTR Decryption
        7. 10.2.4.7 Galois Counter (GCM) Mode
          1. 10.2.4.7.1 GHASH Operation
          2. 10.2.4.7.2 GCM Operating Modes
            1. 10.2.4.7.2.1 Autonomous GCM Operation
              1. 10.2.4.7.2.1.1 GMAC
            2. 10.2.4.7.2.2 GCM With Pre-Calculations
            3. 10.2.4.7.2.3 GCM Operation With Precalculated H- and Y0-Encrypted Forced to Zero
        8. 10.2.4.8 Counter With Cipher Block Chaining Message Authentication Code (CCM)
          1. 10.2.4.8.1 CCM Operation
      5. 10.2.5 AES Events
        1. 10.2.5.1 CPU Interrupt Event Publisher (CPU_EVENT)
        2. 10.2.5.2 DMA Trigger Event Publisher (DMA_TRIG_DATAIN)
        3. 10.2.5.3 DMA Trigger Event Publisher (DMA_TRIG_DATAOUT)
    3. 10.3 AESADV Registers
  13. 11CRC
    1. 11.1 CRC Overview
      1. 11.1.1 CRC16-CCITT
      2. 11.1.2 CRC32-ISO3309
    2. 11.2 CRC Operation
      1. 11.2.1 CRC Generator Implementation
      2. 11.2.2 Configuration
        1. 11.2.2.1 Polynomial Selection
        2. 11.2.2.2 Bit Order
        3. 11.2.2.3 Byte Swap
        4. 11.2.2.4 Byte Order
        5. 11.2.2.5 CRC C Library Compatibility
    3. 11.3 CRCP0 Registers
  14. 12Keystore
    1. 12.1 Overview
    2. 12.2 Detailed Description
    3. 12.3 KEYSTORECTL Registers
  15. 13TRNG
    1. 13.1 TRNG Overview
    2. 13.2 TRNG Operation
      1. 13.2.1 TRNG Generation Data Path
      2. 13.2.2 Clock Configuration and Output Rate
      3. 13.2.3 Behavior in Low Power Modes
      4. 13.2.4 Health Tests
        1. 13.2.4.1 Digital Block Startup Self-Test
        2. 13.2.4.2 Analog Block Startup Self-Test
        3. 13.2.4.3 Runtime Health Test
          1. 13.2.4.3.1 Repetition Count Test
          2. 13.2.4.3.2 Adaptive Proportion Test
          3. 13.2.4.3.3 Handling Runtime Health Test Failures
      5. 13.2.5 Configuration
        1. 13.2.5.1 TRNG State Machine
          1. 13.2.5.1.1 Changing TRNG States
        2. 13.2.5.2 Using the TRNG
        3. 13.2.5.3 TRNG Events
          1. 13.2.5.3.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 13.3 TRNG Registers
  16. 14Temperature Sensor
  17. 15ADC
    1. 15.1 ADC Overview
    2. 15.2 ADC Operation
      1. 15.2.1  ADC Core
      2. 15.2.2  Voltage Reference Options
      3. 15.2.3  Generic Resolution Modes
      4. 15.2.4  Hardware Averaging
      5. 15.2.5  ADC Clocking
      6. 15.2.6  Common ADC Use Cases
      7. 15.2.7  Power Down Behavior
      8. 15.2.8  Sampling Trigger Sources and Sampling Modes
        1. 15.2.8.1 AUTO Sampling Mode
        2. 15.2.8.2 MANUAL Sampling Mode
      9. 15.2.9  Sampling Period
      10. 15.2.10 Conversion Modes
      11. 15.2.11 Data Format
      12. 15.2.12 Advanced Features
        1. 15.2.12.1 Window Comparator
        2. 15.2.12.2 DMA and FIFO Operation
        3. 15.2.12.3 Analog Peripheral Interconnection
      13. 15.2.13 Status Register
      14. 15.2.14 ADC Events
        1. 15.2.14.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 15.2.14.2 Generic Event Publisher (GEN_EVENT)
        3. 15.2.14.3 DMA Trigger Event Publisher (DMA_TRIG)
        4. 15.2.14.4 Generic Event Subscriber (FSUB_0)
    3. 15.3 ADC12 Registers
  18. 16COMP
    1. 16.1 Comparator Overview
    2. 16.2 Comparator Operation
      1. 16.2.1  Comparator Configuration
      2. 16.2.2  Comparator Channels Selection
      3. 16.2.3  Comparator Output
      4. 16.2.4  Output Filter
      5. 16.2.5  Sampled Output Mode
      6. 16.2.6  Blanking Mode
      7. 16.2.7  Reference Voltage Generator
      8. 16.2.8  Comparator Hysteresis
      9. 16.2.9  Input SHORT Switch
      10. 16.2.10 Interrupt and Events Support
        1. 16.2.10.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 16.2.10.2 Generic Event Publisher (GEN_EVENT)
        3. 16.2.10.3 Generic Event Subscribers
    3. 16.3 COMP0 Registers
  19. 17OPA
    1. 17.1 OPA Overview
    2. 17.2 OPA Operation
      1. 17.2.1 Analog Core
      2. 17.2.2 Power Up Behavior
      3. 17.2.3 Inputs
      4. 17.2.4 Output
      5. 17.2.5 Clock Requirements
      6. 17.2.6 Chopping
      7. 17.2.7 OPA Amplifier Modes
        1. 17.2.7.1 General-Purpose Mode
        2. 17.2.7.2 Buffer Mode
        3. 17.2.7.3 OPA PGA Mode
          1. 17.2.7.3.1 Inverting PGA Mode
          2. 17.2.7.3.2 Non-inverting PGA Mode
        4. 17.2.7.4 Difference Amplifier Mode
        5. 17.2.7.5 Cascade Amplifier Mode
      8. 17.2.8 OPA Configuration Selection
      9. 17.2.9 Burnout Current Source
    3. 17.3 OA Registers
  20. 18GPAMP
    1. 18.1 GPAMP Overview
    2. 18.2 GPAMP Operation
      1. 18.2.1 Analog Core
      2. 18.2.2 Power Up Behavior
      3. 18.2.3 Inputs
      4. 18.2.4 Output
      5. 18.2.5 GPAMP Amplifier Modes
        1. 18.2.5.1 General-Purpose Mode
        2. 18.2.5.2 ADC Buffer Mode
        3. 18.2.5.3 Unity Gain Mode
      6. 18.2.6 Chopping
    3. 18.3 GPAMP Registers
  21. 19VREF
    1. 19.1 VREF Overview
    2. 19.2 VREF Operation
      1. 19.2.1 Internal Reference Generation
      2. 19.2.2 External Reference Input
      3. 19.2.3 Analog Peripheral Interface
    3. 19.3 VREF Registers
  22. 20LCD
    1. 20.1 LCD Introduction
      1. 20.1.1 LCD Operating Principle
      2. 20.1.2 Static Mode
      3. 20.1.3 2-Mux Mode
      4. 20.1.4 3-Mux Mode
      5. 20.1.5 4-Mux Mode
      6. 20.1.6 6-Mux Mode
      7. 20.1.7 8-Mux Mode
      8. 20.1.8 Introduction
      9. 20.1.9 LCD Waveforms
    2. 20.2 LCD Clocking
    3. 20.3 Voltage Generation
      1. 20.3.1  Mode 0 - Voltage Generation from external reference and external resistor divider
      2. 20.3.2  Mode 1 - Voltage Generation from AVDD and external resistor divider
      3. 20.3.3  Mode 2 - Voltage Generation from external reference and internal resistor divider
      4. 20.3.4  Mode 3 - Voltage Generation From AVDD and Internal Resistor Ladder
      5. 20.3.5  Mode 4 - Voltage Generation from charge pump with external supply
      6. 20.3.6  Mode 5 - Voltage Generation From Charge Pump With AVDD
      7. 20.3.7  Mode 6 - Voltage Generation From Charge Pump With External Reference on R13
      8. 20.3.8  Mode 7 - Voltage Generation From Charge Pump With Internal Reference on R13
      9. 20.3.9  Charge pump
      10. 20.3.10 Internal Reference Generation
    4. 20.4 Analog Mux
      1. 20.4.1 Static Mode
      2. 20.4.2 Non-Static 1/3 bias mode
      3. 20.4.3 Non-Static 1/4 bias mode
      4. 20.4.4 Low power mode switch controls
    5. 20.5 LCD Memory and output drive
      1. 20.5.1 LCD Memory organization
        1. 20.5.1.1 Memory Organization in Mux-1 to Mux-4 Modes
        2. 20.5.1.2 Memory Organization in Mux-5 to Mux-8 Modes
        3. 20.5.1.3 Configuring memory
        4. 20.5.1.4 Accessing memory and output drive
        5. 20.5.1.5 Blinking Override
    6. 20.6 IO Muxing
    7. 20.7 Interrupt Generation
    8. 20.8 Power Domains and Power Modes
    9. 20.9 LCD Registers
  23. 21UART
    1. 21.1 UART Overview
      1. 21.1.1 Purpose of the Peripheral
      2. 21.1.2 Features
      3. 21.1.3 Functional Block Diagram
    2. 21.2 UART Operation
      1. 21.2.1 Clock Control
      2. 21.2.2 Signal Descriptions
      3. 21.2.3 General Architecture and Protocol
        1. 21.2.3.1  Transmit Receive Logic
        2. 21.2.3.2  Bit Sampling
        3. 21.2.3.3  Majority Voting Feature
        4. 21.2.3.4  Baud Rate Generation
        5. 21.2.3.5  Data Transmission
        6. 21.2.3.6  Error and Status
        7. 21.2.3.7  Local Interconnect Network (LIN) Support
          1. 21.2.3.7.1 LIN Responder Transmission Delay
        8. 21.2.3.8  Flow Control
        9. 21.2.3.9  Idle-Line Multiprocessor
        10. 21.2.3.10 9-Bit UART Mode
        11. 21.2.3.11 RS-485 Support
        12. 21.2.3.12 DALI Protocol
        13. 21.2.3.13 Manchester Encoding and Decoding
        14. 21.2.3.14 IrDA Encoding and Decoding
        15. 21.2.3.15 ISO7816 Smart Card Support
        16. 21.2.3.16 Address Detection
        17. 21.2.3.17 FIFO Operation
        18. 21.2.3.18 Loopback Operation
        19. 21.2.3.19 Glitch Suppression
      4. 21.2.4 Low Power Operation
      5. 21.2.5 Reset Considerations
      6. 21.2.6 Initialization
      7. 21.2.7 Interrupt and Events Support
        1. 21.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 21.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 21.2.8 Emulation Modes
    3. 21.3 UART Registers
  24. 22I2C
    1. 22.1 I2C Overview
      1. 22.1.1 Purpose of the Peripheral
      2. 22.1.2 Features
      3. 22.1.3 Functional Block Diagram
      4. 22.1.4 Environment and External Connections
    2. 22.2 I2C Operation
      1. 22.2.1 Clock Control
        1. 22.2.1.1 Clock Select and I2C Speed
        2. 22.2.1.2 Clock Startup
      2. 22.2.2 Signal Descriptions
      3. 22.2.3 General Architecture
        1. 22.2.3.1  I2C Bus Functional Overview
        2. 22.2.3.2  START and STOP Conditions
        3. 22.2.3.3  Data Format with 7-Bit Address
        4. 22.2.3.4  Acknowledge
        5. 22.2.3.5  Repeated Start
        6. 22.2.3.6  SCL Clock Low Timeout
        7. 22.2.3.7  Clock Stretching
        8. 22.2.3.8  Dual Address
        9. 22.2.3.9  Arbitration
        10. 22.2.3.10 Multiple Controller Mode
        11. 22.2.3.11 Glitch Suppression
        12. 22.2.3.12 FIFO operation
          1. 22.2.3.12.1 Flushing Stale Tx Data in Target Mode
        13. 22.2.3.13 Loopback mode
        14. 22.2.3.14 Burst Mode
        15. 22.2.3.15 DMA Operation
        16. 22.2.3.16 Low-Power Operation
      4. 22.2.4 Protocol Descriptions
        1. 22.2.4.1 I2C Controller Mode
          1. 22.2.4.1.1 Controller Configuration
          2. 22.2.4.1.2 Controller Mode Operation
          3. 22.2.4.1.3 Read On TX Empty
        2. 22.2.4.2 I2C Target Mode
          1. 22.2.4.2.1 Target Mode Operation
      5. 22.2.5 Reset Considerations
      6. 22.2.6 Initialization
      7. 22.2.7 Interrupt and Events Support
        1. 22.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 22.2.7.2 DMA Trigger Publisher (DMA_TRIG1, DMA_TRIG0)
      8. 22.2.8 Emulation Modes
    3. 22.3 I2C Registers
  25. 23SPI
    1. 23.1 SPI Overview
      1. 23.1.1 Purpose of the Peripheral
      2. 23.1.2 Features
      3. 23.1.3 Functional Block Diagram
      4. 23.1.4 External Connections and Signal Descriptions
    2. 23.2 SPI Operation
      1. 23.2.1 Clock Control
      2. 23.2.2 General Architecture
        1. 23.2.2.1 Chip Select and Command Handling
          1. 23.2.2.1.1 Chip Select Control
          2. 23.2.2.1.2 Command Data Control
        2. 23.2.2.2 Data Format
        3. 23.2.2.3 Delayed data sampling
        4. 23.2.2.4 Clock Generation
        5. 23.2.2.5 FIFO Operation
        6. 23.2.2.6 Loopback mode
        7. 23.2.2.7 DMA Operation
        8. 23.2.2.8 Repeat Transfer mode
        9. 23.2.2.9 Low Power Mode
      3. 23.2.3 Protocol Descriptions
        1. 23.2.3.1 Motorola SPI Frame Format
        2. 23.2.3.2 Texas Instruments Synchronous Serial Frame Format
      4. 23.2.4 Reset Considerations
      5. 23.2.5 Initialization
      6. 23.2.6 Interrupt and Events Support
        1. 23.2.6.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 23.2.6.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      7. 23.2.7 Emulation Modes
    3. 23.3 SPI Registers
  26. 24UNICOMM
    1. 24.1 Overview
      1. 24.1.1 Block Diagram
    2. 24.2 Unicomm Architecture
      1. 24.2.1 Serial Peripheral Group (SPG) Configurations
        1. 24.2.1.1 I2C Pairings
      2. 24.2.2 Enables & Resets
    3. 24.3 High-Level Initialization
    4. 24.4 UNICOMM/SPGSS Registers
      1. 24.4.1 UNICOMM Registers
        1. 24.4.1.1 UNICOMM Registers
      2. 24.4.2 SPG Registers
        1. 24.4.2.1 SPGSS Registers
  27. 25UNICOMM UART
    1. 25.1 UART Overview
      1. 25.1.1 Purpose of the Peripheral
      2. 25.1.2 Features
      3. 25.1.3 Functional Block Diagram
    2. 25.2 UART Operation
      1. 25.2.1 Clock Control
      2. 25.2.2 General Architecture and Protocol
        1. 25.2.2.1 Signal Descriptions
        2. 25.2.2.2 Transmit and Receive Logic
        3. 25.2.2.3 Bit Sampling
        4. 25.2.2.4 Baud Rate Generation
        5. 25.2.2.5 Data Transmission
        6. 25.2.2.6 Error and Status
        7. 25.2.2.7 DMA Operation
        8. 25.2.2.8 Internal Loopback Operation
      3. 25.2.3 Additional Protocol and Feature Support
        1. 25.2.3.1  Local Interconnect Network (LIN) Support
          1. 25.2.3.1.1 LIN Commander Transmit
          2. 25.2.3.1.2 LIN Responder Receive
          3. 25.2.3.1.3 LIN Responder Transmission Delay
        2. 25.2.3.2  Flow Control
        3. 25.2.3.3  RS485 Support
        4. 25.2.3.4  FIFO Operation
        5. 25.2.3.5  Idle-Line Multiprocessor
        6. 25.2.3.6  9-Bit UART Mode
        7. 25.2.3.7  DALI Protocol
        8. 25.2.3.8  Manchester Encoding and Decoding
        9. 25.2.3.9  IrDA Encoding and Decoding
        10. 25.2.3.10 ISO7816 Smart Card Support
        11. 25.2.3.11 Address Detection
        12. 25.2.3.12 Glitch Suppression
      4. 25.2.4 Low Power Operation
      5. 25.2.5 Reset Considerations
      6. 25.2.6 UART Initialization
      7. 25.2.7 Interrupt and Events Support
        1. 25.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 25.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 25.2.8 Emulation Modes
    3. 25.3 UNICOMMUART Registers
  28. 26UNICOMM-I2C
    1. 26.1 UNICOMM-I2C Overview
      1. 26.1.1 Purpose of the Peripheral
      2. 26.1.2 Features
      3. 26.1.3 Functional Block Diagram
      4. 26.1.4 Environment and External Connections
    2. 26.2 UNICOMM Common Infrastructure
    3. 26.3 Peripheral Functional Description
      1. 26.3.1 Clock Control
        1. 26.3.1.1 Clock Select and I2C Speed
        2. 26.3.1.2 Clock Startup
      2. 26.3.2 Signal Descriptions
      3. 26.3.3 General Architecture
        1. 26.3.3.1  I2C Bus Functional Overview
        2. 26.3.3.2  START and STOP Conditions
        3. 26.3.3.3  Dual Address
        4. 26.3.3.4  Address Format
          1. 26.3.3.4.1 Data Format with 7-Bit Address
          2. 26.3.3.4.2 Data Format with 10-Bit Address
        5. 26.3.3.5  Acknowledge
        6. 26.3.3.6  Repeated Start
        7. 26.3.3.7  Clock Stretching
        8. 26.3.3.8  Clock Low Timeout
        9. 26.3.3.9  Burst Mode
        10. 26.3.3.10 Arbitration
        11. 26.3.3.11 Multiple Controller Mode
        12. 26.3.3.12 Glitch Suppression
        13. 26.3.3.13 DMA Operation
        14. 26.3.3.14 FIFO Operation
          1. 26.3.3.14.1 FIFO Status Flags
          2. 26.3.3.14.2 FIFO Levels
          3. 26.3.3.14.3 Clearing FIFO Contents
        15. 26.3.3.15 Suspend Communication
        16. 26.3.3.16 Low Power Operation
        17. 26.3.3.17 SMBUS 3.0 Support
          1. 26.3.3.17.1 Quick Command
          2. 26.3.3.17.2 SMBUS Enhanced Acknowledge Control
          3. 26.3.3.17.3 Clock Low Timeout Detection
          4. 26.3.3.17.4 Clock High Timeout Detection
          5. 26.3.3.17.5 Cumulative Clock Low Extended Timeout
          6. 26.3.3.17.6 Packet Error Checking (PEC)
          7. 26.3.3.17.7 Host Notify Protocol
          8. 26.3.3.17.8 Alert Response Protocol
          9. 26.3.3.17.9 Address Resolution Protocol
      4. 26.3.4 Protocol Descriptions & Initialization
        1. 26.3.4.1 I2C Controller Mode
          1. 26.3.4.1.1 I2C Controller Initialization
          2. 26.3.4.1.2 I2C Controller Status
          3. 26.3.4.1.3 I2C Controller Receive Mode
          4. 26.3.4.1.4 I2C Controller Transmitter Mode
          5. 26.3.4.1.5 Controller Transaction Configurations
        2. 26.3.4.2 I2C Target Mode
          1. 26.3.4.2.1 I2C Target Initialization
          2. 26.3.4.2.2 I2C Target Status
          3. 26.3.4.2.3 I2C Target Receiver Mode
          4. 26.3.4.2.4 I2C Target Transmitter Mode
      5. 26.3.5 Reset Considerations
      6. 26.3.6 Initialization
      7. 26.3.7 Interrupt and Events Support
        1. 26.3.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 26.3.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 26.3.8 Emulation Modes
    4. 26.4 UNICOMM I2C Registers
      1. 26.4.1 UNICOMMI2CC Registers
      2. 26.4.2 UNICOMMI2CT Registers
  29. 27UNICOMM-SPI
    1. 27.1 UNICOMM-SPI Overview
      1. 27.1.1 Purpose of the Peripheral
      2. 27.1.2 Features
      3. 27.1.3 Functional Block Diagram
      4. 27.1.4 External Connections and Signal Descriptions
    2. 27.2 SPI Operation
      1. 27.2.1  Clock Frequency Support
        1. 27.2.1.1 SPI Clock Generation
      2. 27.2.2  General Architecture
        1. 27.2.2.1 Chip Select and Command Handling
          1. 27.2.2.1.1 Chip Select Control
        2. 27.2.2.2 Command Data Control
        3. 27.2.2.3 Data Format
        4. 27.2.2.4 Delayed data sampling
        5. 27.2.2.5 DMA Operation
      3. 27.2.3  FIFO Operation
        1. 27.2.3.1 FIFO Size
        2. 27.2.3.2 FIFO Status bits
          1. 27.2.3.2.1 RIS.RX based on FIFO threshold settings
          2. 27.2.3.2.2 RIS.TX based on FIFO threshold settings
        3. 27.2.3.3 Clearing FIFO contents
        4. 27.2.3.4 Hardware monitors empty, full and overflow conditions
      4. 27.2.4  Suspend communication
        1. 27.2.4.1 SPI IDLE State Requirements
      5. 27.2.5  Internal Loopback Operation
      6. 27.2.6  Repeat Transfer mode
      7. 27.2.7  Receive Timeout
      8. 27.2.8  Line Timeout
      9. 27.2.9  Protocol Descriptions
        1. 27.2.9.1 Motorola SPI Frame Format
        2. 27.2.9.2 Texas Instruments Synchronous Serial Frame Format
      10. 27.2.10 Status Flags
      11. 27.2.11 Module configuration
      12. 27.2.12 Reset Considerations
      13. 27.2.13 Initialization
      14. 27.2.14 Interrupt and Events Support
        1. 27.2.14.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 27.2.14.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      15. 27.2.15 Emulation Modes
        1. 27.2.15.1 Graceful Halt
    3. 27.3 UNICOMMSPI Registers
  30. 28Timers (TIMx)
    1. 28.1 TIMx Overview
      1. 28.1.1 TIMG Overview
        1. 28.1.1.1 TIMG Features
        2. 28.1.1.2 Functional Block Diagram
      2. 28.1.2 TIMA Overview
        1. 28.1.2.1 TIMA Features
        2. 28.1.2.2 Functional Block Diagram
      3. 28.1.3 TIMx Instance Configuration
    2. 28.2 TIMx Operation
      1. 28.2.1  Timer Counter
        1. 28.2.1.1 Clock Source Select and Prescaler
          1. 28.2.1.1.1 Internal Clock and Prescaler
          2. 28.2.1.1.2 External Signal Trigger
        2. 28.2.1.2 Repeat Counter (TIMA only)
      2. 28.2.2  Counting Mode Control
        1. 28.2.2.1 One-shot and Periodic Modes
        2. 28.2.2.2 Down Counting Mode
        3. 28.2.2.3 Up/Down Counting Mode
        4. 28.2.2.4 Up Counting Mode
        5. 28.2.2.5 Phase Load (TIMA only)
      3. 28.2.3  Capture/Compare Module
        1. 28.2.3.1 Capture Mode
          1. 28.2.3.1.1 Input Selection, Counter Conditions, and Inversion
            1. 28.2.3.1.1.1 CCP Input Edge Synchronization
            2. 28.2.3.1.1.2 CCP Input Pulse Conditions
            3. 28.2.3.1.1.3 Counter Control Operation
            4. 28.2.3.1.1.4 CCP Input Filtering
            5. 28.2.3.1.1.5 Input Selection
          2. 28.2.3.1.2 Use Cases
            1. 28.2.3.1.2.1 Edge Time Capture
            2. 28.2.3.1.2.2 Period Capture
            3. 28.2.3.1.2.3 Pulse Width Capture
            4. 28.2.3.1.2.4 Combined Pulse Width and Period Time
          3. 28.2.3.1.3 QEI Mode (TIMG with QEI support only)
            1. 28.2.3.1.3.1 QEI With 2-Signal
            2. 28.2.3.1.3.2 QEI With Index Input
            3. 28.2.3.1.3.3 QEI Error Detection
          4. 28.2.3.1.4 Hall Input Mode (TIMG with QEI support only)
        2. 28.2.3.2 Compare Mode
          1. 28.2.3.2.1 Edge Count
      4. 28.2.4  Shadow Load and Shadow Compare
        1. 28.2.4.1 Shadow Load (TIMG4-7, TIMA only)
        2. 28.2.4.2 Shadow Compare (TIMG4-7, TIMG12-13, TIMA only)
      5. 28.2.5  Output Generator
        1. 28.2.5.1 Configuration
        2. 28.2.5.2 Use Cases
          1. 28.2.5.2.1 Edge-Aligned PWM
          2. 28.2.5.2.2 Center-Aligned PWM
          3. 28.2.5.2.3 Asymmetric PWM (TIMA only)
          4. 28.2.5.2.4 Complementary PWM With Deadband Insertion (TIMA only)
        3. 28.2.5.3 Forced Output
      6. 28.2.6  Fault Handler (TIMA only)
        1. 28.2.6.1 Fault Input Conditioning
        2. 28.2.6.2 Fault Input Sources
        3. 28.2.6.3 Counter Behavior With Fault Conditions
        4. 28.2.6.4 Output Behavior With Fault Conditions
      7. 28.2.7  Synchronization With Cross Trigger
        1. 28.2.7.1 Main Timer Cross Trigger Configuration
        2. 28.2.7.2 Secondary Timer Cross Trigger Configuration
      8. 28.2.8  Low Power Operation
      9. 28.2.9  Interrupt and Event Support
        1. 28.2.9.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 28.2.9.2 Generic Event Publisher and Subscriber (GEN_EVENT0 and GEN_EVENT1)
        3. 28.2.9.3 Generic Subscriber Event Example (COMP to TIMx)
      10. 28.2.10 Debug Handler (TIMA Only)
    3. 28.3 TIMx Registers
  31. 29TIMB
    1. 29.1 TIMB Overview
      1. 29.1.1 Features
      2. 29.1.2 TIMB Block Diagram
    2. 29.2 TIMB Operation
      1. 29.2.1 Counter Block Operation
        1. 29.2.1.1 Clock Source Selection
        2. 29.2.1.2 Counter Reset Generation
        3. 29.2.1.3 Event Based Enable and Disable
        4. 29.2.1.4 Event Generation
        5. 29.2.1.5 Interrupt Generation
        6. 29.2.1.6 Counter Behavior on a Debug Halt
        7. 29.2.1.7 Hardware Locking of Configuration Registers
    3. 29.3 TIMB Example Applications
      1. 29.3.1 Periodic Interrupt Generation
      2. 29.3.2 Counter Chaining
      3. 29.3.3 Event Counting
      4. 29.3.4 Event Duration Measurement
      5. 29.3.5 Event Sequence Checking
      6. 29.3.6 PWM Generation
    4. 29.4 TIMB Registers
  32. 30Low Frequency Subsystem (LFSS)
    1. 30.1  Overview
    2. 30.2  Clock System
    3. 30.3  LFSS Reset Using VBAT
    4. 30.4  Power Domains and Supply Detection
      1. 30.4.1 Startup When VBAT Powers on First
      2. 30.4.2 Startup when VDD powers on first
      3. 30.4.3 Behavior When VDD is Lost
      4. 30.4.4 Behavior when VBAT is lost
      5. 30.4.5 Behavior when the device goes into SHUTDOWN mode
      6. 30.4.6 Supercapacitor Charging Circuit
    5. 30.5  Real Time Counter (RTC_x)
    6. 30.6  Independent Watchdog Timer (IWDT)
    7. 30.7  Tamper Input and Output
      1. 30.7.1 IOMUX Mode
      2. 30.7.2 Tamper Mode
        1. 30.7.2.1 Tamper Event Detection
        2. 30.7.2.2 Timestamp Event Output
        3. 30.7.2.3 Heartbeat Generator
        4. 30.7.2.4 RTC Clock Output
    8. 30.8  Scratchpad Memory
    9. 30.9  Lock Function of RTC, TIO, and IWDT
    10. 30.10 LFSS Registers
  33. 31Low Frequency Subsystem (LFSS_B)
    1. 31.1 Overview
    2. 31.2 Clock System
    3. 31.3 LFSS Reset
    4. 31.4 Real Time Counter (RTC_x)
    5. 31.5 Independent Watchdog Timer (IWDT)
    6. 31.6 Lock Function of RTC and IWDT
    7. 31.7 LFSS Registers
  34. 32RTC
    1. 32.1 Overview
      1. 32.1.1 RTC Instances
    2. 32.2 Basic Operation
    3. 32.3 Configuration
      1. 32.3.1  Clocking
      2. 32.3.2  Reading and Writing to RTC Peripheral Registers
      3. 32.3.3  Binary vs. BCD
      4. 32.3.4  Leap Year Handling
      5. 32.3.5  Calendar Alarm Configuration
      6. 32.3.6  Interval Alarm Configuration
      7. 32.3.7  Periodic Alarm Configuration
      8. 32.3.8  Calibration
        1. 32.3.8.1 Crystal Offset Error
          1. 32.3.8.1.1 Offset Error Correction Mechanism
        2. 32.3.8.2 Crystal Temperature Error
          1. 32.3.8.2.1 Temperature Drift Correction Mechanism
      9. 32.3.9  RTC Prescaler Extension
      10. 32.3.10 RTC Timestamp Capture
      11. 32.3.11 RTC Events
        1. 32.3.11.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 32.3.11.2 Generic Event Publisher (GEN_EVENT)
    4. 32.4 RTC Registers
  35. 33IWDT
    1. 33.1 920
    2. 33.2 IWDT Clock Configuration
    3. 33.3 IWDT Period Selection
    4. 33.4 Debug Behavior of the IWDT
    5. 33.5 IWDT Registers
  36. 34Window Watchdog Timer (WWDT)
    1. 34.1 WWDT Overview
      1. 34.1.1 Watchdog Mode
      2. 34.1.2 Interval Timer Mode
    2. 34.2 WWDT Operation
      1. 34.2.1 Mode Selection
      2. 34.2.2 Clock Configuration
      3. 34.2.3 Low-Power Mode Behavior
      4. 34.2.4 Debug Behavior
      5. 34.2.5 WWDT Events
        1. 34.2.5.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 34.3 WWDT Registers
  37. 35Debug
    1. 35.1 DEBUGSS Overview
      1. 35.1.1 Debug Interconnect
      2. 35.1.2 Physical Interface
      3. 35.1.3 Debug Access Ports
    2. 35.2 DEBUGSS Operation
      1. 35.2.1 Debug Features
        1. 35.2.1.1 Processor Debug
          1. 35.2.1.1.1 Breakpoint Unit (BPU)
          2. 35.2.1.1.2 Data Watchpoint and Trace Unit (DWT)
        2. 35.2.1.2 Peripheral Debug
        3. 35.2.1.3 EnergyTrace Technology
      2. 35.2.2 Behavior in Low Power Modes
      3. 35.2.3 Restricting Debug Access
      4. 35.2.4 Mailbox (DSSM)
        1. 35.2.4.1 DSSM Events
          1. 35.2.4.1.1 CPU Interrupt Event (CPU_INT)
        2. 35.2.4.2 Reference
    3. 35.3 DEBUGSS Registers
  38. 36Revision History

31.16 LFSS Registers

Table 31-89 lists the memory-mapped registers for the LFSS registers. All register offset addresses not listed in Table 31-89 should be considered as reserved locations and the register contents should not be modified.

Table 31-89 LFSS Registers
OffsetAcronymRegister NameGroupSection
400hFSUB_0Subsciber Port 0Go
444hFPUB_0Publisher Port 0Go
1004hCLKSELClock Select for Ultra Low Power peripheralsGo
1020hIIDXInterrupt Index RegisterGo
1028hIMASKInterrupt maskGo
1030hRISRaw interrupt statusGo
1038hMISMasked interrupt statusGo
1040hISETInterrupt setGo
1048hICLRInterrupt clearGo
1050hIIDXInterrupt Index RegisterGo
1058hIMASKInterrupt maskGo
1060hRISRaw interrupt statusGo
1068hMISMasked interrupt statusGo
1070hISETInterrupt setGo
1078hICLRInterrupt clearGo
10E0hEVT_MODEEvent ModeGo
10FChDESCLFSS Descriptor RegisterGo
1100hCLKCTLRTC Clock Control RegisterGo
1104hDBGCTLRTC Module Debug Control RegisterGo
1108hCTLRTC Control RegisterGo
110ChSTARTC Status RegisterGo
1110hCALRTC Clock Offset Calibration RegisterGo
1114hTCMPRTC Temperature Compensation RegisterGo
1118hSECRTC Seconds Register - Calendar Mode With Binary / BCD FormatGo
111ChMINRTC Minutes Register - Calendar Mode With Binary / BCD FormatGo
1120hHOURRTC Hours Register - Calendar Mode With Binary / BCD FormatGo
1124hDAYRTC Day Of Week / Month Register - Calendar Mode With Binary / BCD FormatGo
1128hMONRTC Month Register - Calendar Mode With Binary / BCD FormatGo
112ChYEARRTC Year Register - Calendar Mode With Binary / BCD FormatGo
1130hA1MINRTC Minute Alarm Register - Calendar Mode With Binary / BCD FormatGo
1134hA1HOURRTC Hours Alarm Register - Calendar Mode With Binary / BCD FormatGo
1138hA1DAYRTC Alarm Day Of Week / Month Register - Calendar Mode With Binary / BCD FormatGo
113ChA2MINRTC Minute Alarm Register - Calendar Mode With Binary / BCD FormatGo
1140hA2HOURRTC Hours Alarm Register - Calendar Mode With Binary / BCD FormatGo
1144hA2DAYRTC Alarm Day Of Week / Month Register - Calendar Mode With Binary / BCD FormatGo
1148hPSCTLRTC Prescale Timer 0/1 Control RegisterGo
114ChEXTPSCTLRTC Prescale Timer 2 Control RegisterGo
1150hTSSECTime Stamp Seconds Register - Calendar Mode With Binary / BCD FormatGo
1154hTSMINTime Stamp Minutes Register - Calendar Mode With Binary / BCD FormatGo
1158hTSHOURTime Stamp Hours Register - Calendar Mode With Binary / BCD FormatGo
115ChTSDAYTime Stamp Day Of Week / Month Register - Calendar Mode With Binary / BCD FormatGo
1160hTSMONTime Stamp Month Register - Calendar Mode With Binary / BCD FormatGo
1164hTSYEARTime Stamp Years Register - Calendar Mode With Binary / BCD FormatGo
1168hTSSTATTime Stamp Status RegisterGo
116ChTSCTLTime Stamp Control RegisterGo
1170hTSCLRTime Stamp Clear RegisterGo
11F0hLFSSRSTLow frequency subsystem reset requestGo
11FChRTCLOCKReal time clock lock registerGo
1200h + formulaTIOCTL[y]Tamper I/O Control RegisterGo
1280hTOUT3_0Tamper Output 3 to 0Go
1284hTOUT7_4Tamper Output 7 to 4Go
1288hTOUT11_8Tamper Output 11 to 8Go
128ChTOUT15_12Tamper Output 15 to 12Go
1290hTOE3_0Tamper Output Enable 3 to 0Go
1294hTOE7_4Tamper Output Enable 7 to 4Go
1298hTOE11_8Tamper Output Enable 7 to 4Go
129ChTOE15_12Tamper Output Enable 7 to 4Go
12A0hTIN3_0Tamper Input RegisterGo
12A4hTIN7_4Tamper Input RegisterGo
12A8hTIN11_8Tamper Input RegisterGo
12AChTIN15_12Tamper Input RegisterGo
12C0hHEARTBEATHeartbeat RegisterGo
12FChTIOLOCKTamper I/O lock registerGo
1300hWDTENWatchdog Timer Enable RegisterGo
1304hWDTDBGCTLWatchdog Timer Debug Control RegisterGo
1308hWDTCTLWatchdog Timer Control RegisterGo
130ChWDTCNTRSTWatchdog Timer Counter Reset RegisterGo
1310hWDTSTATWatchdog Timer Status RegisterGo
13FChWDTLOCKWatchdog timer lock registerGo
1400h + formulaSPMEM[y]Scratch Pad Memory Data RegisterGo
1500hSPMWPROT0Scratch Pad Memory Write Protect Register 0Go
1504hSPMWPROT1Scratch Pad Memory Write Protect Register 1Go
1508hSPMWPROT2Scratch Pad Memory Write Protect Register 2Go
150ChSPMWPROT3Scratch Pad Memory Write Protect Register 3Go
1510hSPMWPROT4Scratch Pad Memory Write Protect Register 4Go
1514hSPMWPROT5Scratch Pad Memory Write Protect Register 5Go
1518hSPMWPROT6Scratch Pad Memory Write Protect Register 6Go
151ChSPMWPROT7Scratch Pad Memory Write Protect Register 7Go
1540hSPMTERASE0Scratch Pad Memory Tamper Erase Register 0Go
1544hSPMTERASE1Scratch Pad Memory Tamper Erase Register 1Go
1548hSPMTERASE2Scratch Pad Memory Tamper Erase Register 2Go
154ChSPMTERASE3Scratch Pad Memory Tamper Erase Register 3Go
1550hSPMTERASE4Scratch Pad Memory Tamper Erase Register 4Go
1554hSPMTERASE5Scratch Pad Memory Tamper Erase Register 5Go
1558hSPMTERASE6Scratch Pad Memory Tamper Erase Register 6Go
155ChSPMTERASE7Scratch Pad Memory Tamper Erase Register 7Go

Complex bit access types are encoded to fit into small table cells. Table 31-90 shows the codes that are used for access types in this section.

Table 31-90 LFSS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
R-0R
-0		Read
Returns 0s
RmodifyR
modify		Read
Write Type
WWWrite
WKW
K		Write
Write protected by a key
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

30.10.1 FSUB_0 (Offset = 400h) [Reset = 00000000h]

FSUB_0 is shown in Figure 31-9 and described in Table 31-91.

Return to the Summary Table.

Subscriber port

Figure 31-95 FSUB_0
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDCHANID
R-0hR/W-0h
Table 31-91 FSUB_0 Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h
3-0CHANIDR/W0h0 = disconnected.
1-15 = connected to channelID = CHANID.

0h = A value of 0 specifies that the event is not connected
Fh = Consult your device data sheet as the actual allowed maximum may be less than 15.

30.10.2 FPUB_0 (Offset = 444h) [Reset = 00000000h]

FPUB_0 is shown in Figure 31-10 and described in Table 31-92.

Return to the Summary Table.

Publisher port

Figure 31-96 FPUB_0
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDCHANID
R-0hR/W-0h
Table 31-92 FPUB_0 Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h
3-0CHANIDR/W0h0 = disconnected.
1-15 = connected to channelID = CHANID.

0h = A value of 0 specifies that the event is not connected
Fh = Consult your device data sheet as the actual allowed maximum may be less than 15.

30.10.3 CLKSEL (Offset = 1004h) [Reset = 00000000h]

CLKSEL is shown in Figure 31-11 and described in Table 31-93.

Return to the Summary Table.

Clock source selection for ULP peripherals

Figure 31-97 CLKSEL
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDLFCLK_SELRESERVED
R-0hR-0hR-0h
Table 31-93 CLKSEL Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h
1LFCLK_SELR0hSelects LFCLK as clock source if enabled
0h = LFCLK is disabled
1h = LFCLK is enabled
0RESERVEDR0h

30.10.4 IIDX (Offset = 1020h) [Reset = 00000000h]

IIDX is shown in Figure 31-12 and described in Table 31-94.

Return to the Summary Table.

This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, … IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in [RIS] and [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.

Figure 31-98 IIDX
313029282726252423222120191817161514131211109876543210
RESERVEDSTAT
R-0hR-0h
Table 31-94 IIDX Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-0STATR0hInterrupt index status
00h = No interrupt pending
01h = RTC ready
02h = RTC time event
03h = RTC alarm 1
04h = RTC alarm 2
05h = RTC prescale timer 0
06h = RTC prescale timer 1
07h = RTC prescale timer 2
08h = Time stamp event
09h = Tamper I/O 0 event
0Ah = Tamper I/O 1 event
0Bh = Tamper I/O 2 event
0Ch = Tamper I/O 3 event
0Dh = Tamper I/O 4 event
0Eh = Tamper I/O 5 event
0Fh = Tamper I/O 6 event
10h = Tamper I/O 7 event
11h = Tamper I/O 8 event
12h = Tamper I/O 9 event
13h = Tamper I/O 10 event
14h = Tamper I/O 11 event
15h = Tamper I/O 12 event
16h = Tamper I/O 13 event
17h = Tamper I/O 14 event
18h = Tamper I/O 15 event

30.10.5 IMASK (Offset = 1028h) [Reset = 00000000h]

IMASK is shown in Figure 31-13 and described in Table 31-95.

Return to the Summary Table.

Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Figure 31-99 IMASK
3130292827262524
RESERVED
R-0h
2322212019181716
TIO15TIO14TIO13TIO12TIO11TIO10TIO9TIO8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
TIO7TIO6TIO5TIO4TIO3TIO2TIO1TIO0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
TSEVTRT2PSRT1PSRT0PSRTCA2RTCA1RTCTEVRTCRDY
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 31-95 IMASK Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h
23TIO15R/W0hTamper I/O 15 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
22TIO14R/W0hTamper I/O 14 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
21TIO13R/W0hTamper I/O 13 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
20TIO12R/W0hTamper I/O 12 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
19TIO11R/W0hTamper I/O 11 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
18TIO10R/W0hTamper I/O 10 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
17TIO9R/W0hTamper I/O 9 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
16TIO8R/W0hTamper I/O 8 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
15TIO7R/W0hTamper I/O 7 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
14TIO6R/W0hTamper I/O 6 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
13TIO5R/W0hTamper I/O 5 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
12TIO4R/W0hTamper I/O 4 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
11TIO3R/W0hTamper I/O 3 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
10TIO2R/W0hTamper I/O 2 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
9TIO1R/W0hTamper I/O 1 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
8TIO0R/W0hTamper I/O 0 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
7TSEVTR/W0hTime stamp event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
6RT2PSR/W0hRTC prescale timer 2
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
5RT1PSR/W0hRTC prescale timer 1
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
4RT0PSR/W0hRTC prescale timer 0
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
3RTCA2R/W0hRTC alarm 2
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
2RTCA1R/W0hRTC alarm 1
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
1RTCTEVR/W0hRTC time event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
0RTCRDYR/W0hRTC ready
0h = Clear Interrupt Mask
1h = Set Interrupt Mask

30.10.6 RIS (Offset = 1030h) [Reset = 00000000h]

RIS is shown in Figure 31-14 and described in Table 31-96.

Return to the Summary Table.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 31-100 RIS
3130292827262524
RESERVED
R-0h
2322212019181716
TIO15TIO14TIO13TIO12TIO11TIO10TIO9TIO8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
TIO7TIO6TIO5TIO4TIO3TIO2TIO1TIO0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
TSEVTRT2PSRT1PSRT0PSRTCA2RTCA1RTCTEVRTCRDY
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 31-96 RIS Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h
23TIO15R0hTamper I/O 15 event
0h = Interrupt did not occur
1h = Interrupt occurred
22TIO14R0hTamper I/O 14 event
0h = Interrupt did not occur
1h = Interrupt occurred
21TIO13R0hTamper I/O 13 event
0h = Interrupt did not occur
1h = Interrupt occurred
20TIO12R0hTamper I/O 12 event
0h = Interrupt did not occur
1h = Interrupt occurred
19TIO11R0hTamper I/O 11 event
0h = Interrupt did not occur
1h = Interrupt occurred
18TIO10R0hTamper I/O 10 event
0h = Interrupt did not occur
1h = Interrupt occurred
17TIO9R0hTamper I/O 9 event
0h = Interrupt did not occur
1h = Interrupt occurred
16TIO8R0hTamper I/O 8 event
0h = Interrupt did not occur
1h = Interrupt occurred
15TIO7R0hTamper I/O 7 event
0h = Interrupt did not occur
1h = Interrupt occurred
14TIO6R0hTamper I/O 6 event
0h = Interrupt did not occur
1h = Interrupt occurred
13TIO5R0hTamper I/O 5 event
0h = Interrupt did not occur
1h = Interrupt occurred
12TIO4R0hTamper I/O 4 event
0h = Interrupt did not occur
1h = Interrupt occurred
11TIO3R0hTamper I/O 3 event
0h = Interrupt did not occur
1h = Interrupt occurred
10TIO2R0hTamper I/O 2 event
0h = Interrupt did not occur
1h = Interrupt occurred
9TIO1R0hTamper I/O 1 event
0h = Interrupt did not occur
1h = Interrupt occurred
8TIO0R0hTamper I/O 0 event
0h = Interrupt did not occur
1h = Interrupt occurred
7TSEVTR0hTime stamp event
0h = Interrupt did not occur
1h = Interrupt occurred
6RT2PSR0hRTC prescale timer 2
0h = Interrupt did not occur
1h = Interrupt occurred
5RT1PSR0hRTC prescale timer 1
0h = Interrupt did not occur
1h = Interrupt occurred
4RT0PSR0hRTC prescale timer 0
0h = Interrupt did not occur
1h = Interrupt occurred
3RTCA2R0hRTC alarm 2
0h = Interrupt did not occur
1h = Interrupt occurred
2RTCA1R0hRTC alarm 1
0h = Interrupt did not occur
1h = Interrupt occurred
1RTCTEVR0hRTC time event
0h = Interrupt did not occur
1h = Interrupt occurred
0RTCRDYR0hRTC ready
0h = Interrupt did not occur
1h = Interrupt occurred

30.10.7 MIS (Offset = 1038h) [Reset = 00000000h]

MIS is shown in Figure 31-15 and described in Table 31-97.

Return to the Summary Table.

Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 31-101 MIS
3130292827262524
RESERVED
R-0h
2322212019181716
TIO15TIO14TIO13TIO12TIO11TIO10TIO9TIO8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
TIO7TIO6TIO5TIO4TIO3TIO2TIO1TIO0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
TSEVTRT2PSRT1PSRT0PSRTCA2RTCA1RTCTEVRTCRDY
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 31-97 MIS Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h
23TIO15R0hTamper I/O 15 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
22TIO14R0hTamper I/O 14 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
21TIO13R0hTamper I/O 13 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
20TIO12R0hTamper I/O 12 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
19TIO11R0hTamper I/O 11 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
18TIO10R0hTamper I/O 10 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
17TIO9R0hTamper I/O 9 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
16TIO8R0hTamper I/O 8 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
15TIO7R0hTamper I/O 7 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
14TIO6R0hTamper I/O 6 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
13TIO5R0hTamper I/O 5 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
12TIO4R0hTamper I/O 4 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
11TIO3R0hTamper I/O 3 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
10TIO2R0hTamper I/O 2 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
9TIO1R0hTamper I/O 1 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
8TIO0R0hTamper I/O 0 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
7TSEVTR0hTime stamp event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
6RT2PSR0hRTC prescale timer 2
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
5RT1PSR0hRTC prescale timer 1
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
4RT0PSR0hRTC prescale timer 0
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
3RTCA2R0hRTC alarm 2
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
2RTCA1R0hRTC alarm 1
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
1RTCTEVR0hRTC time event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
0RTCRDYR0hRTC ready
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred

30.10.8 ISET (Offset = 1040h) [Reset = 00000000h]

ISET is shown in Figure 31-16 and described in Table 31-98.

Return to the Summary Table.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 31-102 ISET
3130292827262524
RESERVED
R-0h
2322212019181716
TIO15TIO14TIO13TIO12TIO11TIO10TIO9TIO8
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
15141312111098
TIO7TIO6TIO5TIO4TIO3TIO2TIO1TIO0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
TSEVTRT2PSRT1PSRT0PSRTCA2RTCA1RTCTEVRTCRDY
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 31-98 ISET Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h
23TIO15W0hTamper I/O 15 event
0h = Writing 0 has no effect
1h = Set interrupt
22TIO14W0hTamper I/O 14 event
0h = Writing 0 has no effect
1h = Set interrupt
21TIO13W0hTamper I/O 13 event
0h = Writing 0 has no effect
1h = Set interrupt
20TIO12W0hTamper I/O 12 event
0h = Writing 0 has no effect
1h = Set interrupt
19TIO11W0hTamper I/O 11 event
0h = Writing 0 has no effect
1h = Set interrupt
18TIO10W0hTamper I/O 10 event
0h = Writing 0 has no effect
1h = Set interrupt
17TIO9W0hTamper I/O 9 event
0h = Writing 0 has no effect
1h = Set interrupt
16TIO8W0hTamper I/O 8 event
0h = Writing 0 has no effect
1h = Set interrupt
15TIO7W0hTamper I/O 7 event
0h = Writing 0 has no effect
1h = Set interrupt
14TIO6W0hTamper I/O 6 event
0h = Writing 0 has no effect
1h = Set interrupt
13TIO5W0hTamper I/O 5 event
0h = Writing 0 has no effect
1h = Set interrupt
12TIO4W0hTamper I/O 4 event
0h = Writing 0 has no effect
1h = Set interrupt
11TIO3W0hTamper I/O 3 event
0h = Writing 0 has no effect
1h = Set interrupt
10TIO2W0hTamper I/O 2 event
0h = Writing 0 has no effect
1h = Set interrupt
9TIO1W0hTamper I/O 1 event
0h = Writing 0 has no effect
1h = Set interrupt
8TIO0W0hTamper I/O 0 event
0h = Writing 0 has no effect
1h = Set interrupt
7TSEVTW0hTime stamp event
0h = Writing 0 has no effect
1h = Set interrupt
6RT2PSW0hRTC prescale timer 2
0h = Writing 0 has no effect
1h = Set interrupt
5RT1PSW0hRTC prescale timer 1
0h = Writing 0 has no effect
1h = Set interrupt
4RT0PSW0hRTC prescale timer 0
0h = Writing 0 has no effect
1h = Set interrupt
3RTCA2W0hRTC alarm 2
0h = Writing 0 has no effect
1h = Set interrupt
2RTCA1W0hRTC alarm 1
0h = Writing 0 has no effect
1h = Set interrupt
1RTCTEVW0hRTC time event
0h = Writing 0 has no effect
1h = Set interrupt
0RTCRDYW0hRTC ready
0h = Writing 0 has no effect
1h = Set interrupt

30.10.9 ICLR (Offset = 1048h) [Reset = 00000000h]

ICLR is shown in Figure 31-17 and described in Table 31-99.

Return to the Summary Table.

Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 31-103 ICLR
3130292827262524
RESERVED
R-0h
2322212019181716
TIO15TIO14TIO13TIO12TIO11TIO10TIO9TIO8
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
15141312111098
TIO7TIO6TIO5TIO4TIO3TIO2TIO1TIO0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
TSEVTRT2PSRT1PSRT0PSRTCA2RTCA1RTCTEVRTCRDY
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 31-99 ICLR Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h
23TIO15W0hTamper I/O 15 event
0h = Writing 0 has no effect
1h = Clear interrupt
22TIO14W0hTamper I/O 14 event
0h = Writing 0 has no effect
1h = Clear interrupt
21TIO13W0hTamper I/O 13 event
0h = Writing 0 has no effect
1h = Clear interrupt
20TIO12W0hTamper I/O 12 event
0h = Writing 0 has no effect
1h = Clear interrupt
19TIO11W0hTamper I/O 11 event
0h = Writing 0 has no effect
1h = Clear interrupt
18TIO10W0hTamper I/O 10 event
0h = Writing 0 has no effect
1h = Clear interrupt
17TIO9W0hTamper I/O 9 event
0h = Writing 0 has no effect
1h = Clear interrupt
16TIO8W0hTamper I/O 8 event
0h = Writing 0 has no effect
1h = Clear interrupt
15TIO7W0hTamper I/O 7 event
0h = Writing 0 has no effect
1h = Clear interrupt
14TIO6W0hTamper I/O 6 event
0h = Writing 0 has no effect
1h = Clear interrupt
13TIO5W0hTamper I/O 5 event
0h = Writing 0 has no effect
1h = Clear interrupt
12TIO4W0hTamper I/O 4 event
0h = Writing 0 has no effect
1h = Clear interrupt
11TIO3W0hTamper I/O 3 event
0h = Writing 0 has no effect
1h = Clear interrupt
10TIO2W0hTamper I/O 2 event
0h = Writing 0 has no effect
1h = Clear interrupt
9TIO1W0hTamper I/O 1 event
0h = Writing 0 has no effect
1h = Clear interrupt
8TIO0W0hTamper I/O 0 event
0h = Writing 0 has no effect
1h = Clear interrupt
7TSEVTW0hTime stamp event
0h = Writing 0 has no effect
1h = Clear interrupt
6RT2PSW0hRTC prescale timer 2
0h = Writing 0 has no effect
1h = Clear interrupt
5RT1PSW0hRTC prescale timer 1
0h = Writing 0 has no effect
1h = Clear interrupt
4RT0PSW0hRTC prescale timer 0
0h = Writing 0 has no effect
1h = Clear interrupt
3RTCA2W0hRTC alarm 2
0h = Writing 0 has no effect
1h = Clear interrupt
2RTCA1W0hRTC alarm 1
0h = Writing 0 has no effect
1h = Clear interrupt
1RTCTEVW0hRTC time event
0h = Writing 0 has no effect
1h = Clear interrupt
0RTCRDYW0hRTC ready
0h = Writing 0 has no effect
1h = Clear interrupt

30.10.10 IIDX (Offset = 1050h) [Reset = 00000000h]

IIDX is shown in Figure 31-18 and described in Table 31-100.

Return to the Summary Table.

This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, … IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in [RIS] and [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.

Figure 31-104 IIDX
313029282726252423222120191817161514131211109876543210
RESERVEDSTAT
R-0hR-0h
Table 31-100 IIDX Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-0STATR0hInterrupt index status
00h = No interrupt pending
01h = RTC ready
02h = RTC time event
03h = RTC alarm 1
04h = RTC alarm 2
05h = RTC prescale timer 0
06h = RTC prescale timer 1
07h = RTC prescale timer 2
08h = Time stamp event
09h = Tamper I/O 0 event
0Ah = Tamper I/O 1 event
0Bh = Tamper I/O 2 event
0Ch = Tamper I/O 3 event
0Dh = Tamper I/O 4 event
0Eh = Tamper I/O 5 event
0Fh = Tamper I/O 6 event
10h = Tamper I/O 7 event
11h = Tamper I/O 8 event
12h = Tamper I/O 9 event
13h = Tamper I/O 10 event
14h = Tamper I/O 11 event
15h = Tamper I/O 12 event
16h = Tamper I/O 13 event
17h = Tamper I/O 14 event
18h = Tamper I/O 15 event

30.10.11 IMASK (Offset = 1058h) [Reset = 00000000h]

IMASK is shown in Figure 31-19 and described in Table 31-101.

Return to the Summary Table.

Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Figure 31-105 IMASK
3130292827262524
RESERVED
R-0h
2322212019181716
TIO15TIO14TIO13TIO12TIO11TIO10TIO9TIO8
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
TIO7TIO6TIO5TIO4TIO3TIO2TIO1TIO0
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
TSEVTRT2PSRT1PSRT0PSRTCA2RTCA1RTCTEVRTCRDY
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 31-101 IMASK Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h
23TIO15R/W0hTamper I/O 15 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
22TIO14R/W0hTamper I/O 14 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
21TIO13R/W0hTamper I/O 13 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
20TIO12R/W0hTamper I/O 12 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
19TIO11R/W0hTamper I/O 11 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
18TIO10R/W0hTamper I/O 10 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
17TIO9R/W0hTamper I/O 9 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
16TIO8R/W0hTamper I/O 8 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
15TIO7R/W0hTamper I/O 7 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
14TIO6R/W0hTamper I/O 6 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
13TIO5R/W0hTamper I/O 5 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
12TIO4R/W0hTamper I/O 4 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
11TIO3R/W0hTamper I/O 3 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
10TIO2R/W0hTamper I/O 2 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
9TIO1R/W0hTamper I/O 1 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
8TIO0R/W0hTamper I/O 0 event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
7TSEVTR/W0hTime stamp event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
6RT2PSR/W0hRTC prescale timer 2
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
5RT1PSR/W0hRTC prescale timer 1
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
4RT0PSR/W0hRTC prescale timer 0
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
3RTCA2R/W0hRTC alarm 2
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
2RTCA1R/W0hRTC alarm 1
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
1RTCTEVR/W0hRTC time event
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
0RTCRDYR/W0hRTC ready
0h = Clear Interrupt Mask
1h = Set Interrupt Mask

30.10.12 RIS (Offset = 1060h) [Reset = 00000000h]

RIS is shown in Figure 31-20 and described in Table 31-102.

Return to the Summary Table.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 31-106 RIS
3130292827262524
RESERVED
R-0h
2322212019181716
TIO15TIO14TIO13TIO12TIO11TIO10TIO9TIO8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
TIO7TIO6TIO5TIO4TIO3TIO2TIO1TIO0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
TSEVTRT2PSRT1PSRT0PSRTCA2RTCA1RTCTEVRTCRDY
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 31-102 RIS Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h
23TIO15R0hTamper I/O 15 event
0h = Interrupt did not occur
1h = Interrupt occurred
22TIO14R0hTamper I/O 14 event
0h = Interrupt did not occur
1h = Interrupt occurred
21TIO13R0hTamper I/O 13 event
0h = Interrupt did not occur
1h = Interrupt occurred
20TIO12R0hTamper I/O 12 event
0h = Interrupt did not occur
1h = Interrupt occurred
19TIO11R0hTamper I/O 11 event
0h = Interrupt did not occur
1h = Interrupt occurred
18TIO10R0hTamper I/O 10 event
0h = Interrupt did not occur
1h = Interrupt occurred
17TIO9R0hTamper I/O 9 event
0h = Interrupt did not occur
1h = Interrupt occurred
16TIO8R0hTamper I/O 8 event
0h = Interrupt did not occur
1h = Interrupt occurred
15TIO7R0hTamper I/O 7 event
0h = Interrupt did not occur
1h = Interrupt occurred
14TIO6R0hTamper I/O 6 event
0h = Interrupt did not occur
1h = Interrupt occurred
13TIO5R0hTamper I/O 5 event
0h = Interrupt did not occur
1h = Interrupt occurred
12TIO4R0hTamper I/O 4 event
0h = Interrupt did not occur
1h = Interrupt occurred
11TIO3R0hTamper I/O 3 event
0h = Interrupt did not occur
1h = Interrupt occurred
10TIO2R0hTamper I/O 2 event
0h = Interrupt did not occur
1h = Interrupt occurred
9TIO1R0hTamper I/O 1 event
0h = Interrupt did not occur
1h = Interrupt occurred
8TIO0R0hTamper I/O 0 event
0h = Interrupt did not occur
1h = Interrupt occurred
7TSEVTR0hTime stamp event
0h = Interrupt did not occur
1h = Interrupt occurred
6RT2PSR0hRTC prescale timer 2
0h = Interrupt did not occur
1h = Interrupt occurred
5RT1PSR0hRTC prescale timer 1
0h = Interrupt did not occur
1h = Interrupt occurred
4RT0PSR0hRTC prescale timer 0
0h = Interrupt did not occur
1h = Interrupt occurred
3RTCA2R0hRTC alarm 2
0h = Interrupt did not occur
1h = Interrupt occurred
2RTCA1R0hRTC alarm 1
0h = Interrupt did not occur
1h = Interrupt occurred
1RTCTEVR0hRTC time event
0h = Interrupt did not occur
1h = Interrupt occurred
0RTCRDYR0hRTC ready
0h = Interrupt did not occur
1h = Interrupt occurred

30.10.13 MIS (Offset = 1068h) [Reset = 00000000h]

MIS is shown in Figure 31-21 and described in Table 31-103.

Return to the Summary Table.

Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 31-107 MIS
3130292827262524
RESERVED
R-0h
2322212019181716
TIO15TIO14TIO13TIO12TIO11TIO10TIO9TIO8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
TIO7TIO6TIO5TIO4TIO3TIO2TIO1TIO0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
TSEVTRT2PSRT1PSRT0PSRTCA2RTCA1RTCTEVRTCRDY
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 31-103 MIS Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h
23TIO15R0hTamper I/O 15 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
22TIO14R0hTamper I/O 14 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
21TIO13R0hTamper I/O 13 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
20TIO12R0hTamper I/O 12 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
19TIO11R0hTamper I/O 11 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
18TIO10R0hTamper I/O 10 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
17TIO9R0hTamper I/O 9 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
16TIO8R0hTamper I/O 8 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
15TIO7R0hTamper I/O 7 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
14TIO6R0hTamper I/O 6 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
13TIO5R0hTamper I/O 5 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
12TIO4R0hTamper I/O 4 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
11TIO3R0hTamper I/O 3 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
10TIO2R0hTamper I/O 2 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
9TIO1R0hTamper I/O 1 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
8TIO0R0hTamper I/O 0 event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
7TSEVTR0hTime stamp event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
6RT2PSR0hRTC prescale timer 2
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
5RT1PSR0hRTC prescale timer 1
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
4RT0PSR0hRTC prescale timer 0
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
3RTCA2R0hRTC alarm 2
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
2RTCA1R0hRTC alarm 1
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
1RTCTEVR0hRTC time event
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred
0RTCRDYR0hRTC ready
0h = Interrupt did not occur or is masked out
1h = Interrupt occurred

30.10.14 ISET (Offset = 1070h) [Reset = 00000000h]

ISET is shown in Figure 31-22 and described in Table 31-104.

Return to the Summary Table.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 31-108 ISET
3130292827262524
RESERVED
R-0h
2322212019181716
TIO15TIO14TIO13TIO12TIO11TIO10TIO9TIO8
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
15141312111098
TIO7TIO6TIO5TIO4TIO3TIO2TIO1TIO0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
TSEVTRT2PSRT1PSRT0PSRTCA2RTCA1RTCTEVRTCRDY
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 31-104 ISET Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h
23TIO15W0hTamper I/O 15 event
0h = Writing 0 has no effect
1h = Set interrupt
22TIO14W0hTamper I/O 14 event
0h = Writing 0 has no effect
1h = Set interrupt
21TIO13W0hTamper I/O 13 event
0h = Writing 0 has no effect
1h = Set interrupt
20TIO12W0hTamper I/O 12 event
0h = Writing 0 has no effect
1h = Set interrupt
19TIO11W0hTamper I/O 11 event
0h = Writing 0 has no effect
1h = Set interrupt
18TIO10W0hTamper I/O 10 event
0h = Writing 0 has no effect
1h = Set interrupt
17TIO9W0hTamper I/O 9 event
0h = Writing 0 has no effect
1h = Set interrupt
16TIO8W0hTamper I/O 8 event
0h = Writing 0 has no effect
1h = Set interrupt
15TIO7W0hTamper I/O 7 event
0h = Writing 0 has no effect
1h = Set interrupt
14TIO6W0hTamper I/O 6 event
0h = Writing 0 has no effect
1h = Set interrupt
13TIO5W0hTamper I/O 5 event
0h = Writing 0 has no effect
1h = Set interrupt
12TIO4W0hTamper I/O 4 event
0h = Writing 0 has no effect
1h = Set interrupt
11TIO3W0hTamper I/O 3 event
0h = Writing 0 has no effect
1h = Set interrupt
10TIO2W0hTamper I/O 2 event
0h = Writing 0 has no effect
1h = Set interrupt
9TIO1W0hTamper I/O 1 event
0h = Writing 0 has no effect
1h = Set interrupt
8TIO0W0hTamper I/O 0 event
0h = Writing 0 has no effect
1h = Set interrupt
7TSEVTW0hTime stamp event
0h = Writing 0 has no effect
1h = Set interrupt
6RT2PSW0hRTC prescale timer 2
0h = Writing 0 has no effect
1h = Set interrupt
5RT1PSW0hRTC prescale timer 1
0h = Writing 0 has no effect
1h = Set interrupt
4RT0PSW0hRTC prescale timer 0
0h = Writing 0 has no effect
1h = Set interrupt
3RTCA2W0hRTC alarm 2
0h = Writing 0 has no effect
1h = Set interrupt
2RTCA1W0hRTC alarm 1
0h = Writing 0 has no effect
1h = Set interrupt
1RTCTEVW0hRTC time event
0h = Writing 0 has no effect
1h = Set interrupt
0RTCRDYW0hRTC ready
0h = Writing 0 has no effect
1h = Set interrupt

30.10.15 ICLR (Offset = 1078h) [Reset = 00000000h]

ICLR is shown in Figure 31-23 and described in Table 31-105.

Return to the Summary Table.

Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 31-109 ICLR
3130292827262524
RESERVED
R-0h
2322212019181716
TIO15TIO14TIO13TIO12TIO11TIO10TIO9TIO8
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
15141312111098
TIO7TIO6TIO5TIO4TIO3TIO2TIO1TIO0
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
76543210
TSEVTRT2PSRT1PSRT0PSRTCA2RTCA1RTCTEVRTCRDY
W-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 31-105 ICLR Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h
23TIO15W0hTamper I/O 15 event
0h = Writing 0 has no effect
1h = Clear interrupt
22TIO14W0hTamper I/O 14 event
0h = Writing 0 has no effect
1h = Clear interrupt
21TIO13W0hTamper I/O 13 event
0h = Writing 0 has no effect
1h = Clear interrupt
20TIO12W0hTamper I/O 12 event
0h = Writing 0 has no effect
1h = Clear interrupt
19TIO11W0hTamper I/O 11 event
0h = Writing 0 has no effect
1h = Clear interrupt
18TIO10W0hTamper I/O 10 event
0h = Writing 0 has no effect
1h = Clear interrupt
17TIO9W0hTamper I/O 9 event
0h = Writing 0 has no effect
1h = Clear interrupt
16TIO8W0hTamper I/O 8 event
0h = Writing 0 has no effect
1h = Clear interrupt
15TIO7W0hTamper I/O 7 event
0h = Writing 0 has no effect
1h = Clear interrupt
14TIO6W0hTamper I/O 6 event
0h = Writing 0 has no effect
1h = Clear interrupt
13TIO5W0hTamper I/O 5 event
0h = Writing 0 has no effect
1h = Clear interrupt
12TIO4W0hTamper I/O 4 event
0h = Writing 0 has no effect
1h = Clear interrupt
11TIO3W0hTamper I/O 3 event
0h = Writing 0 has no effect
1h = Clear interrupt
10TIO2W0hTamper I/O 2 event
0h = Writing 0 has no effect
1h = Clear interrupt
9TIO1W0hTamper I/O 1 event
0h = Writing 0 has no effect
1h = Clear interrupt
8TIO0W0hTamper I/O 0 event
0h = Writing 0 has no effect
1h = Clear interrupt
7TSEVTW0hTime stamp event
0h = Writing 0 has no effect
1h = Clear interrupt
6RT2PSW0hRTC prescale timer 2
0h = Writing 0 has no effect
1h = Clear interrupt
5RT1PSW0hRTC prescale timer 1
0h = Writing 0 has no effect
1h = Clear interrupt
4RT0PSW0hRTC prescale timer 0
0h = Writing 0 has no effect
1h = Clear interrupt
3RTCA2W0hRTC alarm 2
0h = Writing 0 has no effect
1h = Clear interrupt
2RTCA1W0hRTC alarm 1
0h = Writing 0 has no effect
1h = Clear interrupt
1RTCTEVW0hRTC time event
0h = Writing 0 has no effect
1h = Clear interrupt
0RTCRDYW0hRTC ready
0h = Writing 0 has no effect
1h = Clear interrupt

30.10.16 EVT_MODE (Offset = 10E0h) [Reset = 00000000h]

EVT_MODE is shown in Figure 31-24 and described in Table 31-106.

Return to the Summary Table.

Event mode register. It is used to select whether each line is disabled, in software mode (software clears the RIS) or in hardware mode (hardware clears the RIS)

Figure 31-110 EVT_MODE
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDEVT1_CFGEVT0_CFG
R-0hR-0hR-0h
Table 31-106 EVT_MODE Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h
3-2EVT1_CFGR0hEvent line mode 1 select
2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.
1-0EVT0_CFGR0hEvent line mode 0 select
1h = The interrupt or event line is in software mode. The software ISR clears the associated RIS flag.

30.10.17 DESC (Offset = 10FCh) [Reset = 00000000h]

DESC is shown in Figure 31-25 and described in Table 31-107.

Return to the Summary Table.

RTC Descriptor Register

Figure 31-111 DESC
31302928272625242322212019181716
MODULEID
R-0h
1514131211109876543210
FEATUREVERINSTNUMMAJREVMINREV
R-0hR-0hR-0hR-0h
Table 31-107 DESC Field Descriptions
BitFieldTypeResetDescription
31-16MODULEIDR0h Module identifier. This ID is unique for each module. 0x2911 = Module ID of the LFSS Module
0h = Smallest value
FFFFh = Highest possible value
15-12FEATUREVERR0h Feature set of this module. Differentiates the complexity of the actually instantiated module if there are differences.
0h = Smallest value
Fh = Highest possible value
11-8INSTNUMR0h Instantiated version. Describes which instance of the module accessed.
0h = This is the default, if there is only one instance - like for SSIM
7-4MAJREVR0h Major revision. This number holds the module revision and is incremented by the module developers. n = Major version (see device-specific data sheet)
0h = Smallest value
Fh = Highest possible value
3-0MINREVR0h Minor revision. This number holds the module revision and is incremented by the module developers. n = Minor module revision (see device-specific data sheet)
0h = Smallest value
Fh = Highest possible value

30.10.18 CLKCTL (Offset = 1100h) [Reset = 00000000h]

CLKCTL is shown in Figure 31-26 and described in Table 31-108.

Return to the Summary Table.

RTC Clock Control Register.
This register can be made read only access by the RTCLOCK register.

Figure 31-112 CLKCTL
3130292827262524
MODCLKENRESERVED
R/W-0hR-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVED
R-0h
Table 31-108 CLKCTL Field Descriptions
BitFieldTypeResetDescription
31MODCLKENR/W0hThis bit enables the supply of the 32kHz clock to the RTC. It will not power-up the 32kHz crystal oscillator this needs to be done in the Clock System Module.
0h = 32kHz clock is not supplied to the RTC.
1h = 32kHz clock is supplied to the RTC.
30-0RESERVEDR0h

30.10.19 DBGCTL (Offset = 1104h) [Reset = 00000000h]

DBGCTL is shown in Figure 31-27 and described in Table 31-109.

Return to the Summary Table.

RTC Module Debug Control Register

Figure 31-113 DBGCTL
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDDBGINTDBGRUN
R-0hR/W-0hR/W-0h
Table 31-109 DBGCTL Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h
1DBGINTR/W0h Debug Interrupt Enable.
0h = Interrupts of the module will not be captured anymore if CPU is in debug state. Which means no update to the RTCRIS, RTCMISC and RTCIIDX register.
1h = Interrupts are enabled in debug mode. Interrupt requests are signaled to the interrupt controller. If the flags are required by software (polling mode) the DGBINT bit need to be set to 1.
0DBGRUNR/W0h Debug Run.
0h = Counter is halted if CPU is in debug state.
1h = Continue to operate normally ignoring the debug state of the CPU.

30.10.20 CTL (Offset = 1108h) [Reset = 00000000h]

CTL is shown in Figure 31-28 and described in Table 31-110.

Return to the Summary Table.

RTC Control Register

Figure 31-114 CTL
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RTCBCDRESERVEDRTCTEVTX
R/W-0hR-0hR/W-0h
Table 31-110 CTL Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7RTCBCDR/W0h Real-time clock BCD select. Selects BCD counting for real-time clock.
0h = Binary code selected
1h = Binary coded decimal (BCD) code selected
6-2RESERVEDR0h
1-0RTCTEVTXR/W0hReal-time clock time event 0x0 = Minute changed 0x1 = Hour changed 0x2 = Every day at midnight (00:00) 0x3 = Every day at noon (12:00)
0h = Generate RTC event every minute.
1h = Generate RTC event every hour.
2h = Generate RTC event at midnight.
3h = Generate RTC event at noon.

30.10.21 STA (Offset = 110Ch) [Reset = 00000000h]

STA is shown in Figure 31-29 and described in Table 31-111.

Return to the Summary Table.

RTC Status Register

Figure 31-115 STA
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRTCTCOKRTCTCRDYRTCRDY
R-0hR-0hR-0hR-0h
Table 31-111 STA Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0h
2RTCTCOKR0h Real-time clock temperature compensation write OK. This is a read-only bit that indicates if the write to RTCTCMP is successful or not.
0h = Write to RTCTCMPx is unsuccessful
1h = Write to RTCTCMPx is successful
1RTCTCRDYR0h Real-time clock temperature compensation ready. This is a read only bit that indicates when the RTCTCMPx can be written. Write to RTCTCMPx should be avoided when RTCTCRDY is reset.
0h = RTC temperature compensation in transition
1h = RTC temperature compensation ready
0RTCRDYR0h Real-time clock ready. This bit indicates when the real-time clock time values are safe for reading.
0h = RTC time values in transition
1h = RTC time values safe for reading.

30.10.22 CAL (Offset = 1110h) [Reset = 00000000h]

CAL is shown in Figure 31-30 and described in Table 31-112.

Return to the Summary Table.

RTC Clock Offset Calibration Register

Figure 31-116 CAL
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRTCCALFX
R-0hR/W-0h
15141312111098
RTCOCALSRESERVED
R/W-0hR-0h
76543210
RTCOCALX
R/W-0h
Table 31-112 CAL Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0h
17-16RTCCALFXR/W0hReal-time clock calibration frequency. Selects frequency output to RTCCLK pin for calibration measurement. The corresponding port must be configured for the peripheral module function.
0h = 32kHz
1h = 512Hz
2h = 256Hz
3h = 1Hz
15RTCOCALSR/W0h Real-time clock offset error calibration sign. This bit decides the sign of offset error calibration.
0h = Down calibration. Frequency adjusted down.
1h = Up calibration. Frequency adjusted up.
14-8RESERVEDR0h
7-0RTCOCALXR/W0h Real-time clock offset error calibration. Each LSB represents approximately +1ppm (RTCOCALXS = 1) or -1ppm (RTCOCALXS = 0) adjustment in frequency. Maximum effective calibration value is +/-240ppm. Excess values written above +/-240ppm will be ignored by hardware.
0h = Smallest value
FFh = Highest possible value

30.10.23 TCMP (Offset = 1114h) [Reset = 00000000h]

TCMP is shown in Figure 31-31 and described in Table 31-113.

Return to the Summary Table.

RTC Temperature Compensation Register

Figure 31-117 TCMP
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RTCTCMPSRESERVED
R/W-0hR-0h
76543210
RTCTCMPX
R/W-0h
Table 31-113 TCMP Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0h
15RTCTCMPSR/W0h Real-time clock temperature compensation sign. This bit decides the sign of temperature compensation.
0h = Down calibration. Frequency adjusted down.
1h = Up calibration. Frequency adjusted up.
14-8RESERVEDR0h
7-0RTCTCMPXR/W0h Real-time clock temperature compensation. Value written into this register is used for temperature compensation of RTC. Each LSB represents approximately +1ppm (RTCTCMPS = 1) or -1ppm (RTCTCMPS = 0) adjustment in frequency. Maximum effective calibration value is +/-240ppm. Excess values written above +/-240ppm are ignored by hardware. Reading from RTCTCMP register at any time returns the cumulative value which is the signed addition of RTCOCALx and RTCTCMPX values, and the updated sign bit (RTCTCMPS) of the addition result.
00h = Smallest value
FFh = Highest possible value

30.10.24 SEC (Offset = 1118h) [Reset = 0000XXXXh]

SEC is shown in Figure 31-32 and described in Table 31-114.

Return to the Summary Table.

RTC Seconds Register - Calendar Mode With Binary / BCD Format.
This register can be made read only access by the RTCLOCK register.

Figure 31-118 SEC
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDSECHIGHBCDSECLOWBCD
R-0hR/W-XR/W-X
76543210
RESERVEDSECBIN
R-0hR/W-X
Table 31-114 SEC Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0h
14-12SECHIGHBCDR/WX Seconds BCD – high digit (0 to 5). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
5h = Highest possible value
11-8SECLOWBCDR/WX Seconds BCD – low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
9h = Highest possible value
7-6RESERVEDR0h
5-0SECBINR/WX Seconds Binary (0 to 59). If RTCBCD=1 write to these bits will be ignored and read give the value 0.
00h = Smallest value
3Bh = Highest possible value

30.10.25 MIN (Offset = 111Ch) [Reset = 0000XXXXh]

MIN is shown in Figure 31-33 and described in Table 31-115.

Return to the Summary Table.

RTC Minutes Register - Calendar Mode With Binary / BCD Format.
This register can be made read only access by the RTCLOCK register.

Figure 31-119 MIN
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDMINHIGHBCDMINLOWBCD
R-0hR/W-XR/W-X
76543210
RESERVEDMINBIN
R-0hR/W-X
Table 31-115 MIN Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0h
14-12MINHIGHBCDR/WX Minutes BCD – high digit (0 to 5). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
5h = Highest possible value
11-8MINLOWBCDR/WX Minutes BCD – low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
9h = Highest possible value
7-6RESERVEDR0h
5-0MINBINR/WX Minutes Binary (0 to 59). If RTCBCD=1 write to these bits will be ignored and read give the value 0.
00h = Smallest value
3Bh = Highest possible value

30.10.26 HOUR (Offset = 1120h) [Reset = 0000XXXXh]

HOUR is shown in Figure 31-34 and described in Table 31-116.

Return to the Summary Table.

RTC Hours Register - Calendar Mode With Binary / BCD Format.
This register can be made read only access by the RTCLOCK register.

Figure 31-120 HOUR
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDHOURHIGHBCDHOURLOWBCD
R-0hR/W-XR/W-X
76543210
RESERVEDHOURBIN
R-0hR/W-X
Table 31-116 HOUR Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDR0h
13-12HOURHIGHBCDR/WX Hours BCD – high digit (0 to 2). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
2h = Highest possible value
11-8HOURLOWBCDR/WX Hours BCD – low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
9h = Highest possible value
7-5RESERVEDR0h
4-0HOURBINR/WX Hours Binary (0 to 23). If RTCBCD=1 write to these bits will be ignored and read give the value 0.
00h = Smallest value
17h = Highest possible value

30.10.27 DAY (Offset = 1124h) [Reset = 00XXXX0Xh]

DAY is shown in Figure 31-35 and described in Table 31-117.

Return to the Summary Table.

RTC Day of Week/Month Register - Calendar Mode With Binary / BCD Format.
This register can be made read only access by the RTCLOCK register.

Figure 31-121 DAY
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDDOMHIGHBCDDOMLOWBCD
R-0hR/W-XR/W-X
15141312111098
RESERVEDDOMBIN
R-0hR/W-X
76543210
RESERVEDDOW
R-0hR/W-X
Table 31-117 DAY Field Descriptions
BitFieldTypeResetDescription
31-22RESERVEDR0h
21-20DOMHIGHBCDR/WX Day of month BCD – high digit (0 to 3). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
3h = Highest possible value
19-16DOMLOWBCDR/WX Day of month BCD – low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
9h = Highest possible value
15-13RESERVEDR0h
12-8DOMBINR/WX Day of month Binary (1 to 28, 29, 30, 31). If RTCBCD=1 write to these bits will be ignored and read give the value 0.
00h = Smallest value
1Fh = Highest possible value
7-3RESERVEDR0h
2-0DOWR/WX Day of week (0 to 6). These bits are valid if RTCBCD=1 or RTCBCD=0.
0h = Smallest value
6h = Highest possible value

30.10.28 MON (Offset = 1128h) [Reset = 0000XX0Xh]

MON is shown in Figure 31-36 and described in Table 31-118.

Return to the Summary Table.

RTC Month Register - Calendar Mode With Binary / BCD Format.
This register can be made read only access by the RTCLOCK register.

Figure 31-122 MON
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDMONHIGHBCDMONLOWBCD
R-0hR/W-XR/W-X
76543210
RESERVEDMONBIN
R-0hR/W-X
Table 31-118 MON Field Descriptions
BitFieldTypeResetDescription
31-13RESERVEDR0h
12MONHIGHBCDR/WX Month BCD – high digit (0 or 1). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
1h = Highest possible value
11-8MONLOWBCDR/WX Month BCD – low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
9h = Highest possible value
7-4RESERVEDR0h
3-0MONBINR/WX Month Binary (1 to 12). If RTCBCD=1 write to these bits will be ignored and read give the value 0.
0h = Smallest value
Ch = Highest possible value

30.10.29 YEAR (Offset = 112Ch) [Reset = XXXX0XXXh]

YEAR is shown in Figure 31-37 and described in Table 31-119.

Return to the Summary Table.

RTC Year Register - Calendar Mode With Binary / BCD Format.
This register can be made read only access by the RTCLOCK register.

Figure 31-123 YEAR
3130292827262524
RESERVEDCENTHIGHBCDCENTLOWBCD
R-0hR/W-XR/W-X
2322212019181716
DECADEBCDYEARLOWESTBCD
R/W-XR/W-X
15141312111098
RESERVEDYEARHIGHBIN
R-0hR/W-X
76543210
YEARLOWBIN
R/W-X
Table 31-119 YEAR Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0h
30-28CENTHIGHBCDR/WX Century BCD – high digit (0 to 4). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
4h = Highest possible value
27-24CENTLOWBCDR/WX Century BCD – low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
9h = Highest possible value
23-20DECADEBCDR/WX Decade BCD (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
9h = Highest possible value
19-16YEARLOWESTBCDR/WX Year BCD – lowest digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
9h = Highest possible value
15-12RESERVEDR0h
11-8YEARHIGHBINR/WX Year Binary – high byte. Valid values for Year are 0 to 4095. If RTCBCD=1 write to these bits will be ignored and read give the value 0.
0h = Smallest value
Fh = Highest possible value
7-0YEARLOWBINR/WX Year Binary – low byte. Valid values for Year are 0 to 4095. If RTCBCD=1 write to these bits will be ignored and read give the value 0.
00h = Smallest value
FFh = Highest possible value

30.10.30 A1MIN (Offset = 1130h) [Reset = 0000XXXXh]

A1MIN is shown in Figure 31-38 and described in Table 31-120.

Return to the Summary Table.

RTC Minutes Alarm Register - Calendar Mode With Binary / BCD Format

Figure 31-124 A1MIN
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
AMINAEBCDAMINHIGHBCDAMINLOWBCD
R/W-0hR/W-XR/W-X
76543210
AMINAEBINRESERVEDAMINBIN
R/W-0hR-0hR/W-X
Table 31-120 A1MIN Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0h
15AMINAEBCDR/W0hAlarm Minutes BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled.
0h = No alarm
1h = Alarm enabled
14-12AMINHIGHBCDR/WX Alarm Minutes BCD – high digit (0 to 5). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
5h = Highest possible value
11-8AMINLOWBCDR/WX Alarm Minutes BCD – low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
9h = Highest possible value
7AMINAEBINR/W0h Alarm Minutes Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled.
0h = No alarm
1h = Alarm enabled
6RESERVEDR0h
5-0AMINBINR/WX Alarm Minutes Binary (0 to 59). If RTCBCD=1 write to these bits will be ignored and read give the value 0.
00h = Smallest value
3Bh = Highest possible value

30.10.31 A1HOUR (Offset = 1134h) [Reset = 0000XX0Xh]

A1HOUR is shown in Figure 31-39 and described in Table 31-121.

Return to the Summary Table.

RTC Hours Alarm Register - Calendar Mode With Binary / BCD Format

Figure 31-125 A1HOUR
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
AHOURAEBCDRESERVEDAHOURHIGHBCDAHOURLOWBCD
R/W-0hR-0hR/W-XR/W-X
76543210
AHOURAEBINRESERVEDAHOURBIN
R/W-0hR-0hR/W-X
Table 31-121 A1HOUR Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0h
15AHOURAEBCDR/W0h Alarm Hours BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled.
0h = No alarm
1h = Alarm enabled
14RESERVEDR0h
13-12AHOURHIGHBCDR/WX Alarm Hours BCD – high digit (0 to 2). If RTCBCD=0 write to these bits will be ignored and read give the value 0..
0h = Smallest value
2h = Highest possible value
11-8AHOURLOWBCDR/WX Alarm Hours BCD – low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
9h = Highest possible value
7AHOURAEBINR/W0h Alarm Hours Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled.
0h = No alarm
1h = Alarm enabled
6-5RESERVEDR0h
4-0AHOURBINR/WX Alarm Hours Binary (0 to 23). If RTCBCD=1 write to these bits will be ignored and read give the value 0.
0h = Smallest value
17h = Highest possible value

30.10.32 A1DAY (Offset = 1138h) [Reset = 00XXXX0Xh]

A1DAY is shown in Figure 31-40 and described in Table 31-122.

Return to the Summary Table.

RTC Alarm Day Of Week / Month Register - Calendar Mode With Binary / BCD Format

Figure 31-126 A1DAY
3130292827262524
RESERVED
R-0h
2322212019181716
ADOMAEBCDRESERVEDADOMHIGHBCDADOMLOWBCD
R/W-0hR-0hR/W-XR/W-X
15141312111098
ADOMAEBINRESERVEDADOMBIN
R/W-0hR-0hR/W-X
76543210
ADOWAERESERVEDADOW
R/W-0hR-0hR/W-X
Table 31-122 A1DAY Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h
23ADOMAEBCDR/W0h Alarm Day of month BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled.
0h = No alarm
1h = Alarm enabled
22RESERVEDR0h
21-20ADOMHIGHBCDR/WX Alarm Day of month BCD – high digit (0 to 3). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
3h = Highest possible value
19-16ADOMLOWBCDR/WX Alarm Day of month BCD – low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
9h = Highest possible value
15ADOMAEBINR/W0h Alarm Day of month Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled.
0h = No alarm
1h = Alarm enabled
14-13RESERVEDR0h
12-8ADOMBINR/WX Alarm Day of month Binary (1 to 28, 29, 30, 31) If RTCBCD=1 write to these bits will be ignored and read give the value 0.
00h = Smallest value
1Fh = Highest possible value
7ADOWAER/W0h Alarm Day of week enable. This bit are valid if RTCBCD=1 or RTCBCD=0.
0h = No alarm
1h = Alarm enabled
6-3RESERVEDR0h
2-0ADOWR/WX Alarm Day of week (0 to 6). These bits are valid if RTCBCD=1 or RTCBCD=0.
0h = Smallest value
6h = Highest possible value

30.10.33 A2MIN (Offset = 113Ch) [Reset = 0000XXXXh]

A2MIN is shown in Figure 31-41 and described in Table 31-123.

Return to the Summary Table.

RTC Minutes Alarm Register - Calendar Mode With Binary / BCD Format

Figure 31-127 A2MIN
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
AMINAEBCDAMINHIGHBCDAMINLOWBCD
R/W-0hR/W-XR/W-X
76543210
AMINAEBINRESERVEDAMINBIN
R/W-0hR-0hR/W-X
Table 31-123 A2MIN Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0h
15AMINAEBCDR/W0h Alarm Minutes BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled.
0h = No alarm
1h = Alarm enabled
14-12AMINHIGHBCDR/WX Alarm Minutes BCD – high digit (0 to 5). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
5h = Highest possible value
11-8AMINLOWBCDR/WX Alarm Minutes BCD – low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
9h = Highest possible value
7AMINAEBINR/W0h Alarm Minutes Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled.
0h = No alarm
1h = Alarm enabled
6RESERVEDR0h
5-0AMINBINR/WX Alarm Minutes Binary (0 to 59). If RTCBCD=1 write to these bits will be ignored and read give the value 0.
00h = Smallest value
3Bh = Highest possible value

30.10.34 A2HOUR (Offset = 1140h) [Reset = 0000XX0Xh]

A2HOUR is shown in Figure 31-42 and described in Table 31-124.

Return to the Summary Table.

RTC Hours Alarm Register - Calendar Mode With Binary / BCD Format

Figure 31-128 A2HOUR
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
AHOURAEBCDRESERVEDAHOURHIGHBCDAHOURLOWBCD
R/W-0hR-0hR/W-XR/W-X
76543210
AHOURAEBINRESERVEDAHOURBIN
R/W-0hR-0hR/W-X
Table 31-124 A2HOUR Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0h
15AHOURAEBCDR/W0h Alarm Hours BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled.
0h = No alarm
1h = Alarm enabled
14RESERVEDR0h
13-12AHOURHIGHBCDR/WX Alarm Hours BCD – high digit (0 to 2). If RTCBCD=0 write to these bits will be ignored and read give the value 0..
0h = Smallest value
2h = Highest possible value
11-8AHOURLOWBCDR/WX Alarm Hours BCD – low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
9h = Highest possible value
7AHOURAEBINR/W0h Alarm Hours Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled.
0h = No alarm
1h = Alarm enabled
6-5RESERVEDR0h
4-0AHOURBINR/WX Alarm Hours Binary (0 to 23). If RTCBCD=1 write to these bits will be ignored and read give the value 0.
0h = Smallest value
17h = Highest possible value

30.10.35 A2DAY (Offset = 1144h) [Reset = 00XXXX0Xh]

A2DAY is shown in Figure 31-43 and described in Table 31-125.

Return to the Summary Table.

RTC Alarm Day Of Week / Month Register - Calendar Mode With Binary / BCD Format

Figure 31-129 A2DAY
3130292827262524
RESERVED
R-0h
2322212019181716
ADOMAEBCDRESERVEDADOMHIGHBCDADOMLOWBCD
R/W-0hR-0hR/W-XR/W-X
15141312111098
ADOMAEBINRESERVEDADOMBIN
R/W-0hR-0hR/W-X
76543210
ADOWAERESERVEDADOW
R/W-0hR-0hR/W-X
Table 31-125 A2DAY Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h
23ADOMAEBCDR/W0h Alarm Day of month BCD enable. If RTCBCD=0 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled.
0h = No alarm
1h = Alarm enabled
22RESERVEDR0h
21-20ADOMHIGHBCDR/WX Alarm Day of month BCD – high digit (0 to 3). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
3h = Highest possible value
19-16ADOMLOWBCDR/WX Alarm Day of month BCD – low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
9h = Highest possible value
15ADOMAEBINR/W0h Alarm Day of month Binary enable. If RTCBCD=1 this bit is always 0. Write to this bit will be ignored. 0x0= Alarm disabled. 0x1= Alarm enabled.
0h = No alarm
1h = Alarm enabled
14-13RESERVEDR0h
12-8ADOMBINR/WX Alarm Day of month Binary (1 to 28, 29, 30, 31) If RTCBCD=1 write to these bits will be ignored and read give the value 0.
00h = Smallest value
1Fh = Highest possible value
7ADOWAER/W0h Alarm Day of week enable. This bit are valid if RTCBCD=1 or RTCBCD=0.
0h = No alarm
1h = Alarm enabled
6-3RESERVEDR0h
2-0ADOWR/WX Alarm Day of week (0 to 6). These bits are valid if RTCBCD=1 or RTCBCD=0.
0h = Smallest value
6h = Highest possible value

30.10.36 PSCTL (Offset = 1148h) [Reset = 00000008h]

PSCTL is shown in Figure 31-44 and described in Table 31-126.

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RTC Prescale Timer Control Register

Figure 31-130 PSCTL
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRT1IPRESERVED
R-0hR/W-0hR-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRT0IPRESERVED
R-0hR/W-2hR-0h
Table 31-126 PSCTL Field Descriptions
BitFieldTypeResetDescription
31-21RESERVEDR0h
20-18RT1IPR/W0h Prescale timer 1 interrupt interval
0h = Interval every 15.6 millisecond
1h = Interval every 31.3 millisecond
2h = Interval every 62.5 millisecond
3h = Interval every 125 millisecond
4h = Interval every 250 millisecond
5h = Interval every 500 millisecond
6h = Interval every 1 second
7h = Interval every 2 second
17-5RESERVEDR0h
4-2RT0IPR/W2h Prescale timer 0 interrupt interval
2h = Interval every 244 microsecond
3h = Interval every 488 microsecond
4h = Interval every 0.98 millisecond
5h = Interval every 1.95 millisecond
6h = Interval every 3.91 millisecond
7h = Interval every 7.81 millisecond
1-0RESERVEDR0h

30.10.37 EXTPSCTL (Offset = 114Ch) [Reset = 00000000h]

EXTPSCTL is shown in Figure 31-45 and described in Table 31-127.

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Extended Prescale Timer Control Register

Figure 31-131 EXTPSCTL
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDRT2PSRESERVED
R-0hR/W-0hR-0h
Table 31-127 EXTPSCTL Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h
3-2RT2PSR/W0hPrescale timer 2 interrupt interval
0h = Interval every 4 second
1h = Interval every 8 second
2h = Interval every 16 second
1-0RESERVEDR0h

30.10.38 TSSEC (Offset = 1150h) [Reset = 00000000h]

TSSEC is shown in Figure 31-46 and described in Table 31-128.

Return to the Summary Table.

RTC Second Time Stamp Capture - Calendar Mode With Binary / BCD Format

Figure 31-132 TSSEC
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDSECHIGHBCDSECLOWBCD
R-0hR-0hR-0h
76543210
RESERVEDSECBIN
R-0hR-0h
Table 31-128 TSSEC Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0h
14-12SECHIGHBCDR0hTime Stamp Seconds BCD – high digit (0 to 5). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
5h = Highest possible value
11-8SECLOWBCDR0hTime Stamp Seconds BCD – low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
9h = Highest possible value
7-6RESERVEDR0h
5-0SECBINR0hTime Stamp Second Binary (0 to 59). If RTCBCD=1 write to these bits will be ignored and read give the value 0.
00h = Smallest value
3Bh = Highest possible value

30.10.39 TSMIN (Offset = 1154h) [Reset = 00000000h]

TSMIN is shown in Figure 31-47 and described in Table 31-129.

Return to the Summary Table.

RTC Minutes Time Stamp Capture - Calendar Mode With Binary / BCD Format

Figure 31-133 TSMIN
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDMINHIGHBCDMINLOWBCD
R-0hR-0hR-0h
76543210
RESERVEDMINBIN
R-0hR-0h
Table 31-129 TSMIN Field Descriptions
BitFieldTypeResetDescription
31-15RESERVEDR0h
14-12MINHIGHBCDR0hTime Stamp Minutes BCD – high digit (0 to 5). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
5h = Highest possible value
11-8MINLOWBCDR0hTime Stamp Minutes BCD – low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
9h = Highest possible value
7-6RESERVEDR0h
5-0MINBINR0hTime Stamp Minutes Binary (0 to 59). If RTCBCD=1 write to these bits will be ignored and read give the value 0.
0h = Smallest value
3Bh = Highest possible value

30.10.40 TSHOUR (Offset = 1158h) [Reset = 00000000h]

TSHOUR is shown in Figure 31-48 and described in Table 31-130.

Return to the Summary Table.

RTC Hours Time Stamp Capture - Calendar Mode With Binary / BCD Format

Figure 31-134 TSHOUR
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDHOURHIGHBCDHOURLOWBCD
R-0hR-0hR-0h
76543210
RESERVEDHOURBIN
R-0hR-0h
Table 31-130 TSHOUR Field Descriptions
BitFieldTypeResetDescription
31-14RESERVEDR0h
13-12HOURHIGHBCDR0hTime Stamp Hours BCD – high digit (0 to 2). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
00h = Smallest value
02h = Highest possible value
11-8HOURLOWBCDR0hTime Stamp Hours BCD – low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
00h = Smallest value
09h = Highest possible value
7-5RESERVEDR0h
4-0HOURBINR0hTime Stamp Hours Binary (0 to 23). If RTCBCD=1 write to these bits will be ignored and read give the value 0.
00h = Smallest value
17h = Highest possible value

30.10.41 TSDAY (Offset = 115Ch) [Reset = 00000000h]

TSDAY is shown in Figure 31-49 and described in Table 31-131.

Return to the Summary Table.

RTC Day Of Week / Month Time Stamp Capture - Calendar Mode With Binary / BCD Format

Figure 31-135 TSDAY
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDDOMHIGHBCDDOMLOWBCD
R-0hR-0hR-0h
15141312111098
RESERVEDDOMBIN
R-0hR-0h
76543210
RESERVEDDOW
R-0hR-0h
Table 31-131 TSDAY Field Descriptions
BitFieldTypeResetDescription
31-22RESERVEDR0h
21-20DOMHIGHBCDR0hTime Stamp Day of month BCD – high digit (0 to 3). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
3h = Highest possible value
19-16DOMLOWBCDR0hTime Stamp Day of month BCD – low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
9h = Highest possible value
15-13RESERVEDR0h
12-8DOMBINR0hTime Stamp Day of month Binary (1 to 28, 29, 30, 31) If RTCBCD=1 write to these bits will be ignored and read give the value 0.
00h = Smallest value
1Fh = Highest possible value
7-3RESERVEDR0h
2-0DOWR0hTime Stamp Day of week (0 to 6). These bits are valid if RTCBCD=1 or RTCBCD=0.
0h = Smallest value
6h = Highest possible value

30.10.42 TSMON (Offset = 1160h) [Reset = 00000000h]

TSMON is shown in Figure 31-50 and described in Table 31-132.

Return to the Summary Table.

RTC Month Time Stamp Capture - Calendar Mode With Binary / BCD Format

Figure 31-136 TSMON
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDMONHIGHBCDMONLOWBCD
R-0hR-0hR-0h
76543210
RESERVEDMONBIN
R-0hR-0h
Table 31-132 TSMON Field Descriptions
BitFieldTypeResetDescription
31-13RESERVEDR0h
12MONHIGHBCDR0hTime Stamp Month BCD – high digit (0 or 1). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
1h = Highest possible value
11-8MONLOWBCDR0hTime Stamp Month BCD – low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
9h = Highest possible value
7-4RESERVEDR0h
3-0MONBINR0hTime Stamp Month Binary (1 to 12). If RTCBCD=1 write to these bits will be ignored and read give the value 0.
0h = Smallest value
Ch = Highest possible value

30.10.43 TSYEAR (Offset = 1164h) [Reset = 00000000h]

TSYEAR is shown in Figure 31-51 and described in Table 31-133.

Return to the Summary Table.

RTC Years Time Stamp Capture - Calendar Mode With Binary / BCD Format

Figure 31-137 TSYEAR
3130292827262524
RESERVEDCENTHIGHBCDCENTLOWBCD
R-0hR-0hR-0h
2322212019181716
DECADEBCDYERARLOWESTBCD
R-0hR-0h
15141312111098
RESERVEDYEARHIGHBIN
R-0hR-0h
76543210
YEARLOWBIN
R-0h
Table 31-133 TSYEAR Field Descriptions
BitFieldTypeResetDescription
31RESERVEDR0h
30-28CENTHIGHBCDR0hTime Stamp Century BCD – high digit (0 to 4). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
4h = Highest possible value
27-24CENTLOWBCDR0hTime Stamp Century BCD – low digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
9h = Highest possible value
23-20DECADEBCDR0hTime Stamp Decade BCD (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
9h = Highest possible value
19-16YERARLOWESTBCDR0hTime Stamp Year BCD – lowest digit (0 to 9). If RTCBCD=0 write to these bits will be ignored and read give the value 0.
0h = Smallest value
9h = Highest possible value
15-12RESERVEDR0h
11-8YEARHIGHBINR0hTime Stamp Year Binary – high byte. Valid values for Year are 0 to 4095. If RTCBCD=1 write to these bits will be ignored and read give the value 0.
0h = Smallest value
Fh = Highest possible value
7-0YEARLOWBINR0hTime Stamp Year Binary – low byte. Valid values for Year are 0 to 4095. If RTCBCD=1 write to these bits will be ignored and read give the value 0.
00h = Smallest value
FFh = Highest possible value

30.10.44 TSSTAT (Offset = 1168h) [Reset = 00000000h]

TSSTAT is shown in Figure 31-52 and described in Table 31-134.

Return to the Summary Table.

Time Stamp Status

Figure 31-138 TSSTAT
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDTSVDDEVT
R-0hR-0h
15141312111098
TSTIOEVT15TSTIOEVT14TSTIOEVT13TSTIOEVT12TSTIOEVT11TSTIOEVT10TSTIOEVT9TSTIOEVT8
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
76543210
TSTIOEVT7TSTIOEVT6TSTIOEVT5TSTIOEVT4TSTIOEVT3TSTIOEVT2TSTIOEVT1TSTIOEVT0
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 31-134 TSSTAT Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16TSVDDEVTR0hLoss of VDD caused time stamp event
0h = no event detected
1h = event detected
15TSTIOEVT15R0hTamper I/O 15 caused time stamp event
0h = no event detected
1h = event detected
14TSTIOEVT14R0hTamper I/O 14 caused time stamp event
0h = no event detected
1h = event detected
13TSTIOEVT13R0hTamper I/O 13 caused time stamp event
0h = no event detected
1h = event detected
12TSTIOEVT12R0hTamper I/O 12 caused time stamp event
0h = no event detected
1h = event detected
11TSTIOEVT11R0hTamper I/O 11 caused time stamp event
0h = no event detected
1h = event detected
10TSTIOEVT10R0hTamper I/O 10 caused time stamp event
0h = no event detected
1h = event detected
9TSTIOEVT9R0hTamper I/O 9 caused time stamp event
0h = no event detected
1h = event detected
8TSTIOEVT8R0hTamper I/O 8 caused time stamp event
0h = no event detected
1h = event detected
7TSTIOEVT7R0hTamper I/O 7 caused time stamp event
0h = no event detected
1h = event detected
6TSTIOEVT6R0hTamper I/O 6 caused time stamp event
0h = no event detected
1h = event detected
5TSTIOEVT5R0hTamper I/O 5 caused time stamp event
0h = no event detected
1h = event detected
4TSTIOEVT4R0hTamper I/O 4 caused time stamp event
0h = no event detected
1h = event detected
3TSTIOEVT3R0hTamper I/O 3 caused time stamp event
0h = no event detected
1h = event detected
2TSTIOEVT2R0hTamper I/O 2 caused time stamp event
0h = no event detected
1h = event detected
1TSTIOEVT1R0hTamper I/O 1 caused time stamp event
0h = no event detected
1h = event detected
0TSTIOEVT0R0hTamper I/O 0 caused time stamp event
0h = no event detected
1h = event detected

30.10.45 TSCTL (Offset = 116Ch) [Reset = 00000000h]

TSCTL is shown in Figure 31-53 and described in Table 31-135.

Return to the Summary Table.

time stamp control register

Figure 31-139 TSCTL
3130292827262524
KEY
R-0/W-0h
2322212019181716
RESERVEDTSCAPTURERESERVEDTSVDDEN
R-0hR/WK-0hR-0hR/WK-0h
15141312111098
TSTIOEN15TSTIOEN14TSTIOEN13TSTIOEN12TSTIOEN11TSTIOEN10TSTIOEN9TSTIOEN8
R/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0h
76543210
TSTIOEN7TSTIOEN6TSTIOEN5TSTIOEN4TSTIOEN3TSTIOEN2TSTIOEN1TSTIOEN0
R/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0h
Table 31-135 TSCTL Field Descriptions
BitFieldTypeResetDescription
31-24KEYR-0/W0hneed to write (KEY=0xC5) to update this register
C5h = This field must be written with 0xC5 to be able to clear any of the enable bits
23-21RESERVEDR0h
20TSCAPTURER/WK0hDefines the capture method of the RTC timestamp when a time stamp event occurs.

KEY must be set to C5h to write to this bit.


0h = Time stamp holds RTC capture at first occurrence of time stamp event.
1h = Time stamp holds RTC capture at last occurrence of time stamp event.
19-17RESERVEDR0h
16TSVDDENR/WK0hTime Stamp by VDD Loss detection enable

KEY must be set to C5h to write to this bit.


0h = function disabled
1h = function enabled
15TSTIOEN15R/WK0hTime Stamp by Tamper I/O 15 enable

KEY must be set to C5h to write to this bit.


0h = function disabled
1h = function enabled
14TSTIOEN14R/WK0hTime Stamp by Tamper I/O 14 enable

KEY must be set to C5h to write to this bit.


0h = function disabled
1h = function enabled
13TSTIOEN13R/WK0hTime Stamp by Tamper I/O 13 enable

KEY must be set to C5h to write to this bit.


0h = function disabled
1h = function enabled
12TSTIOEN12R/WK0hTime Stamp by Tamper I/O 12 enable

KEY must be set to C5h to write to this bit.


0h = function disabled
1h = function enabled
11TSTIOEN11R/WK0hTime Stamp by Tamper I/O 11 enable

KEY must be set to C5h to write to this bit.


0h = function disabled
1h = function enabled
10TSTIOEN10R/WK0hTime Stamp by Tamper I/O 10 enable

KEY must be set to C5h to write to this bit.


0h = function disabled
1h = function enabled
9TSTIOEN9R/WK0hTime Stamp by Tamper I/O 9 enable

KEY must be set to C5h to write to this bit.


0h = function disabled
1h = function enabled
8TSTIOEN8R/WK0hTime Stamp by Tamper I/O 8 enable

KEY must be set to C5h to write to this bit.


0h = function disabled
1h = function enabled
7TSTIOEN7R/WK0hTime Stamp by Tamper I/O 7 enable

KEY must be set to C5h to write to this bit.


0h = function disabled
1h = function enabled
6TSTIOEN6R/WK0hTime Stamp by Tamper I/O 6 enable

KEY must be set to C5h to write to this bit.


0h = function disabled
1h = function enabled
5TSTIOEN5R/WK0hTime Stamp by Tamper I/O 5 enable

KEY must be set to C5h to write to this bit.


0h = function disabled
1h = function enabled
4TSTIOEN4R/WK0hTime Stamp by Tamper I/O 4 enable

KEY must be set to C5h to write to this bit.


0h = function disabled
1h = function enabled
3TSTIOEN3R/WK0hTime Stamp by Tamper I/O 3 enable

KEY must be set to C5h to write to this bit.


0h = function disabled
1h = function enabled
2TSTIOEN2R/WK0hTime Stamp by Tamper I/O 2 enable

KEY must be set to C5h to write to this bit.


0h = function disabled
1h = function enabled
1TSTIOEN1R/WK0hTime Stamp by Tamper I/O 1 enable

KEY must be set to C5h to write to this bit.


0h = function disabled
1h = function enabled
0TSTIOEN0R/WK0hTime Stamp by Tamper I/O 0 enable

KEY must be set to C5h to write to this bit.


0h = function disabled
1h = function enabled

30.10.46 TSCLR (Offset = 1170h) [Reset = 00000000h]

TSCLR is shown in Figure 31-54 and described in Table 31-136.

Return to the Summary Table.

time stamp clear register

Figure 31-140 TSCLR
31302928272625242322212019181716
KEYRESERVED
R-0/W-0hR-0h
1514131211109876543210
RESERVEDCLR
R-0hWK-0h
Table 31-136 TSCLR Field Descriptions
BitFieldTypeResetDescription
31-24KEYR-0/W0hneed to write (KEY=0xE2) to update this register
E2h = This field must be written with 0xE2 to be able to clear any of the enable bits
23-1RESERVEDR0h
0CLRWK0hClear time stamp and status register.

KEY must be set to E2h to write to this bit.


0h = Writing 0 has no effect
1h = clear time stamp event

30.10.47 LFSSRST (Offset = 11F0h) [Reset = 00000000h]

LFSSRST is shown in Figure 31-55 and described in Table 31-137.

Return to the Summary Table.

Low frequency subsystem reset request. Asserting the VBATPOR bit in this register will issue a power cycle on the battery backup domain. This reset has the same effect as removing and reconnecting the power supply to the VBAT power pin.
This register can be write protected by the RTCLOCK register.

Figure 31-141 LFSSRST
3130292827262524
KEY
R-0/W-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDVBATPOR
R-0hR/WK-0h
Table 31-137 LFSSRST Field Descriptions
BitFieldTypeResetDescription
31-24KEYR-0/W0hneed to write (KEY=0x12) to update this register
12h = This field must be written with 0x12 to be able to request the power on reset.
23-1RESERVEDR0h
0VBATPORR/WK0hIf set, the register bit will request a power on reset to the PMU of the LFSS.

KEY must be set to 12h to write to this bit.


0h = Writing this value has no effect.
1h = Request power on reset to the LFSS.

30.10.48 RTCLOCK (Offset = 11FCh) [Reset = 00000000h]

RTCLOCK is shown in Figure 31-56 and described in Table 31-138.

Return to the Summary Table.

The RTC lock bit protects the CLKCTL, SEC, MIN, HOUR, DAY, MON, YEAR and LFSSRST registers from accidental updates.

Figure 31-142 RTCLOCK
3130292827262524
KEY
R-0/W-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDPROTECT
R-0hR/WK-0h
Table 31-138 RTCLOCK Field Descriptions
BitFieldTypeResetDescription
31-24KEYR-0/W0hneed to write (KEY=0x22) to update this register
22h = This field must be written with 0x22 to be able to update any of the bits.
23-1RESERVEDR0h
0PROTECTR/WK0hIf set, the register bit will protect the CLKCTL, SEC, MIN, HOUR, DAY, MON, YEAR and LFSSRST from accidental writes.

KEY must be set to 22h to write to this bit.


0h = RTC counter is writable.
1h = RTC counter is read only access.

30.10.49 TIOCTL[y] (Offset = 1200h + formula) [Reset = 00000000h]

TIOCTL[y] is shown in Figure 31-57 and described in Table 31-139.

Return to the Summary Table.

tamper I/O control register

Offset = 1200h + (y * 4h); where y = 0h to Fh

Figure 31-143 TIOCTL[y]
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDOUTINVINENAPIPUPIPD
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVEDFILTERENRESERVEDPOLARITY
R-0hR/W-0hR-0hR/W-0h
76543210
RESERVEDTOUTSELRESERVEDIOMUX
R-0hRmodify/W-0hR-0hR/W-0h
Table 31-139 TIOCTL[y] Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR0h
19OUTINVR/W0hOutput inversion enable
0h = The output inversion is disabled.
1h = The output inversion is enabled.
18INENAR/W0hinput enable
0h = The input path is disabled.
1h = The input path is enabled.
17PIPUR/W0hpull up enable
0h = The pull-up function is disabled.
1h = The pull-up function is enabled.
16PIPDR/W0hpull down enable
0h = The pull-down function is disabled.
1h = The pull-down function is enabled.
15-14RESERVEDR0h
13-12FILTERENR/W0hProgrammable counter length of digital glitch filter for TIO0
0h = no filter on the tamper I/O beyond CDC synchronization sample
1h = 1 FLCLK minimum sample (30us)
2h = 3 LFCLK minimum sample (100us)
3h = 6 LFCLK minimum sample (200us)
11-10RESERVEDR0h
9-8POLARITYR/W0hEnables and configures edge detection polarity for TIO
0h = Edge detection disabled
1h = Detects rising edge of input event
2h = Detects falling edge of input event
3h = Detects both rising and falling edge of input event
7-6RESERVEDR0h
5-4TOUTSELRmodify/W0hSelects the source for TOUT control
0h = The TOUT register is the source for TOUT
1h = The LFCLK is the source for TOUT
2h = The heart beat generator is the source for TOUT
3h = The time stamp event status is the source for TOUT
3-1RESERVEDR0h
0IOMUXR/W0htamper I/O is controlled by SoC IOMUX module
0h = The tamper I/O is controlled by the IOMUX of the SoC and does allow assignment to a peripheral function. In the case the main supply (VDD) is lost, this I/O will go into a Hi-Z state.
1h = The tamper I/O is controlled by the TIOCTL register and stays functional during loss of the main supply (VDD).

30.10.50 TOUT3_0 (Offset = 1280h) [Reset = 00000000h]

TOUT3_0 is shown in Figure 31-58 and described in Table 31-140.

Return to the Summary Table.

Tamper I/O output for pins configured as TIO3 to TIO0.

Figure 31-144 TOUT3_0
3130292827262524
RESERVEDTIO3
R-0hR/W-0h
2322212019181716
RESERVEDTIO2
R-0hR/W-0h
15141312111098
RESERVEDTIO1
R-0hR/W-0h
76543210
RESERVEDTIO0
R-0hR/W-0h
Table 31-140 TOUT3_0 Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0h
24TIO3R/W0hThis bit sets the value of the pin tamper I/O 3 (TIO3) when the output is enabled through TOE3 register.
0h = Output is set to 0
1h = Output is set to 1
23-17RESERVEDR0h
16TIO2R/W0hThis bit sets the value of the pin tamper I/O 2 (TIO0) when the output is enabled through TOE2 register.
0h = Output is set to 0
1h = Output is set to 1
15-9RESERVEDR0h
8TIO1R/W0hThis bit sets the value of the pin tamper I/O 1 (TIO1) when the output is enabled through TOE1 register.
0h = Output is set to 0
1h = Output is set to 1
7-1RESERVEDR0h
0TIO0R/W0hThis bit sets the value of the pin tamper I/O 0 (TIO0) when the output is enabled through TOE0 register.
0h = Output is set to 0
1h = Output is set to 1

30.10.51 TOUT7_4 (Offset = 1284h) [Reset = 00000000h]

TOUT7_4 is shown in Figure 31-59 and described in Table 31-141.

Return to the Summary Table.

Tamper I/O output for pins configured as TIO7 to TIO4.

Figure 31-145 TOUT7_4
3130292827262524
RESERVEDTIO7
R-0hR/W-0h
2322212019181716
RESERVEDTIO6
R-0hR/W-0h
15141312111098
RESERVEDTIO5
R-0hR/W-0h
76543210
RESERVEDTIO4
R-0hR/W-0h
Table 31-141 TOUT7_4 Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0h
24TIO7R/W0hThis bit sets the value of the pin tamper I/O 7 (TIO7) when the output is enabled through TOE7 register.
0h = Output is set to 0
1h = Output is set to 1
23-17RESERVEDR0h
16TIO6R/W0hThis bit sets the value of the pin tamper I/O 2 (TIO6) when the output is enabled through TOE6 register.
0h = Output is set to 0
1h = Output is set to 1
15-9RESERVEDR0h
8TIO5R/W0hThis bit sets the value of the pin tamper I/O 5 (TIO5) when the output is enabled through TOE5 register.
0h = Output is set to 0
1h = Output is set to 1
7-1RESERVEDR0h
0TIO4R/W0hThis bit sets the value of the pin tamper I/O 4 (TIO4) when the output is enabled through TOE4 register.
0h = Output is set to 0
1h = Output is set to 1

30.10.52 TOUT11_8 (Offset = 1288h) [Reset = 00000000h]

TOUT11_8 is shown in Figure 31-60 and described in Table 31-142.

Return to the Summary Table.

Tamper I/O output for pins configured as TIO11 to TIO8.

Figure 31-146 TOUT11_8
3130292827262524
RESERVEDTIO11
R-0hR/W-0h
2322212019181716
RESERVEDTIO10
R-0hR/W-0h
15141312111098
RESERVEDTIO9
R-0hR/W-0h
76543210
RESERVEDTIO8
R-0hR/W-0h
Table 31-142 TOUT11_8 Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0h
24TIO11R/W0hThis bit sets the value of the pin tamper I/O 11 (TIO11) when the output is enabled through TOE11 register.
0h = Output is set to 0
1h = Output is set to 1
23-17RESERVEDR0h
16TIO10R/W0hThis bit sets the value of the pin tamper I/O 10 (TIO10) when the output is enabled through TOE10 register.
0h = Output is set to 0
1h = Output is set to 1
15-9RESERVEDR0h
8TIO9R/W0hThis bit sets the value of the pin tamper I/O 9 (TIO9) when the output is enabled through TOE9 register.
0h = Output is set to 0
1h = Output is set to 1
7-1RESERVEDR0h
0TIO8R/W0hThis bit sets the value of the pin tamper I/O 8 (TIO8) when the output is enabled through TOE8 register.
0h = Output is set to 0
1h = Output is set to 1

30.10.53 TOUT15_12 (Offset = 128Ch) [Reset = 00000000h]

TOUT15_12 is shown in Figure 31-61 and described in Table 31-143.

Return to the Summary Table.

Tamper I/O output for pins configured as TIO15 to TIO12.

Figure 31-147 TOUT15_12
3130292827262524
RESERVEDTIO15
R-0hR/W-0h
2322212019181716
RESERVEDTIO14
R-0hR/W-0h
15141312111098
RESERVEDTIO13
R-0hR/W-0h
76543210
RESERVEDTIO12
R-0hR/W-0h
Table 31-143 TOUT15_12 Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0h
24TIO15R/W0hThis bit sets the value of the pin tamper I/O 15 (TIO15) when the output is enabled through TOE15 register.
0h = Output is set to 0
1h = Output is set to 1
23-17RESERVEDR0h
16TIO14R/W0hThis bit sets the value of the pin tamper I/O 14 (TIO14) when the output is enabled through TOE14 register.
0h = Output is set to 0
1h = Output is set to 1
15-9RESERVEDR0h
8TIO13R/W0hThis bit sets the value of the pin tamper I/O 13 (TIO13) when the output is enabled through TOE13 register.
0h = Output is set to 0
1h = Output is set to 1
7-1RESERVEDR0h
0TIO12R/W0hThis bit sets the value of the pin tamper I/O 12 (TIO12) when the output is enabled through TOE12 register.
0h = Output is set to 0
1h = Output is set to 1

30.10.54 TOE3_0 (Offset = 1290h) [Reset = 00000000h]

TOE3_0 is shown in Figure 31-62 and described in Table 31-144.

Return to the Summary Table.

Tamper I/O output enable for pins configured as TIO3 to TIO0.

Figure 31-148 TOE3_0
3130292827262524
RESERVEDTIO3
R-0hR/W-0h
2322212019181716
RESERVEDTIO2
R-0hR/W-0h
15141312111098
RESERVEDTIO1
R-0hR/W-0h
76543210
RESERVEDTIO0
R-0hR/W-0h
Table 31-144 TOE3_0 Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0h
24TIO3R/W0hEnables data output for tamper I/O 3
0h = output disabled
1h = output enabled
23-17RESERVEDR0h
16TIO2R/W0hEnables data output for tamper I/O 2
0h = output disabled
1h = output enabled
15-9RESERVEDR0h
8TIO1R/W0hEnables data output for tamper I/O 1
0h = output disabled
1h = output enabled
7-1RESERVEDR0h
0TIO0R/W0hEnables data output for tamper I/O 0
0h = output disabled
1h = output enabled

30.10.55 TOE7_4 (Offset = 1294h) [Reset = 00000000h]

TOE7_4 is shown in Figure 31-63 and described in Table 31-145.

Return to the Summary Table.

Tamper I/O output enable for pins configured as TIO7 to TIO4.

Figure 31-149 TOE7_4
3130292827262524
RESERVEDTIO7
R-0hR/W-0h
2322212019181716
RESERVEDTIO6
R-0hR/W-0h
15141312111098
RESERVEDTIO5
R-0hR/W-0h
76543210
RESERVEDTIO4
R-0hR/W-0h
Table 31-145 TOE7_4 Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0h
24TIO7R/W0hEnables data output for tamper I/O 7
0h = output disabled
1h = output enabled
23-17RESERVEDR0h
16TIO6R/W0hEnables data output for tamper I/O 6
0h = output disabled
1h = output enabled
15-9RESERVEDR0h
8TIO5R/W0hEnables data output for tamper I/O 5
0h = output disabled
1h = output enabled
7-1RESERVEDR0h
0TIO4R/W0hEnables data output for tamper I/O 4
0h = output disabled
1h = output enabled

30.10.56 TOE11_8 (Offset = 1298h) [Reset = 00000000h]

TOE11_8 is shown in Figure 31-64 and described in Table 31-146.

Return to the Summary Table.

Tamper I/O output enable for pins configured as TIO11 to TIO8.

Figure 31-150 TOE11_8
3130292827262524
RESERVEDTIO11
R-0hR/W-0h
2322212019181716
RESERVEDTIO10
R-0hR/W-0h
15141312111098
RESERVEDTIO9
R-0hR/W-0h
76543210
RESERVEDTIO8
R-0hR/W-0h
Table 31-146 TOE11_8 Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0h
24TIO11R/W0hEnables data output for tamper I/O 11
0h = output disabled
1h = output enabled
23-17RESERVEDR0h
16TIO10R/W0hEnables data output for tamper I/O 10
0h = output disabled
1h = output enabled
15-9RESERVEDR0h
8TIO9R/W0hEnables data output for tamper I/O 9
0h = output disabled
1h = output enabled
7-1RESERVEDR0h
0TIO8R/W0hEnables data output for tamper I/O 8
0h = output disabled
1h = output enabled

30.10.57 TOE15_12 (Offset = 129Ch) [Reset = 00000000h]

TOE15_12 is shown in Figure 31-65 and described in Table 31-147.

Return to the Summary Table.

Tamper I/O output enable for pins configured as TIO15 to TIO12.

Figure 31-151 TOE15_12
3130292827262524
RESERVEDTIO15
R-0hR/W-0h
2322212019181716
RESERVEDTIO14
R-0hR/W-0h
15141312111098
RESERVEDTIO13
R-0hR/W-0h
76543210
RESERVEDTIO12
R-0hR/W-0h
Table 31-147 TOE15_12 Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0h
24TIO15R/W0hEnables data output for tamper I/O 15
0h = output disabled
1h = output enabled
23-17RESERVEDR0h
16TIO14R/W0hEnables data output for tamper I/O 14
0h = output disabled
1h = output enabled
15-9RESERVEDR0h
8TIO13R/W0hEnables data output for tamper I/O 13
0h = output disabled
1h = output enabled
7-1RESERVEDR0h
0TIO12R/W0hEnables data output for tamper I/O 12
0h = output disabled
1h = output enabled

30.10.58 TIN3_0 (Offset = 12A0h) [Reset = 00000000h]

TIN3_0 is shown in Figure 31-66 and described in Table 31-148.

Return to the Summary Table.

Tamper I/O inputs for pins configured as TIO3 to TIO0.

Figure 31-152 TIN3_0
3130292827262524
RESERVEDTIO3
R-0hR-0h
2322212019181716
RESERVEDTIO2
R-0hR-0h
15141312111098
RESERVEDTIO1
R-0hR-0h
76543210
RESERVEDTIO0
R-0hR-0h
Table 31-148 TIN3_0 Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0h
24TIO3R0hThis bit reads the data input value of tamper I/O 3.
0h = Input value is 0
1h = Input value is 1
23-17RESERVEDR0h
16TIO2R0hThis bit reads the data input value of tamper I/O 2.
0h = Input value is 0
1h = Input value is 1
15-9RESERVEDR0h
8TIO1R0hThis bit reads the data input value of tamper I/O 1.
0h = Input value is 0
1h = Input value is 1
7-1RESERVEDR0h
0TIO0R0hThis bit reads the data input value of tamper I/O 0.
0h = Input value is 0
1h = Input value is 1

30.10.59 TIN7_4 (Offset = 12A4h) [Reset = 00000000h]

TIN7_4 is shown in Figure 31-67 and described in Table 31-149.

Return to the Summary Table.

Tamper I/O inputs for pins configured as TIO7 to TIO4.

Figure 31-153 TIN7_4
3130292827262524
RESERVEDTIO7
R-0hR-0h
2322212019181716
RESERVEDTIO6
R-0hR-0h
15141312111098
RESERVEDTIO5
R-0hR-0h
76543210
RESERVEDTIO4
R-0hR-0h
Table 31-149 TIN7_4 Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0h
24TIO7R0hThis bit reads the data input value of tamper I/O 7.
0h = Input value is 0
1h = Input value is 1
23-17RESERVEDR0h
16TIO6R0hThis bit reads the data input value of tamper I/O 6.
0h = Input value is 0
1h = Input value is 1
15-9RESERVEDR0h
8TIO5R0hThis bit reads the data input value of tamper I/O 5.
0h = Input value is 0
1h = Input value is 1
7-1RESERVEDR0h
0TIO4R0hThis bit reads the data input value of tamper I/O 4.
0h = Input value is 0
1h = Input value is 1

30.10.60 TIN11_8 (Offset = 12A8h) [Reset = 00000000h]

TIN11_8 is shown in Figure 31-68 and described in Table 31-150.

Return to the Summary Table.

Tamper I/O inputs for pins configured as TIO11 to TIO8.

Figure 31-154 TIN11_8
3130292827262524
RESERVEDTIO11
R-0hR-0h
2322212019181716
RESERVEDTIO10
R-0hR-0h
15141312111098
RESERVEDTIO9
R-0hR-0h
76543210
RESERVEDTIO8
R-0hR-0h
Table 31-150 TIN11_8 Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0h
24TIO11R0hThis bit reads the data input value of tamper I/O 11.
0h = Input value is 0
1h = Input value is 1
23-17RESERVEDR0h
16TIO10R0hThis bit reads the data input value of tamper I/O 10.
0h = Input value is 0
1h = Input value is 1
15-9RESERVEDR0h
8TIO9R0hThis bit reads the data input value of tamper I/O 9.
0h = Input value is 0
1h = Input value is 1
7-1RESERVEDR0h
0TIO8R0hThis bit reads the data input value of tamper I/O 8.
0h = Input value is 0
1h = Input value is 1

30.10.61 TIN15_12 (Offset = 12ACh) [Reset = 00000000h]

TIN15_12 is shown in Figure 31-69 and described in Table 31-151.

Return to the Summary Table.

Tamper I/O inputs for pins configured as TIO15 to TIO12.

Figure 31-155 TIN15_12
3130292827262524
RESERVEDTIO15
R-0hR-0h
2322212019181716
RESERVEDTIO14
R-0hR-0h
15141312111098
RESERVEDTIO13
R-0hR-0h
76543210
RESERVEDTIO12
R-0hR-0h
Table 31-151 TIN15_12 Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR0h
24TIO15R0hThis bit reads the data input value of tamper I/O 15.
0h = Input value is 0
1h = Input value is 1
23-17RESERVEDR0h
16TIO14R0hThis bit reads the data input value of tamper I/O 14.
0h = Input value is 0
1h = Input value is 1
15-9RESERVEDR0h
8TIO13R0hThis bit reads the data input value of tamper I/O 13.
0h = Input value is 0
1h = Input value is 1
7-1RESERVEDR0h
0TIO12R0hThis bit reads the data input value of tamper I/O 12.
0h = Input value is 0
1h = Input value is 1

30.10.62 HEARTBEAT (Offset = 12C0h) [Reset = 00000000h]

HEARTBEAT is shown in Figure 31-70 and described in Table 31-152.

Return to the Summary Table.

The configuration register for the heart beat generator

Figure 31-156 HEARTBEAT
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDHBMODE
R-0hR/W-0h
15141312111098
RESERVEDHBWIDTH
R-0hR/W-0h
76543210
RESERVEDHBINTERVAL
R-0hR/W-0h
Table 31-152 HEARTBEAT Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0h
17-16HBMODER/W0hHeart beat mode
0h = Heart beat disabled
1h = Heart beat always enabled
2h = Heart beat enabled when time stamp event detected
3h = Heart beat when VDD has fail condition
15-11RESERVEDR0h
10-8HBWIDTHR/W0hHeart beat interval width
0h = Heart beat pulse width 1msec
1h = Heart beat pulse width 2msec
2h = Heart beat pulse width 4msec
3h = Heart beat pulse width 8msec
4h = Heart beat pulse width 16msec
5h = Heart beat pulse width 32msec
6h = Heart beat pulse width 64msec
7h = Heart beat pulse width 128msec
7-3RESERVEDR0h
2-0HBINTERVALR/W0hHeart beat interval
0h = Heart beat interval 0.125 sec
1h = Heart beat interval 0.25 sec
2h = Heart beat interval 0.5 sec
3h = Heart beat interval 1 sec
4h = Heart beat interval 2 sec
5h = Heart beat interval 4 sec
6h = Heart beat interval 8 sec
7h = Heart beat interval 16 sec

30.10.63 TIOLOCK (Offset = 12FCh) [Reset = 00000000h]

TIOLOCK is shown in Figure 31-71 and described in Table 31-153.

Return to the Summary Table.

The TIO lock bit protects the TIOCTL and HEARTBEAT registers from accidental updates.

Figure 31-157 TIOLOCK
3130292827262524
KEY
R-0/W-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDPROTECT
R-0hR/WK-0h
Table 31-153 TIOLOCK Field Descriptions
BitFieldTypeResetDescription
31-24KEYR-0/W0hneed to write (KEY=0x18) to update this register
18h = This field must be written with 0x18 to be able to clear any of the enable bits
23-1RESERVEDR0h
0PROTECTR/WK0hIf set, the register bit will protect the TIOCTL and HEARTBEAT from accidental writes.

KEY must be set to 18h to write to this bit.


0h = Tamper I/O control is writable.
1h = Tamper I/O control is read only access.

30.10.64 WDTEN (Offset = 1300h) [Reset = 00000000h]

WDTEN is shown in Figure 31-72 and described in Table 31-154.

Return to the Summary Table.

Watchdog Timer Enable Register.
This register can be made read only access by the WDTLOCK register.

Figure 31-158 WDTEN
3130292827262524
KEY
R-0/W-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDENABLE
R-0hR/WK-0h
Table 31-154 WDTEN Field Descriptions
BitFieldTypeResetDescription
31-24KEYR-0/W0hKEY to allow write access to this register. Writing to this register with an incorrect key causes a POR level reset. Read as 0.
EEh = This field must be written with 0xEE to be update the enable bit.
23-1RESERVEDR0h
0ENABLER/WK0hEnable bit for the WDT.

KEY must be set to EEh to write to this bit.


0h = Disable WDT
1h = Enable WDT

30.10.65 WDTDBGCTL (Offset = 1304h) [Reset = 00000000h]

WDTDBGCTL is shown in Figure 31-73 and described in Table 31-155.

Return to the Summary Table.

Watchdog Timer Debug Control

Figure 31-159 WDTDBGCTL
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDFREE
R-0hR/W-0h
Table 31-155 WDTDBGCTL Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h
0FREER/W0hFree run control
0h = The WDT freezes functionality while the CPU is Halted during debug and resumes when the CPU is active.
1h = The WDT ignores the state of the CPU Halted debug state.

30.10.66 WDTCTL (Offset = 1308h) [Reset = 00000043h]

WDTCTL is shown in Figure 31-74 and described in Table 31-156.

Return to the Summary Table.

Watchdog Timer Control Register.
This register can be made read only access by the WDTLOCK register.

Figure 31-160 WDTCTL
3130292827262524
KEY
R-0/W-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDPERRESERVEDCLKDIV
R-0hR/WK-4hR-0hR/WK-3h
Table 31-156 WDTCTL Field Descriptions
BitFieldTypeResetDescription
31-24KEYR-0/W0hKEY to allow write access to this register. Writing to this register with an incorrect key causes a POR level reset. Read as 0.
C6h = This field must be written with 0xC6 to be able to write any of the enable bits
23-7RESERVEDR0h
6-4PERR/WK4hTimer Period of the WDT. These bits select the total watchdog timer count.

KEY must be set to C6h to write to this bit.


0h = Total timer count is 225
1h = Total timer count is 221
2h = Total timer count is 218
3h = Total timer count is 215
4h = Total timer count is 212 (default)
5h = Total timer count is 210
6h = Total timer count is 28
7h = Total timer count is 26
3RESERVEDR0h
2-0CLKDIVR/WK3hModule Clock Divider, Divide the clock source by CLKDIV+1. Divider values from /1 to /8 are possible.

KEY must be set to C6h to write to this bit.


0h = Minimum value
7h = Maximum value

30.10.67 WDTCNTRST (Offset = 130Ch) [Reset = 00000000h]

WDTCNTRST is shown in Figure 31-75 and described in Table 31-157.

Return to the Summary Table.

Watchdog Timer Counter Reset Register

Figure 31-161 WDTCNTRST
313029282726252423222120191817161514131211109876543210
RESTART
R-0/W-0h
Table 31-157 WDTCNTRST Field Descriptions
BitFieldTypeResetDescription
31-0RESTARTR-0/W0hWriting 03A7h to this register restarts the WDT Counter. Writing any other value causes a POR level reset. Read as 0x0h.
0h = Minimum value
000003A7h = VALUE to restart the WDT counter
FFFFFFFFh = Maximum value

30.10.68 WDTSTAT (Offset = 1310h) [Reset = 00000000h]

WDTSTAT is shown in Figure 31-76 and described in Table 31-158.

Return to the Summary Table.

Watchdog Timer Status Register

Figure 31-162 WDTSTAT
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDRUN
R-0hR-0h
Table 31-158 WDTSTAT Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h
0RUNR0hWatchdog running status flag.
0h = Watchdog counter stopped.
1h = Watchdog running.

30.10.69 WDTLOCK (Offset = 13FCh) [Reset = 00000000h]

WDTLOCK is shown in Figure 31-77 and described in Table 31-159.

Return to the Summary Table.

The WDT lock bit protects the WDTEN and WDTCTL registers from accidental updates.

Figure 31-163 WDTLOCK
3130292827262524
KEY
R-0/W-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDPROTECT
R-0hR/WK-0h
Table 31-159 WDTLOCK Field Descriptions
BitFieldTypeResetDescription
31-24KEYR-0/W0hneed to write (KEY=0xBD) to update this register
BDh = This field must be written with 0xBD to be able to clear any of the enable bits
23-1RESERVEDR0h
0PROTECTR/WK0hIf set, the register bit will protect the WDTEN and WDTCTL from accidental writes.

KEY must be set to BDh to write to this bit.


0h = Watchdog timer control is writable.
1h = Watchdog timer control is read only access.

30.10.70 SPMEM[y] (Offset = 1400h + formula) [Reset = 00000000h]

SPMEM[y] is shown in Figure 31-78 and described in Table 31-160.

Return to the Summary Table.

Scratch pad memory

Offset = 1400h + (y * 4h); where y = 0h to 1Fh

Figure 31-164 SPMEM[y]
313029282726252423222120191817161514131211109876543210
DATA3DATA2DATA1DATA0
R/W-0hR/W-0hR/W-0hR/W-0h
Table 31-160 SPMEM[y] Field Descriptions
BitFieldTypeResetDescription
31-24DATA3R/W0hmemory data byte 3
0h = Smallest value
FFh = Highest possible value
23-16DATA2R/W0hmemory data byte 2
0h = Smallest value
FFh = Highest possible value
15-8DATA1R/W0hmemory data byte 1
0h = Smallest value
FFh = Highest possible value
7-0DATA0R/W0hmemory data byte 0
0h = Smallest value
FFh = Highest possible value

30.10.71 SPMWPROT0 (Offset = 1500h) [Reset = 00000000h]

SPMWPROT0 is shown in Figure 31-79 and described in Table 31-161.

Return to the Summary Table.

Scratch pad memory write protect 0

Figure 31-165 SPMWPROT0
3130292827262524
KEY
R-0/W-0h
2322212019181716
RESERVED
R-0h
15141312111098
WP_3_3WP_3_2WP_3_1WP_3_0WP_2_3WP_2_2WP_2_1WP_2_0
R/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0h
76543210
WP_1_3WP_1_2WP_1_1WP_1_0WP_0_3WP_0_2WP_0_1WP_0_0
R/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0h
Table 31-161 SPMWPROT0 Field Descriptions
BitFieldTypeResetDescription
31-24KEYR-0/W0hneed to write (KEY=0xE8) to update this register
E8h = This field must be written with 0xE8 to be update the write protect bits.
23-16RESERVEDR0h
15WP_3_3R/WK0hwrite protect SPMEM3 - DATA3

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
14WP_3_2R/WK0hwrite protect SPMEM3 - DATA2

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
13WP_3_1R/WK0hwrite protect SPMEM3 - DATA1

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
12WP_3_0R/WK0hwrite protect SPMEM3 - DATA0

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
11WP_2_3R/WK0hwrite protect SPMEM2 - DATA3

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
10WP_2_2R/WK0hwrite protect SPMEM2 - DATA2

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
9WP_2_1R/WK0hwrite protect SPMEM2 - DATA1

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
8WP_2_0R/WK0hwrite protect SPMEM2 - DATA0

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
7WP_1_3R/WK0hwrite protect SPMEM1 - DATA3

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
6WP_1_2R/WK0hwrite protect SPMEM1 - DATA2

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
5WP_1_1R/WK0hwrite protect SPMEM1 - DATA1

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
4WP_1_0R/WK0hwrite protect SPMEM1 - DATA0

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
3WP_0_3R/WK0hwrite protect SPMEM0 - DATA3

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
2WP_0_2R/WK0hwrite protect SPMEM0 - DATA2

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
1WP_0_1R/WK0hwrite protect SPMEM0 - DATA1

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
0WP_0_0R/WK0hwrite protect SPMEM0 - DATA0

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access

30.10.72 SPMWPROT1 (Offset = 1504h) [Reset = 00000000h]

SPMWPROT1 is shown in Figure 31-80 and described in Table 31-162.

Return to the Summary Table.

Scratch pad memory write protect 1

Figure 31-166 SPMWPROT1
3130292827262524
KEY
R-0/W-0h
2322212019181716
RESERVED
R-0h
15141312111098
WP_7_3WP_7_2WP_7_1WP_7_0WP_6_3WP_6_2WP_6_1WP_6_0
R/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0h
76543210
WP_5_3WP_5_2WP_5_1WP_5_0WP_4_3WP_4_2WP_4_1WP_4_0
R/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0h
Table 31-162 SPMWPROT1 Field Descriptions
BitFieldTypeResetDescription
31-24KEYR-0/W0hneed to write (KEY=0xE8) to update this register
E8h = This field must be written with 0xE8 to be update the write protect bits.
23-16RESERVEDR0h
15WP_7_3R/WK0hwrite protect SPMEM7 - DATA3

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
14WP_7_2R/WK0hwrite protect SPMEM7 - DATA2

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
13WP_7_1R/WK0hwrite protect SPMEM7 - DATA1

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
12WP_7_0R/WK0hwrite protect SPMEM7 - DATA0

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
11WP_6_3R/WK0hwrite protect SPMEM6 - DATA3

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
10WP_6_2R/WK0hwrite protect SPMEM6 - DATA2

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
9WP_6_1R/WK0hwrite protect SPMEM6 - DATA1

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
8WP_6_0R/WK0hwrite protect SPMEM6 - DATA0

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
7WP_5_3R/WK0hwrite protect SPMEM5 - DATA3

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
6WP_5_2R/WK0hwrite protect SPMEM5 - DATA2

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
5WP_5_1R/WK0hwrite protect SPMEM5 - DATA1

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
4WP_5_0R/WK0hwrite protect SPMEM5 - DATA0

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
3WP_4_3R/WK0hwrite protect SPMEM4 - DATA3

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
2WP_4_2R/WK0hwrite protect SPMEM4 - DATA2

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
1WP_4_1R/WK0hwrite protect SPMEM4 - DATA1

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
0WP_4_0R/WK0hwrite protect SPMEM4 - DATA0

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access

30.10.73 SPMWPROT2 (Offset = 1508h) [Reset = 00000000h]

SPMWPROT2 is shown in Figure 31-81 and described in Table 31-163.

Return to the Summary Table.

Scratch pad memory write protect 2

Figure 31-167 SPMWPROT2
3130292827262524
KEY
R-0/W-0h
2322212019181716
RESERVED
R-0h
15141312111098
WP_11_3WP_11_2WP_11_1WP_11_0WP_10_3WP_10_2WP_10_1WP_10_0
R/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0h
76543210
WP_9_3WP_9_2WP_9_1WP_9_0WP_8_3WP_8_2WP_8_1WP_8_0
R/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0h
Table 31-163 SPMWPROT2 Field Descriptions
BitFieldTypeResetDescription
31-24KEYR-0/W0hneed to write (KEY=0xE8) to update this register
E8h = This field must be written with 0xE8 to be update the write protect bits.
23-16RESERVEDR0h
15WP_11_3R/WK0hwrite protect SPMEM11 - DATA3

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
14WP_11_2R/WK0hwrite protect SPMEM11 - DATA2

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
13WP_11_1R/WK0hwrite protect SPMEM11 - DATA1

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
12WP_11_0R/WK0hwrite protect SPMEM11 - DATA0

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
11WP_10_3R/WK0hwrite protect SPMEM10 - DATA3

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
10WP_10_2R/WK0hwrite protect SPMEM610- DATA2

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
9WP_10_1R/WK0hwrite protect SPMEM10 - DATA1

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
8WP_10_0R/WK0hwrite protect SPMEM10 - DATA0

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
7WP_9_3R/WK0hwrite protect SPMEM9 - DATA3

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
6WP_9_2R/WK0hwrite protect SPMEM9 - DATA2

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
5WP_9_1R/WK0hwrite protect SPMEM9 - DATA1

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
4WP_9_0R/WK0hwrite protect SPMEM9 - DATA0

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
3WP_8_3R/WK0hwrite protect SPMEM8 - DATA3

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
2WP_8_2R/WK0hwrite protect SPMEM8 - DATA2

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
1WP_8_1R/WK0hwrite protect SPMEM8 - DATA1

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
0WP_8_0R/WK0hwrite protect SPMEM8 - DATA0

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access

30.10.74 SPMWPROT3 (Offset = 150Ch) [Reset = 00000000h]

SPMWPROT3 is shown in Figure 31-82 and described in Table 31-164.

Return to the Summary Table.

Scratch pad memory write protect 3

Figure 31-168 SPMWPROT3
3130292827262524
KEY
R-0/W-0h
2322212019181716
RESERVED
R-0h
15141312111098
WP_15_3WP_15_2WP_15_1WP_15_0WP_14_3WP_14_2WP_14_1WP_14_0
R/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0h
76543210
WP_13_3WP_13_2WP_13_1WP_13_0WP_12_3WP_12_2WP_12_1WP_12_0
R/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0h
Table 31-164 SPMWPROT3 Field Descriptions
BitFieldTypeResetDescription
31-24KEYR-0/W0hneed to write (KEY=0xE8) to update this register
E8h = This field must be written with 0xE8 to be update the write protect bits.
23-16RESERVEDR0h
15WP_15_3R/WK0hwrite protect SPMEM15 - DATA3

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
14WP_15_2R/WK0hwrite protect SPMEM15 - DATA2

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
13WP_15_1R/WK0hwrite protect SPMEM15 - DATA1

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
12WP_15_0R/WK0hwrite protect SPMEM15 - DATA0

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
11WP_14_3R/WK0hwrite protect SPMEM14 - DATA3

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
10WP_14_2R/WK0hwrite protect SPMEM14- DATA2

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
9WP_14_1R/WK0hwrite protect SPMEM14 - DATA1

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
8WP_14_0R/WK0hwrite protect SPMEM14 - DATA0

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
7WP_13_3R/WK0hwrite protect SPMEM13 - DATA3

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
6WP_13_2R/WK0hwrite protect SPMEM13 - DATA2

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
5WP_13_1R/WK0hwrite protect SPMEM13 - DATA1

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
4WP_13_0R/WK0hwrite protect SPMEM13 - DATA0

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
3WP_12_3R/WK0hwrite protect SPMEM12 - DATA3

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
2WP_12_2R/WK0hwrite protect SPMEM12 - DATA2

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
1WP_12_1R/WK0hwrite protect SPMEM12 - DATA1

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
0WP_12_0R/WK0hwrite protect SPMEM12 - DATA0

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access

30.10.75 SPMWPROT4 (Offset = 1510h) [Reset = 00000000h]

SPMWPROT4 is shown in Figure 31-83 and described in Table 31-165.

Return to the Summary Table.

Scratch pad memory write protect 4

Figure 31-169 SPMWPROT4
3130292827262524
KEY
R-0/W-0h
2322212019181716
RESERVED
R-0h
15141312111098
WP_19_3WP_19_2WP_19_1WP_19_0WP_18_3WP_18_2WP_18_1WP_18_0
R/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0h
76543210
WP_17_3WP_17_2WP_17_1WP_17_0WP_16_3WP_16_2WP_16_1WP_16_0
R/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0h
Table 31-165 SPMWPROT4 Field Descriptions
BitFieldTypeResetDescription
31-24KEYR-0/W0hneed to write (KEY=0xE8) to update this register
E8h = This field must be written with 0xE8 to be update the write protect bits.
23-16RESERVEDR0h
15WP_19_3R/WK0hwrite protect SPMEM19 - DATA3

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
14WP_19_2R/WK0hwrite protect SPMEM19 - DATA2

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
13WP_19_1R/WK0hwrite protect SPMEM19 - DATA1

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
12WP_19_0R/WK0hwrite protect SPMEM19 - DATA0

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
11WP_18_3R/WK0hwrite protect SPMEM18 - DATA3

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
10WP_18_2R/WK0hwrite protect SPMEM18- DATA2

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
9WP_18_1R/WK0hwrite protect SPMEM18 - DATA1

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
8WP_18_0R/WK0hwrite protect SPMEM18 - DATA0

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
7WP_17_3R/WK0hwrite protect SPMEM17 - DATA3

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
6WP_17_2R/WK0hwrite protect SPMEM17 - DATA2

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
5WP_17_1R/WK0hwrite protect SPMEM17 - DATA1

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
4WP_17_0R/WK0hwrite protect SPMEM17 - DATA0

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
3WP_16_3R/WK0hwrite protect SPMEM16 - DATA3

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
2WP_16_2R/WK0hwrite protect SPMEM16 - DATA2

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
1WP_16_1R/WK0hwrite protect SPMEM16 - DATA1

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
0WP_16_0R/WK0hwrite protect SPMEM16 - DATA0

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access

30.10.76 SPMWPROT5 (Offset = 1514h) [Reset = 00000000h]

SPMWPROT5 is shown in Figure 31-84 and described in Table 31-166.

Return to the Summary Table.

Scratch pad memory write protect 5

Figure 31-170 SPMWPROT5
3130292827262524
KEY
R-0/W-0h
2322212019181716
RESERVED
R-0h
15141312111098
WP_23_3WP_23_2WP_23_1WP_23_0WP_22_3WP_22_2WP_22_1WP_22_0
R/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0h
76543210
WP_21_3WP_21_2WP_21_1WP_21_0WP_20_3WP_20_2WP_20_1WP_20_0
R/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0h
Table 31-166 SPMWPROT5 Field Descriptions
BitFieldTypeResetDescription
31-24KEYR-0/W0hneed to write (KEY=0xE8) to update this register
E8h = This field must be written with 0xE8 to be update the write protect bits.
23-16RESERVEDR0h
15WP_23_3R/WK0hwrite protect SPMEM23 - DATA3

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
14WP_23_2R/WK0hwrite protect SPMEM23 - DATA2

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
13WP_23_1R/WK0hwrite protect SPMEM23 - DATA1

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
12WP_23_0R/WK0hwrite protect SPMEM23 - DATA0

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
11WP_22_3R/WK0hwrite protect SPMEM22 - DATA3

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
10WP_22_2R/WK0hwrite protect SPMEM22- DATA2

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
9WP_22_1R/WK0hwrite protect SPMEM22 - DATA1

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
8WP_22_0R/WK0hwrite protect SPMEM22 - DATA0

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
7WP_21_3R/WK0hwrite protect SPMEM21 - DATA3

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
6WP_21_2R/WK0hwrite protect SPMEM21 - DATA2

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
5WP_21_1R/WK0hwrite protect SPMEM21 - DATA1

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
4WP_21_0R/WK0hwrite protect SPMEM21 - DATA0

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
3WP_20_3R/WK0hwrite protect SPMEM20 - DATA3

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
2WP_20_2R/WK0hwrite protect SPMEM20 - DATA2

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
1WP_20_1R/WK0hwrite protect SPMEM20 - DATA1

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
0WP_20_0R/WK0hwrite protect SPMEM20 - DATA0

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access

30.10.77 SPMWPROT6 (Offset = 1518h) [Reset = 00000000h]

SPMWPROT6 is shown in Figure 31-85 and described in Table 31-167.

Return to the Summary Table.

Scratch pad memory write protect 6

Figure 31-171 SPMWPROT6
3130292827262524
KEY
R-0/W-0h
2322212019181716
RESERVED
R-0h
15141312111098
WP_27_3WP_27_2WP_27_1WP_27_0WP_26_3WP_26_2WP_26_1WP_26_0
R/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0h
76543210
WP_25_3WP_25_2WP_25_1WP_25_0WP_24_3WP_24_2WP_24_1WP_24_0
R/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0h
Table 31-167 SPMWPROT6 Field Descriptions
BitFieldTypeResetDescription
31-24KEYR-0/W0hneed to write (KEY=0xE8) to update this register
E8h = This field must be written with 0xE8 to be update the write protect bits.
23-16RESERVEDR0h
15WP_27_3R/WK0hwrite protect SPMEM27 - DATA3

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
14WP_27_2R/WK0hwrite protect SPMEM27 - DATA2

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
13WP_27_1R/WK0hwrite protect SPMEM27 - DATA1

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
12WP_27_0R/WK0hwrite protect SPMEM27 - DATA0

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
11WP_26_3R/WK0hwrite protect SPMEM26 - DATA3

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
10WP_26_2R/WK0hwrite protect SPMEM26- DATA2

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
9WP_26_1R/WK0hwrite protect SPMEM26 - DATA1

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
8WP_26_0R/WK0hwrite protect SPMEM26 - DATA0

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
7WP_25_3R/WK0hwrite protect SPMEM25 - DATA3

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
6WP_25_2R/WK0hwrite protect SPMEM25 - DATA2

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
5WP_25_1R/WK0hwrite protect SPMEM25 - DATA1

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
4WP_25_0R/WK0hwrite protect SPMEM25 - DATA0

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
3WP_24_3R/WK0hwrite protect SPMEM24 - DATA3

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
2WP_24_2R/WK0hwrite protect SPMEM24 - DATA2

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
1WP_24_1R/WK0hwrite protect SPMEM24 - DATA1

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
0WP_24_0R/WK0hwrite protect SPMEM24 - DATA0

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access

30.10.78 SPMWPROT7 (Offset = 151Ch) [Reset = 00000000h]

SPMWPROT7 is shown in Figure 31-86 and described in Table 31-168.

Return to the Summary Table.

Scratch pad memory write protect 7

Figure 31-172 SPMWPROT7
3130292827262524
KEY
R-0/W-0h
2322212019181716
RESERVED
R-0h
15141312111098
WP_31_3WP_31_2WP_31_1WP_31_0WP_30_3WP_30_2WP_30_1WP_30_0
R/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0h
76543210
WP_29_3WP_29_2WP_29_1WP_29_0WP_28_3WP_28_2WP_28_1WP_28_0
R/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0h
Table 31-168 SPMWPROT7 Field Descriptions
BitFieldTypeResetDescription
31-24KEYR-0/W0hneed to write (KEY=0xE8) to update this register
E8h = This field must be written with 0xE8 to be update the write protect bits.
23-16RESERVEDR0h
15WP_31_3R/WK0hwrite protect SPMEM31 - DATA3

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
14WP_31_2R/WK0hwrite protect SPMEM31 - DATA2

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
13WP_31_1R/WK0hwrite protect SPMEM31 - DATA1

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
12WP_31_0R/WK0hwrite protect SPMEM31 - DATA0

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
11WP_30_3R/WK0hwrite protect SPMEM30 - DATA3

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
10WP_30_2R/WK0hwrite protect SPMEM30- DATA2

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
9WP_30_1R/WK0hwrite protect SPMEM30 - DATA1

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
8WP_30_0R/WK0hwrite protect SPMEM30 - DATA0

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
7WP_29_3R/WK0hwrite protect SPMEM29 - DATA3

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
6WP_29_2R/WK0hwrite protect SPMEM29 - DATA2

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
5WP_29_1R/WK0hwrite protect SPMEM29 - DATA1

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
4WP_29_0R/WK0hwrite protect SPMEM29 - DATA0

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
3WP_28_3R/WK0hwrite protect SPMEM28 - DATA3

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
2WP_28_2R/WK0hwrite protect SPMEM28 - DATA2

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
1WP_28_1R/WK0hwrite protect SPMEM28 - DATA1

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access
0WP_28_0R/WK0hwrite protect SPMEM28 - DATA0

KEY must be set to E8h to write to this bit.


0h = SPMEM is read and write access
1h = SPMEM is read only access

30.10.79 SPMTERASE0 (Offset = 1540h) [Reset = 00000000h]

SPMTERASE0 is shown in Figure 31-87 and described in Table 31-169.

Return to the Summary Table.

Scratch pad memory tamper erase enable 0

Figure 31-173 SPMTERASE0
3130292827262524
KEY
R-0/W-0h
2322212019181716
RESERVED
R-0h
15141312111098
TE_3_3TE_3_2TE_3_1TE_3_0TE_2_3TE_2_2TE_2_1TE_2_0
R/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0h
76543210
TE_1_3TE_1_2TE_1_1TE_1_0TE_0_3TE_0_2TE_0_1TE_0_0
R/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0h
Table 31-169 SPMTERASE0 Field Descriptions
BitFieldTypeResetDescription
31-24KEYR-0/W0hneed to write (KEY=0xA3) to update this register
A3h = This field must be written with 0xA3 to be update the tamper erase enable bit.
23-16RESERVEDR0h
15TE_3_3R/WK0htamper erase enable SPMEM3 - DATA3

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
14TE_3_2R/WK0htamper erase enable SPMEM3 - DATA2

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
13TE_3_1R/WK0htamper erase enable SPMEM3 - DATA1

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
12TE_3_0R/WK0htamper erase enable SPMEM3 - DATA0

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
11TE_2_3R/WK0htamper erase enable SPMEM2 - DATA3

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
10TE_2_2R/WK0htamper erase enable SPMEM2 - DATA2

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
9TE_2_1R/WK0htamper erase enable SPMEM2 - DATA1

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
8TE_2_0R/WK0htamper erase enable SPMEM2 - DATA0

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
7TE_1_3R/WK0htamper erase enable SPMEM1 - DATA3

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
6TE_1_2R/WK0htamper erase enable SPMEM1 - DATA2

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
5TE_1_1R/WK0htamper erase enable SPMEM1 - DATA1

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
4TE_1_0R/WK0htamper erase enable SPMEM1 - DATA0

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
3TE_0_3R/WK0htamper erase enable SPMEM0 - DATA3

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
2TE_0_2R/WK0htamper erase enable SPMEM0 - DATA2

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
1TE_0_1R/WK0htamper erase enable SPMEM0 - DATA1

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
0TE_0_0R/WK0htamper erase enable SPMEM0 - DATA0

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event

30.10.80 SPMTERASE1 (Offset = 1544h) [Reset = 00000000h]

SPMTERASE1 is shown in Figure 31-88 and described in Table 31-170.

Return to the Summary Table.

Scratch pad memory tamper erase enable 1

Figure 31-174 SPMTERASE1
3130292827262524
KEY
R-0/W-0h
2322212019181716
RESERVED
R-0h
15141312111098
TE_7_3TE_7_2TE_7_1TE_7_0TE_6_3TE_6_2TE_6_1TE_6_0
R/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0h
76543210
TE_5_3TE_5_2TE_5_1TE_5_0TE_4_3TE_4_2TE_4_1TE_4_0
R/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0h
Table 31-170 SPMTERASE1 Field Descriptions
BitFieldTypeResetDescription
31-24KEYR-0/W0hneed to write (KEY=0xA3) to update this register
A3h = This field must be written with 0xA3 to be update the tamper erase enable bit.
23-16RESERVEDR0h
15TE_7_3R/WK0htamper erase enable SPMEM7 - DATA3

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
14TE_7_2R/WK0htamper erase enable SPMEM7 - DATA2

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
13TE_7_1R/WK0htamper erase enable SPMEM7 - DATA1

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
12TE_7_0R/WK0htamper erase enable SPMEM7 - DATA0

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
11TE_6_3R/WK0htamper erase enable SPMEM6 - DATA3

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
10TE_6_2R/WK0htamper erase enable SPMEM6 - DATA2

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
9TE_6_1R/WK0htamper erase enable SPMEM6 - DATA1

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
8TE_6_0R/WK0htamper erase enable SPMEM6 - DATA0

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
7TE_5_3R/WK0htamper erase enable SPMEM5 - DATA3

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
6TE_5_2R/WK0htamper erase enable SPMEM5 - DATA2

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
5TE_5_1R/WK0htamper erase enable SPMEM5 - DATA1

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
4TE_5_0R/WK0htamper erase enable SPMEM5 - DATA0

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
3TE_4_3R/WK0htamper erase enable SPMEM4 - DATA3

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
2TE_4_2R/WK0htamper erase enable SPMEM4 - DATA2

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
1TE_4_1R/WK0htamper erase enable SPMEM4 - DATA1

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
0TE_4_0R/WK0htamper erase enable SPMEM4 - DATA0

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event

30.10.81 SPMTERASE2 (Offset = 1548h) [Reset = 00000000h]

SPMTERASE2 is shown in Figure 31-89 and described in Table 31-171.

Return to the Summary Table.

Scratch pad memory tamper erase enable 2

Figure 31-175 SPMTERASE2
3130292827262524
KEY
R-0/W-0h
2322212019181716
RESERVED
R-0h
15141312111098
TE_11_3TE_11_2TE_11_1TE_11_0TE_10_3TE_10_2TE_10_1TE_10_0
R/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0h
76543210
TE_9_3TE_9_2TE_9_1TE_9_0TE_8_3TE_8_2TE_8_1TE_8_0
R/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0h
Table 31-171 SPMTERASE2 Field Descriptions
BitFieldTypeResetDescription
31-24KEYR-0/W0hneed to write (KEY=0xA3) to update this register
A3h = This field must be written with 0xA3 to be update the tamper erase enable bit.
23-16RESERVEDR0h
15TE_11_3R/WK0htamper erase enable SPMEM11 - DATA3

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
14TE_11_2R/WK0htamper erase enable SPMEM11 - DATA2

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
13TE_11_1R/WK0htamper erase enable SPMEM11 - DATA1

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
12TE_11_0R/WK0htamper erase enable SPMEM11 - DATA0

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
11TE_10_3R/WK0htamper erase enable SPMEM10 - DATA3

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
10TE_10_2R/WK0htamper erase enable SPMEM10 - DATA2

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
9TE_10_1R/WK0htamper erase enable SPMEM10 - DATA1

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
8TE_10_0R/WK0htamper erase enable SPMEM10 - DATA0

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
7TE_9_3R/WK0htamper erase enable SPMEM9 - DATA3

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
6TE_9_2R/WK0htamper erase enable SPMEM9 - DATA2

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
5TE_9_1R/WK0htamper erase enable SPMEM9 - DATA1

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
4TE_9_0R/WK0htamper erase enable SPMEM9 - DATA0

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
3TE_8_3R/WK0htamper erase enable SPMEM8 - DATA3

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
2TE_8_2R/WK0htamper erase enable SPMEM8 - DATA2

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
1TE_8_1R/WK0htamper erase enable SPMEM8 - DATA1

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
0TE_8_0R/WK0htamper erase enable SPMEM8 - DATA0

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event

30.10.82 SPMTERASE3 (Offset = 154Ch) [Reset = 00000000h]

SPMTERASE3 is shown in Figure 31-90 and described in Table 31-172.

Return to the Summary Table.

Scratch pad memory tamper erase enable 3

Figure 31-176 SPMTERASE3
3130292827262524
KEY
R-0/W-0h
2322212019181716
RESERVED
R-0h
15141312111098
TE_15_3TE_15_2TE_15_1TE_15_0TE_14_3TE_14_2TE_14_1TE_14_0
R/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0h
76543210
TE_13_3TE_13_2TE_13_1TE_13_0TE_12_3TE_12_2TE_12_1TE_12_0
R/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0h
Table 31-172 SPMTERASE3 Field Descriptions
BitFieldTypeResetDescription
31-24KEYR-0/W0hneed to write (KEY=0xA3) to update this register
A3h = This field must be written with 0xA3 to be update the tamper erase enable bit.
23-16RESERVEDR0h
15TE_15_3R/WK0htamper erase enable SPMEM15 - DATA3

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
14TE_15_2R/WK0htamper erase enable SPMEM15 - DATA2

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
13TE_15_1R/WK0htamper erase enable SPMEM15 - DATA1

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
12TE_15_0R/WK0htamper erase enable SPMEM15 - DATA0

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
11TE_14_3R/WK0htamper erase enable SPMEM14 - DATA3

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
10TE_14_2R/WK0htamper erase enable SPMEM14 - DATA2

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
9TE_14_1R/WK0htamper erase enable SPMEM14 - DATA1

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
8TE_14_0R/WK0htamper erase enable SPMEM14 - DATA0

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
7TE_13_3R/WK0htamper erase enable SPMEM13 - DATA3

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
6TE_13_2R/WK0htamper erase enable SPMEM13 - DATA2

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
5TE_13_1R/WK0htamper erase enable SPMEM13 - DATA1

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
4TE_13_0R/WK0htamper erase enable SPMEM13 - DATA0

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
3TE_12_3R/WK0htamper erase enable SPMEM12 - DATA3

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
2TE_12_2R/WK0htamper erase enable SPMEM12 - DATA2

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
1TE_12_1R/WK0htamper erase enable SPMEM12 - DATA1

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
0TE_12_0R/WK0htamper erase enable SPMEM12 - DATA0

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event

30.10.83 SPMTERASE4 (Offset = 1550h) [Reset = 00000000h]

SPMTERASE4 is shown in Figure 31-91 and described in Table 31-173.

Return to the Summary Table.

Scratch pad memory tamper erase enable 4

Figure 31-177 SPMTERASE4
3130292827262524
KEY
R-0/W-0h
2322212019181716
RESERVED
R-0h
15141312111098
TE_19_3TE_19_2TE_19_1TE_19_0TE_18_3TE_18_2TE_18_1TE_18_0
R/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0h
76543210
TE_17_3TE_17_2TE_17_1TE_17_0TE_16_3TE_16_2TE_16_1TE_16_0
R/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0h
Table 31-173 SPMTERASE4 Field Descriptions
BitFieldTypeResetDescription
31-24KEYR-0/W0hneed to write (KEY=0xA3) to update this register
A3h = This field must be written with 0xA3 to be update the tamper erase enable bit.
23-16RESERVEDR0h
15TE_19_3R/WK0htamper erase enable SPMEM19 - DATA3

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
14TE_19_2R/WK0htamper erase enable SPMEM19 - DATA2

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
13TE_19_1R/WK0htamper erase enable SPMEM19 - DATA1

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
12TE_19_0R/WK0htamper erase enable SPMEM19 - DATA0

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
11TE_18_3R/WK0htamper erase enable SPMEM18 - DATA3

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
10TE_18_2R/WK0htamper erase enable SPMEM18 - DATA2

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
9TE_18_1R/WK0htamper erase enable SPMEM18 - DATA1

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
8TE_18_0R/WK0htamper erase enable SPMEM18 - DATA0

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
7TE_17_3R/WK0htamper erase enable SPMEM17 - DATA3

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
6TE_17_2R/WK0htamper erase enable SPMEM17 - DATA2

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
5TE_17_1R/WK0htamper erase enable SPMEM17 - DATA1

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
4TE_17_0R/WK0htamper erase enable SPMEM17 - DATA0

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
3TE_16_3R/WK0htamper erase enable SPMEM16 - DATA3

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
2TE_16_2R/WK0htamper erase enable SPMEM16 - DATA2

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
1TE_16_1R/WK0htamper erase enable SPMEM16 - DATA1

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
0TE_16_0R/WK0htamper erase enable SPMEM16 - DATA0

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event

30.10.84 SPMTERASE5 (Offset = 1554h) [Reset = 00000000h]

SPMTERASE5 is shown in Figure 31-92 and described in Table 31-174.

Return to the Summary Table.

Scratch pad memory tamper erase enable 5

Figure 31-178 SPMTERASE5
3130292827262524
KEY
R-0/W-0h
2322212019181716
RESERVED
R-0h
15141312111098
TE_23_3TE_23_2TE_23_1TE_23_0TE_22_3TE_22_2TE_22_1TE_22_0
R/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0h
76543210
TE_21_3TE_21_2TE_21_1TE_21_0TE_20_3TE_20_2TE_20_1TE_20_0
R/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0h
Table 31-174 SPMTERASE5 Field Descriptions
BitFieldTypeResetDescription
31-24KEYR-0/W0hneed to write (KEY=0xA3) to update this register
A3h = This field must be written with 0xA3 to be update the tamper erase enable bit.
23-16RESERVEDR0h
15TE_23_3R/WK0htamper erase enable SPMEM23 - DATA3

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
14TE_23_2R/WK0htamper erase enable SPMEM23 - DATA2

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
13TE_23_1R/WK0htamper erase enable SPMEM23 - DATA1

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
12TE_23_0R/WK0htamper erase enable SPMEM23 - DATA0

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
11TE_22_3R/WK0htamper erase enable SPMEM22 - DATA3

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
10TE_22_2R/WK0htamper erase enable SPMEM22 - DATA2

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
9TE_22_1R/WK0htamper erase enable SPMEM22 - DATA1

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
8TE_22_0R/WK0htamper erase enable SPMEM22 - DATA0

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
7TE_21_3R/WK0htamper erase enable SPMEM21 - DATA3

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
6TE_21_2R/WK0htamper erase enable SPMEM21 - DATA2

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
5TE_21_1R/WK0htamper erase enable SPMEM21 - DATA1

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
4TE_21_0R/WK0htamper erase enable SPMEM21 - DATA0

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
3TE_20_3R/WK0htamper erase enable SPMEM20 - DATA3

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
2TE_20_2R/WK0htamper erase enable SPMEM20 - DATA2

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
1TE_20_1R/WK0htamper erase enable SPMEM20 - DATA1

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
0TE_20_0R/WK0htamper erase enable SPMEM20 - DATA0

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event

30.10.85 SPMTERASE6 (Offset = 1558h) [Reset = 00000000h]

SPMTERASE6 is shown in Figure 31-93 and described in Table 31-175.

Return to the Summary Table.

Scratch pad memory tamper erase enable 6

Figure 31-179 SPMTERASE6
3130292827262524
KEY
R-0/W-0h
2322212019181716
RESERVED
R-0h
15141312111098
TE_27_3TE_27_2TE_27_1TE_27_0TE_26_3TE_26_2TE_26_1TE_26_0
R/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0h
76543210
TE_25_3TE_25_2TE_25_1TE_25_0TE_24_3TE_24_2TE_24_1TE_24_0
R/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0h
Table 31-175 SPMTERASE6 Field Descriptions
BitFieldTypeResetDescription
31-24KEYR-0/W0hneed to write (KEY=0xA3) to update this register
A3h = This field must be written with 0xA3 to be update the tamper erase enable bit.
23-16RESERVEDR0h
15TE_27_3R/WK0htamper erase enable SPMEM27 - DATA3

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
14TE_27_2R/WK0htamper erase enable SPMEM27 - DATA2

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
13TE_27_1R/WK0htamper erase enable SPMEM27 - DATA1

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
12TE_27_0R/WK0htamper erase enable SPMEM27 - DATA0

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
11TE_26_3R/WK0htamper erase enable SPMEM26 - DATA3

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
10TE_26_2R/WK0htamper erase enable SPMEM26 - DATA2

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
9TE_26_1R/WK0htamper erase enable SPMEM26 - DATA1

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
8TE_26_0R/WK0htamper erase enable SPMEM26 - DATA0

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
7TE_25_3R/WK0htamper erase enable SPMEM25 - DATA3

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
6TE_25_2R/WK0htamper erase enable SPMEM25 - DATA2

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
5TE_25_1R/WK0htamper erase enable SPMEM25 - DATA1

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
4TE_25_0R/WK0htamper erase enable SPMEM25 - DATA0

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
3TE_24_3R/WK0htamper erase enable SPMEM24 - DATA3

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
2TE_24_2R/WK0htamper erase enable SPMEM24 - DATA2

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
1TE_24_1R/WK0htamper erase enable SPMEM24 - DATA1

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
0TE_24_0R/WK0htamper erase enable SPMEM24 - DATA0

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event

30.10.86 SPMTERASE7 (Offset = 155Ch) [Reset = 00000000h]

SPMTERASE7 is shown in Figure 31-94 and described in Table 31-176.

Return to the Summary Table.

Scratch pad memory tamper erase enable 7

Figure 31-180 SPMTERASE7
3130292827262524
KEY
R-0/W-0h
2322212019181716
RESERVED
R-0h
15141312111098
TE_31_3TE_31_2TE_31_1TE_31_0TE_30_3TE_30_2TE_30_1TE_30_0
R/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0h
76543210
TE_29_3TE_29_2TE_29_1TE_29_0TE_28_3TE_28_2TE_28_1TE_28_0
R/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0hR/WK-0h
Table 31-176 SPMTERASE7 Field Descriptions
BitFieldTypeResetDescription
31-24KEYR-0/W0hneed to write (KEY=0xA3) to update this register
A3h = This field must be written with 0xA3 to be update the tamper erase enable bit.
23-16RESERVEDR0h
15TE_31_3R/WK0htamper erase enable SPMEM31 - DATA3

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
14TE_31_2R/WK0htamper erase enable SPMEM31 - DATA2

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
13TE_31_1R/WK0htamper erase enable SPMEM31 - DATA1

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
12TE_31_0R/WK0htamper erase enable SPMEM31 - DATA0

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
11TE_30_3R/WK0htamper erase enable SPMEM30 - DATA3

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
10TE_30_2R/WK0htamper erase enable SPMEM30 - DATA2

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
9TE_30_1R/WK0htamper erase enable SPMEM30 - DATA1

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
8TE_30_0R/WK0htamper erase enable SPMEM30 - DATA0

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
7TE_29_3R/WK0htamper erase enable SPMEM29 - DATA3

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
6TE_29_2R/WK0htamper erase enable SPMEM29 - DATA2

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
5TE_29_1R/WK0htamper erase enable SPMEM29 - DATA1

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
4TE_29_0R/WK0htamper erase enable SPMEM29 - DATA0

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
3TE_28_3R/WK0htamper erase enable SPMEM28 - DATA3

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
2TE_28_2R/WK0htamper erase enable SPMEM28 - DATA2

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
1TE_28_1R/WK0htamper erase enable SPMEM28 - DATA1

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event
0TE_28_0R/WK0htamper erase enable SPMEM28 - DATA0

KEY must be set to A3h to write to this bit.


0h = SPMEM is unmodified during tamper event
1h = SPMEM will be erased with tamper event