SLAU847F October   2022  â€“ March 2026 MSPM0L1105 , MSPM0L1106 , MSPM0L1116 , MSPM0L1117 , MSPM0L1227 , MSPM0L1227-Q1 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346 , MSPM0L2116 , MSPM0L2117 , MSPM0L2227 , MSPM0L2227-Q1 , MSPM0L2228 , MSPM0L2228-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation
    5.     Support Resources
    6.     Trademarks
  3. 1 Architecture
    1. 1.1 Architecture Overview
    2. 1.2 Bus Organization
    3. 1.3 Platform Memory Map
      1. 1.3.1 Code Region
      2. 1.3.2 SRAM Region
      3. 1.3.3 Peripheral Region
      4. 1.3.4 Subsystem Region
      5. 1.3.5 System PPB Region
    4. 1.4 Boot Configuration
      1. 1.4.1 Configuration Memory (NONMAIN)
        1. 1.4.1.1 CRC-Backed Configuration Data
        2. 1.4.1.2 16-bit Pattern Match for Critical Fields
      2. 1.4.2 Boot Configuration Routine (BCR)
        1. 1.4.2.1 Serial Wire Debug Related Policies
          1. 1.4.2.1.1 SWD Security Level 0
          2. 1.4.2.1.2 SWD Security Level 1
          3. 1.4.2.1.3 SWD Security Level 2
        2. 1.4.2.2 SWD Mass Erase and Factory Reset Commands
        3. 1.4.2.3 Flash Memory Protection and Integrity Related Policies
          1. 1.4.2.3.1 Locking the Application (MAIN) Flash Memory
          2. 1.4.2.3.2 Locking the Configuration (NONMAIN) Flash Memory
          3. 1.4.2.3.3 Static Write Protection NONMAIN Fields
        4. 1.4.2.4 Application CRC Verification
        5. 1.4.2.5 Fast Boot
        6. 1.4.2.6 Bootstrap Loader (BSL) Enable/Disable Policy
          1. 1.4.2.6.1 BSL Enable
      3. 1.4.3 Bootstrap Loader (BSL)
        1. 1.4.3.1 GPIO Invoke
        2. 1.4.3.2 Bootstrap Loader (BSL) Security Policies
          1. 1.4.3.2.1 BSL Access Password
          2. 1.4.3.2.2 BSL Read-out Policy
          3. 1.4.3.2.3 BSL Security Alert Policy
        3. 1.4.3.3 Application Version
        4. 1.4.3.4 BSL Triggered Mass Erase and Factory Reset
      4. 1.4.4 NONMAIN Layout Types
      5. 1.4.5 NONMAIN_TYPEA Registers
      6. 1.4.6 NONMAIN_TYPEC Registers
      7. 1.4.7 NONMAIN_TYPEE Registers
    5. 1.5 Factory Constants
      1. 1.5.1 FACTORYREGION Layout Types
      2. 1.5.2 FACTORYREGION_TYPEA Registers
      3. 1.5.3 FACTORYREGION_TYPEC Registers
      4. 1.5.4 FACTORYREGION_TYPED Registers
      5. 1.5.5 FACTORYREGION_TYPEE Registers
  4. 2 PMCU
    1. 2.1 PMCU Overview
      1. 2.1.1 Power Domains
      2. 2.1.2 Operating Modes
        1. 2.1.2.1 RUN Mode
        2. 2.1.2.2 SLEEP Mode
        3. 2.1.2.3 STOP Mode
        4. 2.1.2.4 STANDBY Mode
        5. 2.1.2.5 SHUTDOWN Mode
        6. 2.1.2.6 Supported Functionality by Operating Mode
        7. 2.1.2.7 Suspended Low-Power Mode Operation
    2. 2.2 Power Management (PMU)
      1. 2.2.1 Power Supply
      2. 2.2.2 Core Regulator
      3. 2.2.3 Supply Supervisors
        1. 2.2.3.1 Power-on Reset (POR)
        2. 2.2.3.2 Brownout Reset (BOR)
        3. 2.2.3.3 POR and BOR Behavior During Supply Changes
      4. 2.2.4 Bandgap Reference
      5. 2.2.5 VBOOST for Analog Muxes
      6. 2.2.6 Peripheral Enable
        1. 2.2.6.1 Automatic Peripheral Disable in Low Power Modes
    3. 2.3 Clock Module (CKM)
      1. 2.3.1 Oscillators
        1. 2.3.1.1 Internal Low-Frequency Oscillator (LFOSC)
        2. 2.3.1.2 Internal System Oscillator (SYSOSC)
          1. 2.3.1.2.1 SYSOSC Gear Shift
          2. 2.3.1.2.2 SYSOSC Frequency
          3. 2.3.1.2.3 SYSOSC Frequency Correction Loop
            1. 2.3.1.2.3.1 SYSOSC FCL in External Resistor Mode (ROSC)
            2. 2.3.1.2.3.2 SYSOSC FCL in Internal Resistor Mode
          4. 2.3.1.2.4 SYSOSC User Trim Procedure
          5. 2.3.1.2.5 Disabling SYSOSC
        3. 2.3.1.3 Low Frequency Crystal Oscillator (LFXT)
        4. 2.3.1.4 LFCLK_IN (Digital Clock)
        5. 2.3.1.5 High Frequency Crystal Oscillator (HFXT)
        6. 2.3.1.6 HFCLK_IN (Digital clock)
      2. 2.3.2 Clocks
        1. 2.3.2.1  MCLK (Main Clock) Tree
        2. 2.3.2.2  CPUCLK (Processor Clock)
        3. 2.3.2.3  ULPCLK (Low-Power Clock)
        4. 2.3.2.4  MFCLK (Middle Frequency Clock)
        5. 2.3.2.5  MFPCLK (Middle Frequency Precision Clock)
        6. 2.3.2.6  LFCLK (Low-Frequency Clock)
        7. 2.3.2.7  HFCLK (High-Frequency External Clock)
        8. 2.3.2.8  HSCLK (High Speed Clock)
        9. 2.3.2.9  ADCCLK (ADC Sample Period Clock)
        10. 2.3.2.10 CANCLK (CAN-FD Functional Clock)
        11. 2.3.2.11 RTCCLK (RTC Clock)
        12. 2.3.2.12 External Clock Output (CLK_OUT)
        13. 2.3.2.13 Direct Clock Connections for Infrastructure
      3. 2.3.3 Clock Tree
        1. 2.3.3.1 Peripheral Clock Source Selection
      4. 2.3.4 Clock Monitors
        1. 2.3.4.1 LFCLK Monitor
        2. 2.3.4.2 MCLK Monitor
        3. 2.3.4.3 Startup Monitors
          1. 2.3.4.3.1 LFOSC Startup Monitor
          2. 2.3.4.3.2 LFXT Startup Monitor
          3. 2.3.4.3.3 HFCLK Startup Monitor
          4. 2.3.4.3.4 HSCLK Status
      5. 2.3.5 Frequency Clock Counter (FCC)
        1. 2.3.5.1 Using the FCC
        2. 2.3.5.2 FCC Frequency Computation and Accuracy
    4. 2.4 System Controller (SYSCTL)
      1. 2.4.1  Resets and Device Initialization
        1. 2.4.1.1 Reset Levels
          1. 2.4.1.1.1 Power-on Reset (POR) Reset Level
          2. 2.4.1.1.2 Brownout Reset (BOR) Reset Level
          3. 2.4.1.1.3 Boot Reset (BOOTRST) Reset Level
          4. 2.4.1.1.4 System Reset (SYSRST) Reset Level
          5. 2.4.1.1.5 CPU-only Reset (CPURST) Reset Level
        2. 2.4.1.2 Initial Conditions After Power-Up
        3. 2.4.1.3 NRST Pin
        4. 2.4.1.4 SWD Pins
        5. 2.4.1.5 Generating Resets in Software
        6. 2.4.1.6 Reset Cause
        7. 2.4.1.7 Peripheral Reset Control
        8. 2.4.1.8 Boot Fail Handling
      2. 2.4.2  Operating Mode Selection
      3. 2.4.3  Asynchronous Fast Clock Requests
      4. 2.4.4  SRAM Write Protection
      5. 2.4.5  Flash Wait States
      6. 2.4.6  Flash Bank Address Swap
      7. 2.4.7  Shutdown Mode Handling (if present)
      8. 2.4.8  Configuration Lockout
      9. 2.4.9  System Status
      10. 2.4.10 Error Handling
      11. 2.4.11 SYSCTL Events
        1. 2.4.11.1 CPU Interrupt Event (CPU_INT)
        2. 2.4.11.2 Nonmaskable Interrupt Event (NMI)
    5. 2.5 SYSCTL Layout Types
    6. 2.6 SYSCTL_TYPEA Registers
    7. 2.7 SYSCTL_TYPEB Registers
    8. 2.8 SYSCTL_TYPEC Registers
    9. 2.9 Quick Start Reference
      1. 2.9.1 Default Device Configuration
      2. 2.9.2 Leveraging MFCLK
      3. 2.9.3 Optimizing Power Consumption in STOP Mode
      4. 2.9.4 Optimizing Power Consumption in STANDBY Mode
      5. 2.9.5 Increasing MCLK Precision
      6. 2.9.6 High Speed Clock (SYSPLL, HFCLK) Handling in Low-Power Modes
      7. 2.9.7 Optimizing for Lowest Wakeup Latency
      8. 2.9.8 Optimizing for Lowest Peak Current in RUN/SLEEP Mode
  5. 3 CPU
    1. 3.1 Overview
    2. 3.2 Arm Cortex-M0+ CPU
      1. 3.2.1 CPU Register File
      2. 3.2.2 Stack Behavior
      3. 3.2.3 Execution Modes and Privilege Levels
      4. 3.2.4 Address Space and Supported Data Sizes
    3. 3.3 Interrupts and Exceptions
      1. 3.3.1 Peripheral Interrupts (IRQs)
        1. 3.3.1.1 Nested Vectored Interrupt Controller (NVIC)
        2. 3.3.1.2 Interrupt Groups
        3. 3.3.1.3 Wake Up Controller (WUC)
      2. 3.3.2 Interrupt and Exception Table
      3. 3.3.3 Processor Lockup Scenario
    4. 3.4 CPU Peripherals
      1. 3.4.1 System Control Block (SCB)
      2. 3.4.2 System Tick Timer (SysTick)
    5. 3.5 Read-Only Memory (ROM)
    6. 3.6 CPUSS Registers
    7. 3.7 WUC Registers
  6. 4 SECURITY
    1. 4.1 Overview
      1. 4.1.1 Secure Boot
      2. 4.1.2 Customer Secure Code (CSC)
    2. 4.2 Boot and Startup Sequence
      1. 4.2.1 CSC Programming Overview
    3. 4.3 Secure Key Storage
    4. 4.4 Flash Memory Protection
      1. 4.4.1 Bank Swapping
      2. 4.4.2 Write Protection
      3. 4.4.3 Read-Execute Protection
      4. 4.4.4 IP Protection
      5. 4.4.5 Data Bank Protection
      6. 4.4.6 Hardware Monotonic Counter
    5. 4.5 SRAM Protection
    6. 4.6 SECURITY Registers
  7. 5 Direct Memory Access (DMA)
    1. 5.1 DMA Overview
    2. 5.2 DMA Operation
      1. 5.2.1  Addressing Modes
      2. 5.2.2  Channel Types
      3. 5.2.3  Transfer Modes
        1. 5.2.3.1 Single Transfer
        2. 5.2.3.2 Block Transfer
        3. 5.2.3.3 Repeated Single Transfer
        4. 5.2.3.4 Repeated Block Transfer
        5. 5.2.3.5 Stride Mode
      4. 5.2.4  Extended Modes
        1. 5.2.4.1 Fill Mode
        2. 5.2.4.2 Table Mode
      5. 5.2.5  Initiating DMA Transfers
      6. 5.2.6  Stopping DMA Transfers
      7. 5.2.7  Channel Priorities
      8. 5.2.8  Burst Block Mode
      9. 5.2.9  Using DMA with System Interrupts
      10. 5.2.10 DMA Controller Interrupts
      11. 5.2.11 DMA Trigger Event Status
      12. 5.2.12 DMA Operating Mode Support
        1. 5.2.12.1 Transfer in RUN Mode
        2. 5.2.12.2 Transfer in SLEEP Mode
        3. 5.2.12.3 Transfer in STOP Mode
        4. 5.2.12.4 Transfers in STANDBY Mode
      13. 5.2.13 DMA Address and Data Errors
      14. 5.2.14 Interrupt and Event Support
    3. 5.3 DMA Registers
  8. 6 NVM (Flash)
    1. 6.1 NVM Overview
      1. 6.1.1 Key Features
      2. 6.1.2 System Components
      3. 6.1.3 Terminology
    2. 6.2 Flash Memory Bank Organization
      1. 6.2.1 Banks
      2. 6.2.2 Flash Memory Regions
      3. 6.2.3 Addressing
        1. 6.2.3.1 Flash Memory Map
      4. 6.2.4 Memory Organization Examples
    3. 6.3 Flash Controller
      1. 6.3.1 Overview of Flash Controller Commands
      2. 6.3.2 NOOP Command
      3. 6.3.3 PROGRAM Command
        1. 6.3.3.1 Program Bit Masking Behavior
        2. 6.3.3.2 Programming Less Than One Flash Word
        3. 6.3.3.3 Target Data Alignment (Devices with Single Flash Word Programming Only)
        4. 6.3.3.4 Target Data Alignment (Devices With Multiword Programming)
        5. 6.3.3.5 Executing a PROGRAM Operation
      4. 6.3.4 ERASE Command
        1. 6.3.4.1 Erase Sector Masking Behavior
        2. 6.3.4.2 Executing an ERASE Operation
      5. 6.3.5 READVERIFY Command
        1. 6.3.5.1 Executing a READVERIFY Operation
      6. 6.3.6 BLANKVERIFY Command
        1. 6.3.6.1 Executing a BLANKVERIFY Operation
      7. 6.3.7 Command Diagnostics
        1. 6.3.7.1 Command Status
        2. 6.3.7.2 Address Translation
        3. 6.3.7.3 Pulse Counts
      8. 6.3.8 Overriding the System Address With a Bank ID, Region ID, and Bank Address
      9. 6.3.9 FLASHCTL Events
        1. 6.3.9.1 CPU Interrupt Event Publisher
    4. 6.4 Write Protection
      1. 6.4.1 Write Protection Resolution
      2. 6.4.2 Static Write Protection
      3. 6.4.3 Dynamic Write Protection
        1. 6.4.3.1 Configuring Protection for the MAIN Region
        2. 6.4.3.2 Configuring Protection for the NONMAIN Region
    5. 6.5 Read Interface
      1. 6.5.1 Bank Address Swapping
    6. 6.6 FLASHCTL Registers
  9. 7 Events
    1. 7.1 Events Overview
      1. 7.1.1 Event Publisher
      2. 7.1.2 Event Subscriber
      3. 7.1.3 Event Fabric Routing
        1. 7.1.3.1 CPU Interrupt Event Route (CPU_INT)
        2. 7.1.3.2 DMA Trigger Event Route (DMA_TRIGx)
        3. 7.1.3.3 Generic Event Route (GEN_EVENTx)
      4. 7.1.4 Event Routing Map
      5. 7.1.5 Event Propagation Latency
    2. 7.2 Events Operation
      1. 7.2.1 CPU Interrupt
      2. 7.2.2 DMA Trigger
      3. 7.2.3 Peripheral to Peripheral Event
      4. 7.2.4 Extended Module Description Register
      5. 7.2.5 Using Event Registers
        1. 7.2.5.1 Event Registers
        2. 7.2.5.2 Configuring Events
        3. 7.2.5.3 Responding to CPU Interrupts in Application Software
        4. 7.2.5.4 Hardware Event Handling
  10. 8 IOMUX
    1. 8.1 IOMUX Overview
      1. 8.1.1 IO Types and Analog Sharing
    2. 8.2 IOMUX Operation
      1. 8.2.1 Peripheral Function (PF) Assignment
      2. 8.2.2 Logic High to Hi-Z Conversion
      3. 8.2.3 Logic Inversion
      4. 8.2.4 SHUTDOWN Mode Wakeup Logic
      5. 8.2.5 Pullup/Pulldown Resistors
      6. 8.2.6 Drive Strength Control
      7. 8.2.7 Hysteresis and Logic Level Control
    3. 8.3 IOMUX Registers
  11. 9 General-Purpose Input/Output (GPIO)
    1. 9.1 GPIO Overview
    2. 9.2 GPIO Operation
      1. 9.2.1 GPIO Ports
      2. 9.2.2 GPIO Read/Write Interface
      3. 9.2.3 GPIO Input Glitch Filtering and Synchronization
      4. 9.2.4 GPIO Fast Wake
      5. 9.2.5 GPIO DMA Interface
      6. 9.2.6 Event Publishers and Subscribers
    3. 9.3 GPIO Registers
  12. 10AES
    1. 10.1 AES Overview
      1. 10.1.1 AESADV Performance
    2. 10.2 AESADV Operation
      1. 10.2.1 Loading the Key
      2. 10.2.2 Writing Input Data
      3. 10.2.3 Reading Output Data
      4. 10.2.4 Operation Descriptions
        1. 10.2.4.1 Single Block Operation
        2. 10.2.4.2 Electronic Codebook (ECB) Mode
          1. 10.2.4.2.1 ECB Encryption
          2. 10.2.4.2.2 ECB Decryption
        3. 10.2.4.3 Cipher Block Chaining (CBC) Mode
          1. 10.2.4.3.1 CBC Encryption
          2. 10.2.4.3.2 CBC Decryption
        4. 10.2.4.4 Output Feedback (OFB) Mode
          1. 10.2.4.4.1 OFB Encryption
          2. 10.2.4.4.2 OFB Decryption
        5. 10.2.4.5 Cipher Feedback (CFB) Mode
          1. 10.2.4.5.1 CFB Encryption
          2. 10.2.4.5.2 CFB Decryption
        6. 10.2.4.6 Counter (CTR) Mode
          1. 10.2.4.6.1 CTR Encryption
          2. 10.2.4.6.2 CTR Decryption
        7. 10.2.4.7 Galois Counter (GCM) Mode
          1. 10.2.4.7.1 GHASH Operation
          2. 10.2.4.7.2 GCM Operating Modes
            1. 10.2.4.7.2.1 Autonomous GCM Operation
              1. 10.2.4.7.2.1.1 GMAC
            2. 10.2.4.7.2.2 GCM With Pre-Calculations
            3. 10.2.4.7.2.3 GCM Operation With Precalculated H- and Y0-Encrypted Forced to Zero
        8. 10.2.4.8 Counter With Cipher Block Chaining Message Authentication Code (CCM)
          1. 10.2.4.8.1 CCM Operation
      5. 10.2.5 AES Events
        1. 10.2.5.1 CPU Interrupt Event Publisher (CPU_EVENT)
        2. 10.2.5.2 DMA Trigger Event Publisher (DMA_TRIG_DATAIN)
        3. 10.2.5.3 DMA Trigger Event Publisher (DMA_TRIG_DATAOUT)
    3. 10.3 AESADV Registers
  13. 11CRC
    1. 11.1 CRC Overview
      1. 11.1.1 CRC16-CCITT
      2. 11.1.2 CRC32-ISO3309
    2. 11.2 CRC Operation
      1. 11.2.1 CRC Generator Implementation
      2. 11.2.2 Configuration
        1. 11.2.2.1 Polynomial Selection
        2. 11.2.2.2 Bit Order
        3. 11.2.2.3 Byte Swap
        4. 11.2.2.4 Byte Order
        5. 11.2.2.5 CRC C Library Compatibility
    3. 11.3 CRCP0 Registers
  14. 12Keystore
    1. 12.1 Overview
    2. 12.2 Detailed Description
    3. 12.3 KEYSTORECTL Registers
  15. 13TRNG
    1. 13.1 TRNG Overview
    2. 13.2 TRNG Operation
      1. 13.2.1 TRNG Generation Data Path
      2. 13.2.2 Clock Configuration and Output Rate
      3. 13.2.3 Behavior in Low Power Modes
      4. 13.2.4 Health Tests
        1. 13.2.4.1 Digital Block Startup Self-Test
        2. 13.2.4.2 Analog Block Startup Self-Test
        3. 13.2.4.3 Runtime Health Test
          1. 13.2.4.3.1 Repetition Count Test
          2. 13.2.4.3.2 Adaptive Proportion Test
          3. 13.2.4.3.3 Handling Runtime Health Test Failures
      5. 13.2.5 Configuration
        1. 13.2.5.1 TRNG State Machine
          1. 13.2.5.1.1 Changing TRNG States
        2. 13.2.5.2 Using the TRNG
        3. 13.2.5.3 TRNG Events
          1. 13.2.5.3.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 13.3 TRNG Registers
  16. 14Temperature Sensor
  17. 15ADC
    1. 15.1 ADC Overview
    2. 15.2 ADC Operation
      1. 15.2.1  ADC Core
      2. 15.2.2  Voltage Reference Options
      3. 15.2.3  Generic Resolution Modes
      4. 15.2.4  Hardware Averaging
      5. 15.2.5  ADC Clocking
      6. 15.2.6  Common ADC Use Cases
      7. 15.2.7  Power Down Behavior
      8. 15.2.8  Sampling Trigger Sources and Sampling Modes
        1. 15.2.8.1 AUTO Sampling Mode
        2. 15.2.8.2 MANUAL Sampling Mode
      9. 15.2.9  Sampling Period
      10. 15.2.10 Conversion Modes
      11. 15.2.11 Data Format
      12. 15.2.12 Advanced Features
        1. 15.2.12.1 Window Comparator
        2. 15.2.12.2 DMA and FIFO Operation
        3. 15.2.12.3 Analog Peripheral Interconnection
      13. 15.2.13 Status Register
      14. 15.2.14 ADC Events
        1. 15.2.14.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 15.2.14.2 Generic Event Publisher (GEN_EVENT)
        3. 15.2.14.3 DMA Trigger Event Publisher (DMA_TRIG)
        4. 15.2.14.4 Generic Event Subscriber (FSUB_0)
    3. 15.3 ADC12 Registers
  18. 16COMP
    1. 16.1 Comparator Overview
    2. 16.2 Comparator Operation
      1. 16.2.1  Comparator Configuration
      2. 16.2.2  Comparator Channels Selection
      3. 16.2.3  Comparator Output
      4. 16.2.4  Output Filter
      5. 16.2.5  Sampled Output Mode
      6. 16.2.6  Blanking Mode
      7. 16.2.7  Reference Voltage Generator
      8. 16.2.8  Comparator Hysteresis
      9. 16.2.9  Input SHORT Switch
      10. 16.2.10 Interrupt and Events Support
        1. 16.2.10.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 16.2.10.2 Generic Event Publisher (GEN_EVENT)
        3. 16.2.10.3 Generic Event Subscribers
    3. 16.3 COMP0 Registers
  19. 17OPA
    1. 17.1 OPA Overview
    2. 17.2 OPA Operation
      1. 17.2.1 Analog Core
      2. 17.2.2 Power Up Behavior
      3. 17.2.3 Inputs
      4. 17.2.4 Output
      5. 17.2.5 Clock Requirements
      6. 17.2.6 Chopping
      7. 17.2.7 OPA Amplifier Modes
        1. 17.2.7.1 General-Purpose Mode
        2. 17.2.7.2 Buffer Mode
        3. 17.2.7.3 OPA PGA Mode
          1. 17.2.7.3.1 Inverting PGA Mode
          2. 17.2.7.3.2 Non-inverting PGA Mode
        4. 17.2.7.4 Difference Amplifier Mode
        5. 17.2.7.5 Cascade Amplifier Mode
      8. 17.2.8 OPA Configuration Selection
      9. 17.2.9 Burnout Current Source
    3. 17.3 OA Registers
  20. 18GPAMP
    1. 18.1 GPAMP Overview
    2. 18.2 GPAMP Operation
      1. 18.2.1 Analog Core
      2. 18.2.2 Power Up Behavior
      3. 18.2.3 Inputs
      4. 18.2.4 Output
      5. 18.2.5 GPAMP Amplifier Modes
        1. 18.2.5.1 General-Purpose Mode
        2. 18.2.5.2 ADC Buffer Mode
        3. 18.2.5.3 Unity Gain Mode
      6. 18.2.6 Chopping
    3. 18.3 GPAMP Registers
  21. 19VREF
    1. 19.1 VREF Overview
    2. 19.2 VREF Operation
      1. 19.2.1 Internal Reference Generation
      2. 19.2.2 External Reference Input
      3. 19.2.3 Analog Peripheral Interface
    3. 19.3 VREF Registers
  22. 20LCD
    1. 20.1 LCD Introduction
      1. 20.1.1 LCD Operating Principle
      2. 20.1.2 Static Mode
      3. 20.1.3 2-Mux Mode
      4. 20.1.4 3-Mux Mode
      5. 20.1.5 4-Mux Mode
      6. 20.1.6 6-Mux Mode
      7. 20.1.7 8-Mux Mode
      8. 20.1.8 Introduction
      9. 20.1.9 LCD Waveforms
    2. 20.2 LCD Clocking
    3. 20.3 Voltage Generation
      1. 20.3.1  Mode 0 - Voltage Generation from external reference and external resistor divider
      2. 20.3.2  Mode 1 - Voltage Generation from AVDD and external resistor divider
      3. 20.3.3  Mode 2 - Voltage Generation from external reference and internal resistor divider
      4. 20.3.4  Mode 3 - Voltage Generation From AVDD and Internal Resistor Ladder
      5. 20.3.5  Mode 4 - Voltage Generation from charge pump with external supply
      6. 20.3.6  Mode 5 - Voltage Generation From Charge Pump With AVDD
      7. 20.3.7  Mode 6 - Voltage Generation From Charge Pump With External Reference on R13
      8. 20.3.8  Mode 7 - Voltage Generation From Charge Pump With Internal Reference on R13
      9. 20.3.9  Charge pump
      10. 20.3.10 Internal Reference Generation
    4. 20.4 Analog Mux
      1. 20.4.1 Static Mode
      2. 20.4.2 Non-Static 1/3 bias mode
      3. 20.4.3 Non-Static 1/4 bias mode
      4. 20.4.4 Low power mode switch controls
    5. 20.5 LCD Memory and output drive
      1. 20.5.1 LCD Memory organization
        1. 20.5.1.1 Memory Organization in Mux-1 to Mux-4 Modes
        2. 20.5.1.2 Memory Organization in Mux-5 to Mux-8 Modes
        3. 20.5.1.3 Configuring memory
        4. 20.5.1.4 Accessing memory and output drive
        5. 20.5.1.5 Blinking Override
    6. 20.6 IO Muxing
    7. 20.7 Interrupt Generation
    8. 20.8 Power Domains and Power Modes
    9. 20.9 LCD Registers
  23. 21UART
    1. 21.1 UART Overview
      1. 21.1.1 Purpose of the Peripheral
      2. 21.1.2 Features
      3. 21.1.3 Functional Block Diagram
    2. 21.2 UART Operation
      1. 21.2.1 Clock Control
      2. 21.2.2 Signal Descriptions
      3. 21.2.3 General Architecture and Protocol
        1. 21.2.3.1  Transmit Receive Logic
        2. 21.2.3.2  Bit Sampling
        3. 21.2.3.3  Majority Voting Feature
        4. 21.2.3.4  Baud Rate Generation
        5. 21.2.3.5  Data Transmission
        6. 21.2.3.6  Error and Status
        7. 21.2.3.7  Local Interconnect Network (LIN) Support
          1. 21.2.3.7.1 LIN Responder Transmission Delay
        8. 21.2.3.8  Flow Control
        9. 21.2.3.9  Idle-Line Multiprocessor
        10. 21.2.3.10 9-Bit UART Mode
        11. 21.2.3.11 RS-485 Support
        12. 21.2.3.12 DALI Protocol
        13. 21.2.3.13 Manchester Encoding and Decoding
        14. 21.2.3.14 IrDA Encoding and Decoding
        15. 21.2.3.15 ISO7816 Smart Card Support
        16. 21.2.3.16 Address Detection
        17. 21.2.3.17 FIFO Operation
        18. 21.2.3.18 Loopback Operation
        19. 21.2.3.19 Glitch Suppression
      4. 21.2.4 Low Power Operation
      5. 21.2.5 Reset Considerations
      6. 21.2.6 Initialization
      7. 21.2.7 Interrupt and Events Support
        1. 21.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 21.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 21.2.8 Emulation Modes
    3. 21.3 UART Registers
  24. 22I2C
    1. 22.1 I2C Overview
      1. 22.1.1 Purpose of the Peripheral
      2. 22.1.2 Features
      3. 22.1.3 Functional Block Diagram
      4. 22.1.4 Environment and External Connections
    2. 22.2 I2C Operation
      1. 22.2.1 Clock Control
        1. 22.2.1.1 Clock Select and I2C Speed
        2. 22.2.1.2 Clock Startup
      2. 22.2.2 Signal Descriptions
      3. 22.2.3 General Architecture
        1. 22.2.3.1  I2C Bus Functional Overview
        2. 22.2.3.2  START and STOP Conditions
        3. 22.2.3.3  Data Format with 7-Bit Address
        4. 22.2.3.4  Acknowledge
        5. 22.2.3.5  Repeated Start
        6. 22.2.3.6  SCL Clock Low Timeout
        7. 22.2.3.7  Clock Stretching
        8. 22.2.3.8  Dual Address
        9. 22.2.3.9  Arbitration
        10. 22.2.3.10 Multiple Controller Mode
        11. 22.2.3.11 Glitch Suppression
        12. 22.2.3.12 FIFO operation
          1. 22.2.3.12.1 Flushing Stale Tx Data in Target Mode
        13. 22.2.3.13 Loopback mode
        14. 22.2.3.14 Burst Mode
        15. 22.2.3.15 DMA Operation
        16. 22.2.3.16 Low-Power Operation
      4. 22.2.4 Protocol Descriptions
        1. 22.2.4.1 I2C Controller Mode
          1. 22.2.4.1.1 Controller Configuration
          2. 22.2.4.1.2 Controller Mode Operation
          3. 22.2.4.1.3 Read On TX Empty
        2. 22.2.4.2 I2C Target Mode
          1. 22.2.4.2.1 Target Mode Operation
      5. 22.2.5 Reset Considerations
      6. 22.2.6 Initialization
      7. 22.2.7 Interrupt and Events Support
        1. 22.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 22.2.7.2 DMA Trigger Publisher (DMA_TRIG1, DMA_TRIG0)
      8. 22.2.8 Emulation Modes
    3. 22.3 I2C Registers
  25. 23SPI
    1. 23.1 SPI Overview
      1. 23.1.1 Purpose of the Peripheral
      2. 23.1.2 Features
      3. 23.1.3 Functional Block Diagram
      4. 23.1.4 External Connections and Signal Descriptions
    2. 23.2 SPI Operation
      1. 23.2.1 Clock Control
      2. 23.2.2 General Architecture
        1. 23.2.2.1 Chip Select and Command Handling
          1. 23.2.2.1.1 Chip Select Control
          2. 23.2.2.1.2 Command Data Control
        2. 23.2.2.2 Data Format
        3. 23.2.2.3 Delayed data sampling
        4. 23.2.2.4 Clock Generation
        5. 23.2.2.5 FIFO Operation
        6. 23.2.2.6 Loopback mode
        7. 23.2.2.7 DMA Operation
        8. 23.2.2.8 Repeat Transfer mode
        9. 23.2.2.9 Low Power Mode
      3. 23.2.3 Protocol Descriptions
        1. 23.2.3.1 Motorola SPI Frame Format
        2. 23.2.3.2 Texas Instruments Synchronous Serial Frame Format
      4. 23.2.4 Reset Considerations
      5. 23.2.5 Initialization
      6. 23.2.6 Interrupt and Events Support
        1. 23.2.6.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 23.2.6.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      7. 23.2.7 Emulation Modes
    3. 23.3 SPI Registers
  26. 24UNICOMM
    1. 24.1 Overview
      1. 24.1.1 Block Diagram
    2. 24.2 Unicomm Architecture
      1. 24.2.1 Serial Peripheral Group (SPG) Configurations
        1. 24.2.1.1 I2C Pairings
      2. 24.2.2 Enables & Resets
    3. 24.3 High-Level Initialization
    4. 24.4 UNICOMM/SPGSS Registers
      1. 24.4.1 UNICOMM Registers
        1. 24.4.1.1 UNICOMM Registers
      2. 24.4.2 SPG Registers
        1. 24.4.2.1 SPGSS Registers
  27. 25UNICOMM UART
    1. 25.1 UART Overview
      1. 25.1.1 Purpose of the Peripheral
      2. 25.1.2 Features
      3. 25.1.3 Functional Block Diagram
    2. 25.2 UART Operation
      1. 25.2.1 Clock Control
      2. 25.2.2 General Architecture and Protocol
        1. 25.2.2.1 Signal Descriptions
        2. 25.2.2.2 Transmit and Receive Logic
        3. 25.2.2.3 Bit Sampling
        4. 25.2.2.4 Baud Rate Generation
        5. 25.2.2.5 Data Transmission
        6. 25.2.2.6 Error and Status
        7. 25.2.2.7 DMA Operation
        8. 25.2.2.8 Internal Loopback Operation
      3. 25.2.3 Additional Protocol and Feature Support
        1. 25.2.3.1  Local Interconnect Network (LIN) Support
          1. 25.2.3.1.1 LIN Commander Transmit
          2. 25.2.3.1.2 LIN Responder Receive
          3. 25.2.3.1.3 LIN Responder Transmission Delay
        2. 25.2.3.2  Flow Control
        3. 25.2.3.3  RS485 Support
        4. 25.2.3.4  FIFO Operation
        5. 25.2.3.5  Idle-Line Multiprocessor
        6. 25.2.3.6  9-Bit UART Mode
        7. 25.2.3.7  DALI Protocol
        8. 25.2.3.8  Manchester Encoding and Decoding
        9. 25.2.3.9  IrDA Encoding and Decoding
        10. 25.2.3.10 ISO7816 Smart Card Support
        11. 25.2.3.11 Address Detection
        12. 25.2.3.12 Glitch Suppression
      4. 25.2.4 Low Power Operation
      5. 25.2.5 Reset Considerations
      6. 25.2.6 UART Initialization
      7. 25.2.7 Interrupt and Events Support
        1. 25.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 25.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 25.2.8 Emulation Modes
    3. 25.3 UNICOMMUART Registers
  28. 26UNICOMM-I2C
    1. 26.1 UNICOMM-I2C Overview
      1. 26.1.1 Purpose of the Peripheral
      2. 26.1.2 Features
      3. 26.1.3 Functional Block Diagram
      4. 26.1.4 Environment and External Connections
    2. 26.2 UNICOMM Common Infrastructure
    3. 26.3 Peripheral Functional Description
      1. 26.3.1 Clock Control
        1. 26.3.1.1 Clock Select and I2C Speed
        2. 26.3.1.2 Clock Startup
      2. 26.3.2 Signal Descriptions
      3. 26.3.3 General Architecture
        1. 26.3.3.1  I2C Bus Functional Overview
        2. 26.3.3.2  START and STOP Conditions
        3. 26.3.3.3  Dual Address
        4. 26.3.3.4  Address Format
          1. 26.3.3.4.1 Data Format with 7-Bit Address
          2. 26.3.3.4.2 Data Format with 10-Bit Address
        5. 26.3.3.5  Acknowledge
        6. 26.3.3.6  Repeated Start
        7. 26.3.3.7  Clock Stretching
        8. 26.3.3.8  Clock Low Timeout
        9. 26.3.3.9  Burst Mode
        10. 26.3.3.10 Arbitration
        11. 26.3.3.11 Multiple Controller Mode
        12. 26.3.3.12 Glitch Suppression
        13. 26.3.3.13 DMA Operation
        14. 26.3.3.14 FIFO Operation
          1. 26.3.3.14.1 FIFO Status Flags
          2. 26.3.3.14.2 FIFO Levels
          3. 26.3.3.14.3 Clearing FIFO Contents
        15. 26.3.3.15 Suspend Communication
        16. 26.3.3.16 Low Power Operation
        17. 26.3.3.17 SMBUS 3.0 Support
          1. 26.3.3.17.1 Quick Command
          2. 26.3.3.17.2 SMBUS Enhanced Acknowledge Control
          3. 26.3.3.17.3 Clock Low Timeout Detection
          4. 26.3.3.17.4 Clock High Timeout Detection
          5. 26.3.3.17.5 Cumulative Clock Low Extended Timeout
          6. 26.3.3.17.6 Packet Error Checking (PEC)
          7. 26.3.3.17.7 Host Notify Protocol
          8. 26.3.3.17.8 Alert Response Protocol
          9. 26.3.3.17.9 Address Resolution Protocol
      4. 26.3.4 Protocol Descriptions & Initialization
        1. 26.3.4.1 I2C Controller Mode
          1. 26.3.4.1.1 I2C Controller Initialization
          2. 26.3.4.1.2 I2C Controller Status
          3. 26.3.4.1.3 I2C Controller Receive Mode
          4. 26.3.4.1.4 I2C Controller Transmitter Mode
          5. 26.3.4.1.5 Controller Transaction Configurations
        2. 26.3.4.2 I2C Target Mode
          1. 26.3.4.2.1 I2C Target Initialization
          2. 26.3.4.2.2 I2C Target Status
          3. 26.3.4.2.3 I2C Target Receiver Mode
          4. 26.3.4.2.4 I2C Target Transmitter Mode
      5. 26.3.5 Reset Considerations
      6. 26.3.6 Initialization
      7. 26.3.7 Interrupt and Events Support
        1. 26.3.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 26.3.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 26.3.8 Emulation Modes
    4. 26.4 UNICOMM I2C Registers
      1. 26.4.1 UNICOMMI2CC Registers
      2. 26.4.2 UNICOMMI2CT Registers
  29. 27UNICOMM-SPI
    1. 27.1 UNICOMM-SPI Overview
      1. 27.1.1 Purpose of the Peripheral
      2. 27.1.2 Features
      3. 27.1.3 Functional Block Diagram
      4. 27.1.4 External Connections and Signal Descriptions
    2. 27.2 SPI Operation
      1. 27.2.1  Clock Frequency Support
        1. 27.2.1.1 SPI Clock Generation
      2. 27.2.2  General Architecture
        1. 27.2.2.1 Chip Select and Command Handling
          1. 27.2.2.1.1 Chip Select Control
        2. 27.2.2.2 Command Data Control
        3. 27.2.2.3 Data Format
        4. 27.2.2.4 Delayed data sampling
        5. 27.2.2.5 DMA Operation
      3. 27.2.3  FIFO Operation
        1. 27.2.3.1 FIFO Size
        2. 27.2.3.2 FIFO Status bits
          1. 27.2.3.2.1 RIS.RX based on FIFO threshold settings
          2. 27.2.3.2.2 RIS.TX based on FIFO threshold settings
        3. 27.2.3.3 Clearing FIFO contents
        4. 27.2.3.4 Hardware monitors empty, full and overflow conditions
      4. 27.2.4  Suspend communication
        1. 27.2.4.1 SPI IDLE State Requirements
      5. 27.2.5  Internal Loopback Operation
      6. 27.2.6  Repeat Transfer mode
      7. 27.2.7  Receive Timeout
      8. 27.2.8  Line Timeout
      9. 27.2.9  Protocol Descriptions
        1. 27.2.9.1 Motorola SPI Frame Format
        2. 27.2.9.2 Texas Instruments Synchronous Serial Frame Format
      10. 27.2.10 Status Flags
      11. 27.2.11 Module configuration
      12. 27.2.12 Reset Considerations
      13. 27.2.13 Initialization
      14. 27.2.14 Interrupt and Events Support
        1. 27.2.14.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 27.2.14.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      15. 27.2.15 Emulation Modes
        1. 27.2.15.1 Graceful Halt
    3. 27.3 UNICOMMSPI Registers
  30. 28Timers (TIMx)
    1. 28.1 TIMx Overview
      1. 28.1.1 TIMG Overview
        1. 28.1.1.1 TIMG Features
        2. 28.1.1.2 Functional Block Diagram
      2. 28.1.2 TIMA Overview
        1. 28.1.2.1 TIMA Features
        2. 28.1.2.2 Functional Block Diagram
      3. 28.1.3 TIMx Instance Configuration
    2. 28.2 TIMx Operation
      1. 28.2.1  Timer Counter
        1. 28.2.1.1 Clock Source Select and Prescaler
          1. 28.2.1.1.1 Internal Clock and Prescaler
          2. 28.2.1.1.2 External Signal Trigger
        2. 28.2.1.2 Repeat Counter (TIMA only)
      2. 28.2.2  Counting Mode Control
        1. 28.2.2.1 One-shot and Periodic Modes
        2. 28.2.2.2 Down Counting Mode
        3. 28.2.2.3 Up/Down Counting Mode
        4. 28.2.2.4 Up Counting Mode
        5. 28.2.2.5 Phase Load (TIMA only)
      3. 28.2.3  Capture/Compare Module
        1. 28.2.3.1 Capture Mode
          1. 28.2.3.1.1 Input Selection, Counter Conditions, and Inversion
            1. 28.2.3.1.1.1 CCP Input Edge Synchronization
            2. 28.2.3.1.1.2 CCP Input Pulse Conditions
            3. 28.2.3.1.1.3 Counter Control Operation
            4. 28.2.3.1.1.4 CCP Input Filtering
            5. 28.2.3.1.1.5 Input Selection
          2. 28.2.3.1.2 Use Cases
            1. 28.2.3.1.2.1 Edge Time Capture
            2. 28.2.3.1.2.2 Period Capture
            3. 28.2.3.1.2.3 Pulse Width Capture
            4. 28.2.3.1.2.4 Combined Pulse Width and Period Time
          3. 28.2.3.1.3 QEI Mode (TIMG with QEI support only)
            1. 28.2.3.1.3.1 QEI With 2-Signal
            2. 28.2.3.1.3.2 QEI With Index Input
            3. 28.2.3.1.3.3 QEI Error Detection
          4. 28.2.3.1.4 Hall Input Mode (TIMG with QEI support only)
        2. 28.2.3.2 Compare Mode
          1. 28.2.3.2.1 Edge Count
      4. 28.2.4  Shadow Load and Shadow Compare
        1. 28.2.4.1 Shadow Load (TIMG4-7, TIMA only)
        2. 28.2.4.2 Shadow Compare (TIMG4-7, TIMG12-13, TIMA only)
      5. 28.2.5  Output Generator
        1. 28.2.5.1 Configuration
        2. 28.2.5.2 Use Cases
          1. 28.2.5.2.1 Edge-Aligned PWM
          2. 28.2.5.2.2 Center-Aligned PWM
          3. 28.2.5.2.3 Asymmetric PWM (TIMA only)
          4. 28.2.5.2.4 Complementary PWM With Deadband Insertion (TIMA only)
        3. 28.2.5.3 Forced Output
      6. 28.2.6  Fault Handler (TIMA only)
        1. 28.2.6.1 Fault Input Conditioning
        2. 28.2.6.2 Fault Input Sources
        3. 28.2.6.3 Counter Behavior With Fault Conditions
        4. 28.2.6.4 Output Behavior With Fault Conditions
      7. 28.2.7  Synchronization With Cross Trigger
        1. 28.2.7.1 Main Timer Cross Trigger Configuration
        2. 28.2.7.2 Secondary Timer Cross Trigger Configuration
      8. 28.2.8  Low Power Operation
      9. 28.2.9  Interrupt and Event Support
        1. 28.2.9.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 28.2.9.2 Generic Event Publisher and Subscriber (GEN_EVENT0 and GEN_EVENT1)
        3. 28.2.9.3 Generic Subscriber Event Example (COMP to TIMx)
      10. 28.2.10 Debug Handler (TIMA Only)
    3. 28.3 TIMx Registers
  31. 29TIMB
    1. 29.1 TIMB Overview
      1. 29.1.1 Features
      2. 29.1.2 TIMB Block Diagram
    2. 29.2 TIMB Operation
      1. 29.2.1 Counter Block Operation
        1. 29.2.1.1 Clock Source Selection
        2. 29.2.1.2 Counter Reset Generation
        3. 29.2.1.3 Event Based Enable and Disable
        4. 29.2.1.4 Event Generation
        5. 29.2.1.5 Interrupt Generation
        6. 29.2.1.6 Counter Behavior on a Debug Halt
        7. 29.2.1.7 Hardware Locking of Configuration Registers
    3. 29.3 TIMB Example Applications
      1. 29.3.1 Periodic Interrupt Generation
      2. 29.3.2 Counter Chaining
      3. 29.3.3 Event Counting
      4. 29.3.4 Event Duration Measurement
      5. 29.3.5 Event Sequence Checking
      6. 29.3.6 PWM Generation
    4. 29.4 TIMB Registers
  32. 30Low Frequency Subsystem (LFSS)
    1. 30.1  Overview
    2. 30.2  Clock System
    3. 30.3  LFSS Reset Using VBAT
    4. 30.4  Power Domains and Supply Detection
      1. 30.4.1 Startup When VBAT Powers on First
      2. 30.4.2 Startup when VDD powers on first
      3. 30.4.3 Behavior When VDD is Lost
      4. 30.4.4 Behavior when VBAT is lost
      5. 30.4.5 Behavior when the device goes into SHUTDOWN mode
      6. 30.4.6 Supercapacitor Charging Circuit
    5. 30.5  Real Time Counter (RTC_x)
    6. 30.6  Independent Watchdog Timer (IWDT)
    7. 30.7  Tamper Input and Output
      1. 30.7.1 IOMUX Mode
      2. 30.7.2 Tamper Mode
        1. 30.7.2.1 Tamper Event Detection
        2. 30.7.2.2 Timestamp Event Output
        3. 30.7.2.3 Heartbeat Generator
        4. 30.7.2.4 RTC Clock Output
    8. 30.8  Scratchpad Memory
    9. 30.9  Lock Function of RTC, TIO, and IWDT
    10. 30.10 LFSS Registers
  33. 31Low Frequency Subsystem (LFSS_B)
    1. 31.1 Overview
    2. 31.2 Clock System
    3. 31.3 LFSS Reset
    4. 31.4 Real Time Counter (RTC_x)
    5. 31.5 Independent Watchdog Timer (IWDT)
    6. 31.6 Lock Function of RTC and IWDT
    7. 31.7 LFSS Registers
  34. 32RTC
    1. 32.1 Overview
      1. 32.1.1 RTC Instances
    2. 32.2 Basic Operation
    3. 32.3 Configuration
      1. 32.3.1  Clocking
      2. 32.3.2  Reading and Writing to RTC Peripheral Registers
      3. 32.3.3  Binary vs. BCD
      4. 32.3.4  Leap Year Handling
      5. 32.3.5  Calendar Alarm Configuration
      6. 32.3.6  Interval Alarm Configuration
      7. 32.3.7  Periodic Alarm Configuration
      8. 32.3.8  Calibration
        1. 32.3.8.1 Crystal Offset Error
          1. 32.3.8.1.1 Offset Error Correction Mechanism
        2. 32.3.8.2 Crystal Temperature Error
          1. 32.3.8.2.1 Temperature Drift Correction Mechanism
      9. 32.3.9  RTC Prescaler Extension
      10. 32.3.10 RTC Timestamp Capture
      11. 32.3.11 RTC Events
        1. 32.3.11.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 32.3.11.2 Generic Event Publisher (GEN_EVENT)
    4. 32.4 RTC Registers
  35. 33IWDT
    1. 33.1 920
    2. 33.2 IWDT Clock Configuration
    3. 33.3 IWDT Period Selection
    4. 33.4 Debug Behavior of the IWDT
    5. 33.5 IWDT Registers
  36. 34Window Watchdog Timer (WWDT)
    1. 34.1 WWDT Overview
      1. 34.1.1 Watchdog Mode
      2. 34.1.2 Interval Timer Mode
    2. 34.2 WWDT Operation
      1. 34.2.1 Mode Selection
      2. 34.2.2 Clock Configuration
      3. 34.2.3 Low-Power Mode Behavior
      4. 34.2.4 Debug Behavior
      5. 34.2.5 WWDT Events
        1. 34.2.5.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 34.3 WWDT Registers
  37. 35Debug
    1. 35.1 DEBUGSS Overview
      1. 35.1.1 Debug Interconnect
      2. 35.1.2 Physical Interface
      3. 35.1.3 Debug Access Ports
    2. 35.2 DEBUGSS Operation
      1. 35.2.1 Debug Features
        1. 35.2.1.1 Processor Debug
          1. 35.2.1.1.1 Breakpoint Unit (BPU)
          2. 35.2.1.1.2 Data Watchpoint and Trace Unit (DWT)
        2. 35.2.1.2 Peripheral Debug
        3. 35.2.1.3 EnergyTrace Technology
      2. 35.2.2 Behavior in Low Power Modes
      3. 35.2.3 Restricting Debug Access
      4. 35.2.4 Mailbox (DSSM)
        1. 35.2.4.1 DSSM Events
          1. 35.2.4.1.1 CPU Interrupt Event (CPU_INT)
        2. 35.2.4.2 Reference
    3. 35.3 DEBUGSS Registers
  38. 36Revision History

6.6 FLASHCTL Registers

Table 6-12 lists the memory-mapped registers for the FLASHCTL registers. All register offset addresses not listed in Table 6-12 should be considered as reserved locations and the register contents should not be modified.

Table 6-12 FLASHCTL Registers
OffsetAcronymRegister NameGroupSection
1020hIIDXInterrupt Index RegisterGo
1028hIMASKInterrupt Mask RegisterGo
1030hRISRaw Interrupt Status RegisterGo
1038hMISMasked Interrupt Status RegisterGo
1040hISETInterrupt Set RegisterGo
1048hICLRInterrupt Clear RegisterGo
10E0hEVT_MODEEvent ModeGo
10FChDESCHardware Version Description RegisterGo
1100hCMDEXECCommand Execute RegisterGo
1104hCMDTYPECommand Type RegisterGo
1108hCMDCTLCommand Control RegisterGo
1120hCMDADDRCommand Address RegisterGo
1124hCMDBYTENCommand Program Byte Enable RegisterGo
112ChCMDDATAINDEXCommand Data Index RegisterGo
1130hCMDDATA0Command Data Register 0Go
1134hCMDDATA1Command Data Register 1Go
1138hCMDDATA2Command Data Register 2Go
113ChCMDDATA3Command Data Register Bits 127:96Go
1140hCMDDATA4Command Data Register 4Go
1144hCMDDATA5Command Data Register 5Go
1148hCMDDATA6Command Data Register 6Go
114ChCMDDATA7Command Data Register 7Go
1150hCMDDATA8Command Data Register 8Go
1154hCMDDATA9Command Data Register 9Go
1158hCMDDATA10Command Data Register 10Go
115ChCMDDATA11Command Data Register 11Go
1160hCMDDATA12Command Data Register 12Go
1164hCMDDATA13Command Data Register 13Go
1168hCMDDATA14Command Data Register 14Go
116ChCMDDATA15Command Data Register 15Go
1170hCMDDATA16Command Data Register 16Go
1174hCMDDATA17Command Data Register 17Go
1178hCMDDATA18Command Data Register 18Go
117ChCMDDATA19Command Data Register 19Go
1180hCMDDATA20Command Data Register 20Go
1184hCMDDATA21Command Data Register 21Go
1188hCMDDATA22Command Data Register 22Go
118ChCMDDATA23Command Data Register 23Go
1190hCMDDATA24Command Data Register 24Go
1194hCMDDATA25Command Data Register 25Go
1198hCMDDATA26Command Data Register 26Go
119ChCMDDATA27Command Data Register 27Go
11A0hCMDDATA28Command Data Register 28Go
11A4hCMDDATA29Command Data Register 29Go
11A8hCMDDATA30Command Data Register 30Go
11AChCMDDATA31Command Data Register 31Go
11B0hCMDDATAECC0Command Data Register ECC 0Go
11B4hCMDDATAECC1Command Data Register ECC 1Go
11B8hCMDDATAECC2Command Data Register ECC 2Go
11BChCMDDATAECC3Command Data Register ECC 3Go
11C0hCMDDATAECC4Command Data Register ECC 4Go
11C4hCMDDATAECC5Command Data Register ECC 5Go
11C8hCMDDATAECC6Command Data Register ECC 6Go
11CChCMDDATAECC7Command Data Register ECC 7Go
11D0hCMDWEPROTACommand Write Erase Protect A RegisterGo
11D4hCMDWEPROTBCommand Write Erase Protect B RegisterGo
11D8hCMDWEPROTCCommand Write Erase Protect C RegisterGo
1210hCMDWEPROTNMCommand Write Erase Protect Non-Main RegisterGo
1214hCMDWEPROTTRCommand Write Erase Protect Trim RegisterGo
1218hCMDWEPROTENCommand Write Erase Protect Engr RegisterGo
13B0hCFGCMDCommand Configuration RegisterGo
13B4hCFGPCNTPulse Counter Configuration RegisterGo
13D0hSTATCMDCommand Status RegisterGo
13D4hSTATADDRAddress Status RegisterGo
13D8hSTATPCNTPulse Count Status RegisterGo
13DChSTATMODEMode Status RegisterGo
13F0hGBLINFO0Global Information Register 0Go
13F4hGBLINFO1Global Information Register 1Go
13F8hGBLINFO2Global Information Register 2Go
1400hBANK0INFO0Bank Information Register 0 for Bank 0Go
1404hBANK0INFO1Bank Information Register 1 for Bank 0Go
1410hBANK1INFO0Bank Information Register 0 for Bank 1Go
1414hBANK1INFO1Bank Information Register 1 for Bank 1Go
1420hBANK2INFO0Bank Information Register 0 for Bank 2Go
1424hBANK2INFO1Bank Information Register 1 for Bank 2Go
1430hBANK3INFO0Bank Information Register 0 for Bank 3Go
1434hBANK3INFO1Bank Information Register 1 for Bank 3Go
1440hBANK4INFO0Bank Information Register 0 for Bank 4Go
1444hBANK4INFO1Bank Information Register 1 for Bank 4Go

Complex bit access types are encoded to fit into small table cells. Table 6-13 shows the codes that are used for access types in this section.

Table 6-13 FLASHCTL Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

6.6.1 IIDX (Offset = 1020h) [Reset = 00000000h]

IIDX is shown in Figure 6-4 and described in Table 6-14.

Return to the Summary Table.

Interrupt Index Register:
The IIDX register provides the highest priority enabled interrupt index.

PSD compliant register.
Note that it is not recommended to use this register if the system clock is
running at a slower clock frequency than the flash wrapper clock. If this is the
case, then reading this register may fail to update the RIS register correctly.
The MIS register should be read directly, and a write to ICLR should be used to
clear interrupts when this clock relationship is present.

Figure 6-4 IIDX
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDSTAT
R-0hR-0h
Table 6-14 IIDX Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0STATR0hIndicates which interrupt has fired. 0x0 means no event pending. The priority order is fixed. On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flags in the RIS and MIS are cleared as well. After a read from the CPU (not from the debug interface), the register must be updated with the next highest priority interrupt.
  • 0h (R/W) = No Interrupt Pending
  • 1h (R/W) = DONE Interrupt Pending

6.6.2 IMASK (Offset = 1028h) [Reset = 00000000h]

IMASK is shown in Figure 6-5 and described in Table 6-15.

Return to the Summary Table.

Interrupt Mask Register: The IMASK register holds the current interrupt mask settings. Masked interrupts are read in the MIS register. PSD compliant register.

Figure 6-5 IMASK
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDDONE
R-0hR/W-0h
Table 6-15 IMASK Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0DONER/W0hInterrupt mask for DONE: 0: Interrupt is disabled in MIS register 1: Interrupt is enabled in MIS register
  • 0h (R/W) = Interrupt is masked out
  • 1h (R/W) = Interrupt will request an interrupt service routine and corresponding bit in MIS will be set

6.6.3 RIS (Offset = 1030h) [Reset = 00000000h]

RIS is shown in Figure 6-6 and described in Table 6-16.

Return to the Summary Table.

Raw Interrupt Status Register: The RIS register reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing a 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled. A flag can be set by software by writing a 1 to the ISET register. Reading the IIDX register will also clear the corresponding bit in RIS. PSD compliant register.

Figure 6-6 RIS
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDDONE
R-0hR-0h
Table 6-16 RIS Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0DONER0hFlash wrapper operation completed.
This interrupt bit is set by firmware or the corresponding bit in the ISET register.
It is cleared by the corresponding bit in in the ICLR register or reading the IIDX register when this interrupt is the highest priority.
  • 0h (R/W) = Interrupt did not occur
  • 1h (R/W) = Interrupt occurred

6.6.4 MIS (Offset = 1038h) [Reset = 00000000h]

MIS is shown in Figure 6-7 and described in Table 6-17.

Return to the Summary Table.

Masked Interrupt Status Register: The MIS register is a bit-wise AND of the contents of the IMASK and RIS registers. This is kept mainly for ARM compatibility, and has limited use since the highest priority interrupt index is returned via the IIDX register. PSD compliant register.

Figure 6-7 MIS
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDDONE
R-0hR-0h
Table 6-17 MIS Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0DONER0hFlash wrapper operation completed.
This masked interrupt bit reflects the bitwise AND of the corresponding RIS and IMASK bits.
  • 0h (R/W) = Masked interrupt did not occur
  • 1h (R/W) = Masked interrupt occurred

6.6.5 ISET (Offset = 1040h) [Reset = 00000000h]

ISET is shown in Figure 6-8 and described in Table 6-18.

Return to the Summary Table.

Interrupt Set Register: The ISET register allows software to write a 1 to set corresponding interrupt. Safety: This meets a safety requirement to allow software diagnostics to trigger interrupts. PSD compliant register.

Figure 6-8 ISET
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDDONE
R-0hW-0h
Table 6-18 ISET Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0DONEW0h0: No effect 1: Set the DONE interrupt in the RIS register
  • 0h (R/W) = Writing a 0 has no effect
  • 1h (R/W) = Set RIS bit

6.6.6 ICLR (Offset = 1048h) [Reset = 00000000h]

ICLR is shown in Figure 6-9 and described in Table 6-19.

Return to the Summary Table.

Interrupt Clear Register. The ICLR register allows allows software to write a 1 to clear corresponding interrupt. PSD compliant register.

Figure 6-9 ICLR
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDDONE
R-0hW-0h
Table 6-19 ICLR Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0DONEW0h0: No effect 1: Clear the DONE interrupt in the RIS register
  • 0h (R/W) = Writing a 0 has no effect
  • 1h (R/W) = Clear RIS bit

6.6.7 EVT_MODE (Offset = 10E0h) [Reset = 00000000h]

EVT_MODE is shown in Figure 6-10 and described in Table 6-20.

Return to the Summary Table.

Event mode register. It is used to select whether each line is disabled, in software mode (software clears the RIS) or in hardware mode (hardware clears the RIS).

Figure 6-10 EVT_MODE
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDINT0_CFG
R-0hR-0h
Table 6-20 EVT_MODE Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1-0INT0_CFGR1hEvent line mode select for peripheral event
  • 0h = The interrupt or event line is disabled.
  • 1h = The interrupt or event line is in software mode. Software must clear the RIS.
  • 2h = The interrupt or event line is in hardware mode. Hardware should clear the RIS.

6.6.8 DESC (Offset = 10FCh) [Reset = 00000000h]

DESC is shown in Figure 6-11 and described in Table 6-21.

Return to the Summary Table.

Hardware Version Description Register:
This register identifies the flash wrapper hardware version and feature set used.

Figure 6-11 DESC
31302928272625242322212019181716
MODULEID
R-0h
1514131211109876543210
FEATUREVERINSTNUMMAJREVMINREV
R-0hR-0hR-0hR-0h
Table 6-21 DESC Field Descriptions
BitFieldTypeResetDescription
31-16MODULEIDR0hModule ID
  • 0h = Smallest value
  • FFFFh = Highest possible value
15-12FEATUREVERR0hFeature set
  • 0h = Minimum Value
  • Fh = Maximum Value
11-8INSTNUMR0hInstance number
  • 0h = Smallest value
  • Fh = Highest possible value
7-4MAJREVR0hMajor Revision
  • 0h = Smallest value
  • Fh = Highest possible value
3-0MINREVR0hMinor Revision
  • 0h = Smallest value
  • Fh = Highest possible value

6.6.9 CMDEXEC (Offset = 1100h) [Reset = 00000000h]

CMDEXEC is shown in Figure 6-12 and described in Table 6-22.

Return to the Summary Table.

Command Execute Register:
Initiates execution of the command specified in the CMDTYPE register.
This register is blocked for writes after being written to 1 and prior to
STATCMD.DONE being set by the flash wrapper hardware.
flash wrapper hardware clears this register after the processing of the command
has completed.

Figure 6-12 CMDEXEC
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDVAL
R-0hR/W-0h
Table 6-22 CMDEXEC Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0hReserved
0VALR/W0hCommand Execute value Initiates execution of the command specified in the CMDTYPE register.
  • 0h (R/W) = Command will not execute or is not executing in flash wrapper
  • 1h (R/W) = Command will execute or is executing in flash wrapper

6.6.10 CMDTYPE (Offset = 1104h) [Reset = 00000000h]

CMDTYPE is shown in Figure 6-13 and described in Table 6-23.

Return to the Summary Table.

Command Type Register
This register specifies the type of command to be executed by the flash wrapper
hardware.
This register is blocked for writes after CMDEXEC is written to a 1 and
prior to STATCMD.DONE being set by the hardware to indicate that
command execution has completed.

Figure 6-13 CMDTYPE
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDSIZERESERVEDCOMMAND
R-0hR/W-0hR-0hR/W-0h
Table 6-23 CMDTYPE Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6-4SIZER/W0hCommand size
  • 0h (R/W) = Operate on 1 flash word
  • 1h (R/W) = Operate on 2 flash words
  • 2h (R/W) = Operate on 4 flash words
  • 3h (R/W) = Operate on 8 flash words
  • 4h (R/W) = Operate on a flash sector
  • 5h (R/W) = Operate on an entire flash bank
3RESERVEDR0hReserved
2-0COMMANDR/W0hCommand type
  • 0h (R/W) = No Operation
  • 1h (R/W) = Program
  • 2h (R/W) = Erase
  • 3h (R/W) = Read Verify - Perform a standalone read verify operation.
  • 4h (R/W) = Mode Change - Perform a mode change only, no other operation.
  • 5h (R/W) = Clear Status - Clear status bits in FW_SMSTAT only.
  • 6h (R/W) = Blank Verify - Check whether a flash word is in the erased state. This command may only be used with CMDTYPE.SIZE = ONEWORD

6.6.11 CMDCTL (Offset = 1108h) [Reset = 00000000h]

CMDCTL is shown in Figure 6-14 and described in Table 6-24.

Return to the Summary Table.

Command Control Register This register configures specific capabilities of the state machine for related to the execution of a command. This register is blocked for writes after CMDEXEC is written to a 1 and prior to STATCMD.DONE being set by the hardware to indicate that command execution has completed.

Figure 6-14 CMDCTL
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDDATAVERENSSERASEDISERASEMASKDISPROGMASKDISECCGENOVRADDRXLATEOVR
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
POSTVERENPREVERENRESERVEDREGIONSELRESERVED
R/W-0hR/W-0hR-0hR/W-0hR-0h
76543210
RESERVEDBANKSELMODESEL
R-0hR/W-0hR/W-0h
Table 6-24 CMDCTL Field Descriptions
BitFieldTypeResetDescription
31-22RESERVEDR0hReserved
21DATAVERENR/W0hEnable invalid data verify. This checks for 0->1 transitions in the memory when a program operation is initiated. If such a transition is found, the program will fail with an error without doing any programming.
  • 0h (R/W) = Disable
  • 1h (R/W) = Enable
20SSERASEDISR/W0hDisable Stair-Step Erase. If set, the default VHV trim voltage setting will be used for all erase pulses. By default, this bit is reset, meaning that the VHV voltage will be stepped during successive erase pulses. The step count, step voltage, begin and end voltages are all hard-wired.
  • 0h (R/W) = Enable
  • 1h (R/W) = Disable
19ERASEMASKDISR/W0hDisable use of erase mask for erase Bit masking will not be used during erase verify. If any sectors fail the verify either before (prever) or after (postver) the operation, then all specified flash sectors will receive subsequent erase pulse.
  • 0h (R/W) = Enable
  • 1h (R/W) = Disable
18PROGMASKDISR/W0hDisable use of program mask for programming. Bit masking will not be used during program verify. If any bits fail the verify either before (prever) or after (postver) the operation, then all specified flash entries will receive subsequent program pulse.
  • 0h (R/W) = Enable
  • 1h (R/W) = Disable
17ECCGENOVRR/W0hOverride hardware generation of ECC data for program. Use data written to CMDDATAECC*.
  • 0h (R/W) = Do not override
  • 1h (R/W) = Override
16ADDRXLATEOVRR/W0hOverride hardware address translation of address in CMDADDR from a system address to a bank address and bank ID. Use data written to CMDADDR directly as the bank address. Use the value written to CMDCTL.BANKSEL directly as the bank ID. Use the value written to CMDCTL.REGIONSEL directly as the region ID.
  • 0h (R/W) = Do not override
  • 1h (R/W) = Override
15POSTVERENR/W1hEnable verify after program or erase
  • 0h (R/W) = Disable
  • 1h (R/W) = Enable
14PREVERENR/W1hEnable verify before program or erase. For program, bits already programmed to the requested value will be masked. For erase, sectors already erased will be masked.
  • 0h (R/W) = Disable
  • 1h (R/W) = Enable
13RESERVEDR0hReserved
12-9REGIONSELR/W0hBank Region A specific region ID can be written to this field to indicate to which region an operation should be applied if CMDCTL.ADDRXLATEOVR is set.
  • 1h (R/W) = Main Region
  • 2h (R/W) = Non-Main Region
  • 4h (R/W) = Trim Region
  • 8h (R/W) = Engr Region
8-5RESERVEDR0h
4BANKSELR/W0hBank Select A specific Bank ID can be written to this field to indicate to which bank an operation should be applied if CMDCTL.ADDRXLATEOVR is set.
  • 1h (R/W) = Bank 0
  • 2h (R/W) = Bank 1
  • 4h (R/W) = Bank 2
  • 8h (R/W) = Bank 3
  • 10h (R/W) = Bank 4
3-0MODESELR/W0hMode This field is only used for the Mode Change command type. Otherwise, bank and pump modes are set automaticlly via the NW hardware.
  • 0h = Read Mode
  • 2h = Read Margin 0 Mode
  • 4h = Read Margin 1 Mode
  • 6h = Read Margin 0B Mode
  • 7h = Read Margin 1B Mode
  • 9h = Program Verify Mode
  • Ah = Program Single Word
  • Bh = Erase Verify Mode
  • Ch = Erase Sector
  • Eh = Program Multiple Word
  • Fh = Erase Bank

6.6.12 CMDADDR (Offset = 1120h) [Reset = 00000000h]

CMDADDR is shown in Figure 6-15 and described in Table 6-25.

Return to the Summary Table.

Command Address Register:
This register forms the target address of a command. The use cases are as
follows:
1) For single-word program, this address indicates the flash bank word to be
programmed.
2) For multi-word program, this address indicates the first flash bank address
for the program. The address will be incremented for further words.
3) For sector erase, this address indicates the sector to be erased.
4) For bank erase, the address indicates the bank to be erased.
5) For read verify, the address indications follow program/erase listed above.
Note the address written to this register will be submitted for translation to the
flash wrapper address translation interface, and the translated address
will be used to access the bank. However, if the
CMDCTL.ADDRXLATEOVR bit is set, then the address written to this register will
be used directly as the bank address.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.

Figure 6-15 CMDADDR
313029282726252423222120191817161514131211109876543210
VAL
R/W-0h
Table 6-25 CMDADDR Field Descriptions
BitFieldTypeResetDescription
31-0VALR/W0hAddress value
  • 0h = Minimum value of [VAL]
  • FFFFFFFFh = Maximum value of [VAL]

6.6.13 CMDBYTEN (Offset = 1124h) [Reset = 00000000h]

CMDBYTEN is shown in Figure 6-16 and described in Table 6-26.

Return to the Summary Table.

Command Program Byte Enable Register:
This register forms a per-byte enable for programming data. For data bytes to
be programmed, a 1 must be written to the corresponding bit in this register.
Normally, all bits are written to 1, allowing program of full flash words.
However, leaving some bits 0 allows programming of 8-bit, 16-bit, 32-bit
or 64-bit portions of a flash word.
In addtion, the read verify command will ignore data bytes read from the flash
in its comparison if the corresponding CMDBYTEN bit is 0.
ECC data bytes are protected by the 1-2 MSB bits in this register, depending on
the presence of ECC and the flash word data width.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is written to all 0 after the completion of all flash wrapper commands.

Figure 6-16 CMDBYTEN
313029282726252423222120191817161514131211109876543210
RESERVEDRESERVEDVAL
R-0hR-0hR/W-0h
Table 6-26 CMDBYTEN Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0hReserved
17-8RESERVEDR0h
7-0VALR/W0hCommand Byte Enable value. A 1-bit per flash word byte value is placed in this register.
  • 0h = Minimum value of [VAL]
  • 0003FFFFh = Maximum value of [VAL]

6.6.14 CMDDATAINDEX (Offset = 112Ch) [Reset = 00000000h]

CMDDATAINDEX is shown in Figure 6-17 and described in Table 6-27.

Return to the Summary Table.

Command Program Data Index Register:
When multiple data registers are available for multi-word program, this register
can be written with an index which points to one of the data registers. When
a write to CMDDATA* is done, the data will be written to the physical
data register indexed by the value in this register.
Up to 8 data registers can be present, so this register can be written with 0x0
to 0x7. If less than 8 data registers are present, successive MSB bits of this
register are ignored when indexing the CMDDATA* registers.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.

Figure 6-17 CMDDATAINDEX
313029282726252423222120191817161514131211109876543210
RESERVEDVAL
R-0hR/W-0h
Table 6-27 CMDDATAINDEX Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0hReserved
2-0VALR/W0hData register index
  • 0h = Minimum value of [VAL]
  • 7h = Maximum value of [VAL]

6.6.15 CMDDATA0 (Offset = 1130h) [Reset = 00000000h]

CMDDATA0 is shown in Figure 6-18 and described in Table 6-28.

Return to the Summary Table.

Command Data Register 0
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 31:0 of flash word data register 0.
For DATAWIDTH == 64: This register represents bits 31:0 of flash word data register 0.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 6-18 CMDDATA0
313029282726252423222120191817161514131211109876543210
VAL
R/W-0h
Table 6-28 CMDDATA0 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
  • 0h = Minimum value of [VAL]
  • FFFFFFFFh = Maximum value of [VAL]

6.6.16 CMDDATA1 (Offset = 1134h) [Reset = 00000000h]

CMDDATA1 is shown in Figure 6-19 and described in Table 6-29.

Return to the Summary Table.

Command Data Register 1
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 63:32 of flash word data register 0.
For DATAWIDTH == 64: This register represents bits 63:32 of flash word data register 0.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to CMDSTAT.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 6-19 CMDDATA1
313029282726252423222120191817161514131211109876543210
VAL
R/W-0h
Table 6-29 CMDDATA1 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
  • 0h = Minimum value of [VAL]
  • FFFFFFFFh = Maximum value of [VAL]

6.6.17 CMDDATA2 (Offset = 1138h) [Reset = 00000000h]

CMDDATA2 is shown in Figure 6-20 and described in Table 6-30.

Return to the Summary Table.

Command Data Register 2
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 95:64 of flash word data register 0.
For DATAWIDTH == 64: This register represents bits 31:0 of flash word data register 1.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 6-20 CMDDATA2
313029282726252423222120191817161514131211109876543210
VAL
R/W-0h
Table 6-30 CMDDATA2 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
  • 0h = Minimum value of [VAL]
  • FFFFFFFFh = Maximum value of [VAL]

6.6.18 CMDDATA3 (Offset = 113Ch) [Reset = 00000000h]

CMDDATA3 is shown in Figure 6-21 and described in Table 6-31.

Return to the Summary Table.

Command Data Register 3
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 127:96 of flash word data register 0.
For DATAWIDTH == 64: This register represents bits 63:32 of flash word data register 1.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 6-21 CMDDATA3
313029282726252423222120191817161514131211109876543210
VAL
R/W-0h
Table 6-31 CMDDATA3 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
  • 0h = Minimum value of [VAL]
  • FFFFFFFFh = Maximum value of [VAL]

6.6.19 CMDDATA4 (Offset = 1140h) [Reset = 00000000h]

CMDDATA4 is shown in Figure 6-22 and described in Table 6-32.

Return to the Summary Table.

Command Data Register 4
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 31:0 of flash word data register 1.
For DATAWIDTH == 64: This register represents bits 31:0 of flash word data register 2.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 6-22 CMDDATA4
313029282726252423222120191817161514131211109876543210
VAL
R/W-0h
Table 6-32 CMDDATA4 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field. T
  • 0h = Minimum value of [VAL]
  • FFFFFFFFh = Maximum value of [VAL]

6.6.20 CMDDATA5 (Offset = 1144h) [Reset = 00000000h]

CMDDATA5 is shown in Figure 6-23 and described in Table 6-33.

Return to the Summary Table.

Command Data Register 5
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 63:32 of flash word data register 1.
For DATAWIDTH == 64: This register represents bits 63:32 of flash word data register 2.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 6-23 CMDDATA5
313029282726252423222120191817161514131211109876543210
VAL
R/W-0h
Table 6-33 CMDDATA5 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
  • 0h = Minimum value of [VAL]
  • FFFFFFFFh = Maximum value of [VAL]

6.6.21 CMDDATA6 (Offset = 1148h) [Reset = 00000000h]

CMDDATA6 is shown in Figure 6-24 and described in Table 6-34.

Return to the Summary Table.

Command Data Register 6
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 95:64 of flash word data register 1.
For DATAWIDTH == 64: This register represents bits 31:0 of flash word data register 3.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 6-24 CMDDATA6
313029282726252423222120191817161514131211109876543210
VAL
R/W-0h
Table 6-34 CMDDATA6 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
  • 0h = Minimum value of [VAL]
  • FFFFFFFFh = Maximum value of [VAL]

6.6.22 CMDDATA7 (Offset = 114Ch) [Reset = 00000000h]

CMDDATA7 is shown in Figure 6-25 and described in Table 6-35.

Return to the Summary Table.

Command Data Register 7
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 127:96 of flash word data register 1.
For DATAWIDTH == 64: This register represents bits 63:32 of flash word data register 3.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 6-25 CMDDATA7
313029282726252423222120191817161514131211109876543210
VAL
R/W-0h
Table 6-35 CMDDATA7 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
  • 0h = Minimum value of [VAL]
  • FFFFFFFFh = Maximum value of [VAL]

6.6.23 CMDDATA8 (Offset = 1150h) [Reset = 00000000h]

CMDDATA8 is shown in Figure 6-26 and described in Table 6-36.

Return to the Summary Table.

Command Data Register 8
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 31:0 of flash word data register 2.
For DATAWIDTH == 64: This register represents bits 31:0 of flash word data register 4.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 6-26 CMDDATA8
313029282726252423222120191817161514131211109876543210
VAL
R/W-0h
Table 6-36 CMDDATA8 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
  • 0h = Minimum value of [VAL]
  • FFFFFFFFh = Maximum value of [VAL]

6.6.24 CMDDATA9 (Offset = 1154h) [Reset = 00000000h]

CMDDATA9 is shown in Figure 6-27 and described in Table 6-37.

Return to the Summary Table.

Command Data Register 9
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 63:32 of flash word data register 2.
For DATAWIDTH == 64: This register represents bits 63:32 of flash word data register 4.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 6-27 CMDDATA9
313029282726252423222120191817161514131211109876543210
VAL
R/W-0h
Table 6-37 CMDDATA9 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
  • 0h = Minimum value of [VAL]
  • FFFFFFFFh = Maximum value of [VAL]

6.6.25 CMDDATA10 (Offset = 1158h) [Reset = 00000000h]

CMDDATA10 is shown in Figure 6-28 and described in Table 6-38.

Return to the Summary Table.

Command Data Register 10
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 95:64 of flash word data register 2.
For DATAWIDTH == 64: This register represents bits 31:0 of flash word data register 5.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 6-28 CMDDATA10
313029282726252423222120191817161514131211109876543210
VAL
R/W-0h
Table 6-38 CMDDATA10 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
  • 0h = Minimum value of [VAL]
  • FFFFFFFFh = Maximum value of [VAL]

6.6.26 CMDDATA11 (Offset = 115Ch) [Reset = 00000000h]

CMDDATA11 is shown in Figure 6-29 and described in Table 6-39.

Return to the Summary Table.

Command Data Register 11
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 127:96 of flash word data register 2.
For DATAWIDTH == 64: This register represents bits 63:32 of flash word data register 5.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 6-29 CMDDATA11
313029282726252423222120191817161514131211109876543210
VAL
R/W-0h
Table 6-39 CMDDATA11 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
  • 0h = Minimum value of [VAL]
  • FFFFFFFFh = Maximum value of [VAL]

6.6.27 CMDDATA12 (Offset = 1160h) [Reset = 00000000h]

CMDDATA12 is shown in Figure 6-30 and described in Table 6-40.

Return to the Summary Table.

Command Data Register 12
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 31:0 of flash word data register 3.
For DATAWIDTH == 64: This register represents bits 31:0 of flash word data register 6.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 6-30 CMDDATA12
313029282726252423222120191817161514131211109876543210
VAL
R/W-0h
Table 6-40 CMDDATA12 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
  • 0h = Minimum value of [VAL]
  • FFFFFFFFh = Maximum value of [VAL]

6.6.28 CMDDATA13 (Offset = 1164h) [Reset = 00000000h]

CMDDATA13 is shown in Figure 6-31 and described in Table 6-41.

Return to the Summary Table.

Command Data Register 13

This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 63:32 of flash word data register 3.
For DATAWIDTH == 64: This register represents bits 63:32 of flash word data register 6.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 6-31 CMDDATA13
313029282726252423222120191817161514131211109876543210
VAL
R/W-0h
Table 6-41 CMDDATA13 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
  • 0h = Minimum value of [VAL]
  • FFFFFFFFh = Maximum value of [VAL]

6.6.29 CMDDATA14 (Offset = 1168h) [Reset = 00000000h]

CMDDATA14 is shown in Figure 6-32 and described in Table 6-42.

Return to the Summary Table.

Command Data Register 14
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 95:64 of flash word data register 3.
For DATAWIDTH == 64: This register represents bits 31:0 of flash word data register 7.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 6-32 CMDDATA14
313029282726252423222120191817161514131211109876543210
VAL
R/W-0h
Table 6-42 CMDDATA14 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
  • 0h = Minimum value of [VAL]
  • FFFFFFFFh = Maximum value of [VAL]

6.6.30 CMDDATA15 (Offset = 116Ch) [Reset = 00000000h]

CMDDATA15 is shown in Figure 6-33 and described in Table 6-43.

Return to the Summary Table.

Command Data Register 15
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 127:96 of flash word data register 3.
For DATAWIDTH == 64: This register represents bits 63:32 of flash word data register 7.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 6-33 CMDDATA15
313029282726252423222120191817161514131211109876543210
VAL
R/W-0h
Table 6-43 CMDDATA15 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
  • 0h = Minimum value of [VAL]
  • FFFFFFFFh = Maximum value of [VAL]

6.6.31 CMDDATA16 (Offset = 1170h) [Reset = 00000000h]

CMDDATA16 is shown in Figure 6-34 and described in Table 6-44.

Return to the Summary Table.

Command Data Register 16
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 31:0 of flash word data register 4.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 6-34 CMDDATA16
313029282726252423222120191817161514131211109876543210
VAL
R/W-0h
Table 6-44 CMDDATA16 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
  • 0h = Minimum value of [VAL]
  • FFFFFFFFh = Maximum value of [VAL]

6.6.32 CMDDATA17 (Offset = 1174h) [Reset = 00000000h]

CMDDATA17 is shown in Figure 6-35 and described in Table 6-45.

Return to the Summary Table.

Command Data Register 17
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 63:32 of flash word data register 4.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 6-35 CMDDATA17
313029282726252423222120191817161514131211109876543210
VAL
R/W-0h
Table 6-45 CMDDATA17 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
  • 0h = Minimum value of [VAL]
  • FFFFFFFFh = Maximum value of [VAL]

6.6.33 CMDDATA18 (Offset = 1178h) [Reset = 00000000h]

CMDDATA18 is shown in Figure 6-36 and described in Table 6-46.

Return to the Summary Table.

Command Data Register 18
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 95:64 of flash word data register 4.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 6-36 CMDDATA18
313029282726252423222120191817161514131211109876543210
VAL
R/W-0h
Table 6-46 CMDDATA18 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
  • 0h = Minimum value of [VAL]
  • FFFFFFFFh = Maximum value of [VAL]

6.6.34 CMDDATA19 (Offset = 117Ch) [Reset = 00000000h]

CMDDATA19 is shown in Figure 6-37 and described in Table 6-47.

Return to the Summary Table.

Command Data Register 19
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 127:96 of flash word data register 4.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 6-37 CMDDATA19
313029282726252423222120191817161514131211109876543210
VAL
R/W-0h
Table 6-47 CMDDATA19 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
  • 0h = Minimum value of [VAL]
  • FFFFFFFFh = Maximum value of [VAL]

6.6.35 CMDDATA20 (Offset = 1180h) [Reset = 00000000h]

CMDDATA20 is shown in Figure 6-38 and described in Table 6-48.

Return to the Summary Table.

Command Data Register 20
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 31:0 of flash word data register 5.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 6-38 CMDDATA20
313029282726252423222120191817161514131211109876543210
VAL
R/W-0h
Table 6-48 CMDDATA20 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
  • 0h = Minimum value of [VAL]
  • FFFFFFFFh = Maximum value of [VAL]

6.6.36 CMDDATA21 (Offset = 1184h) [Reset = 00000000h]

CMDDATA21 is shown in Figure 6-39 and described in Table 6-49.

Return to the Summary Table.

Command Data Register 21
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 63:32 of flash word data register 5.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 6-39 CMDDATA21
313029282726252423222120191817161514131211109876543210
VAL
R/W-0h
Table 6-49 CMDDATA21 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
  • 0h = Minimum value of [VAL]
  • FFFFFFFFh = Maximum value of [VAL]

6.6.37 CMDDATA22 (Offset = 1188h) [Reset = 00000000h]

CMDDATA22 is shown in Figure 6-40 and described in Table 6-50.

Return to the Summary Table.

Command Data Register 22
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 95:64 of flash word data register 5.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 6-40 CMDDATA22
313029282726252423222120191817161514131211109876543210
VAL
R/W-0h
Table 6-50 CMDDATA22 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
  • 0h = Minimum value of [VAL]
  • FFFFFFFFh = Maximum value of [VAL]

6.6.38 CMDDATA23 (Offset = 118Ch) [Reset = 00000000h]

CMDDATA23 is shown in Figure 6-41 and described in Table 6-51.

Return to the Summary Table.

Command Data Register 23
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 127:96 of flash word data register 5.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 6-41 CMDDATA23
313029282726252423222120191817161514131211109876543210
VAL
R/W-0h
Table 6-51 CMDDATA23 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
  • 0h = Minimum value of [VAL]
  • FFFFFFFFh = Maximum value of [VAL]

6.6.39 CMDDATA24 (Offset = 1190h) [Reset = 00000000h]

CMDDATA24 is shown in Figure 6-42 and described in Table 6-52.

Return to the Summary Table.

Command Data Register 24
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 31:0 of flash word data register 6.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 6-42 CMDDATA24
313029282726252423222120191817161514131211109876543210
VAL
R/W-0h
Table 6-52 CMDDATA24 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
  • 0h = Minimum value of [VAL]
  • FFFFFFFFh = Maximum value of [VAL]

6.6.40 CMDDATA25 (Offset = 1194h) [Reset = 00000000h]

CMDDATA25 is shown in Figure 6-43 and described in Table 6-53.

Return to the Summary Table.

Command Data Register 25
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 63:32 of flash word data register 6.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 6-43 CMDDATA25
313029282726252423222120191817161514131211109876543210
VAL
R/W-0h
Table 6-53 CMDDATA25 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
  • 0h = Minimum value of [VAL]
  • FFFFFFFFh = Maximum value of [VAL]

6.6.41 CMDDATA26 (Offset = 1198h) [Reset = 00000000h]

CMDDATA26 is shown in Figure 6-44 and described in Table 6-54.

Return to the Summary Table.

Command Data Register 26
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 95:64 of flash word data register 6.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 6-44 CMDDATA26
313029282726252423222120191817161514131211109876543210
VAL
R/W-0h
Table 6-54 CMDDATA26 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
  • 0h = Minimum value of [VAL]
  • FFFFFFFFh = Maximum value of [VAL]

6.6.42 CMDDATA27 (Offset = 119Ch) [Reset = 00000000h]

CMDDATA27 is shown in Figure 6-45 and described in Table 6-55.

Return to the Summary Table.

Command Data Register 27
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 127:96 of flash word data register 6.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 6-45 CMDDATA27
313029282726252423222120191817161514131211109876543210
VAL
R/W-0h
Table 6-55 CMDDATA27 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
  • 0h = Minimum value of [VAL]
  • FFFFFFFFh = Maximum value of [VAL]

6.6.43 CMDDATA28 (Offset = 11A0h) [Reset = 00000000h]

CMDDATA28 is shown in Figure 6-46 and described in Table 6-56.

Return to the Summary Table.

Command Data Register 28
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 31:0 of flash word data register 7.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 6-46 CMDDATA28
313029282726252423222120191817161514131211109876543210
VAL
R/W-0h
Table 6-56 CMDDATA28 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
  • 0h = Minimum value of [VAL]
  • FFFFFFFFh = Maximum value of [VAL]

6.6.44 CMDDATA29 (Offset = 11A4h) [Reset = 00000000h]

CMDDATA29 is shown in Figure 6-47 and described in Table 6-57.

Return to the Summary Table.

Command Data Register 29
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 63:32 of flash word data register 7.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 6-47 CMDDATA29
313029282726252423222120191817161514131211109876543210
VAL
R/W-0h
Table 6-57 CMDDATA29 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
  • 0h = Minimum value of [VAL]
  • FFFFFFFFh = Maximum value of [VAL]

6.6.45 CMDDATA30 (Offset = 11A8h) [Reset = 00000000h]

CMDDATA30 is shown in Figure 6-48 and described in Table 6-58.

Return to the Summary Table.

Command Data Register 30
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 95:64 of flash word data register 7.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 6-48 CMDDATA30
313029282726252423222120191817161514131211109876543210
VAL
R/W-0h
Table 6-58 CMDDATA30 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
  • 0h = Minimum value of [VAL]
  • FFFFFFFFh = Maximum value of [VAL]

6.6.46 CMDDATA31 (Offset = 11ACh) [Reset = 00000000h]

CMDDATA31 is shown in Figure 6-49 and described in Table 6-59.

Return to the Summary Table.

Command Data Register 31
This register forms the data for a command.
For DATAWIDTH == 128: This register represents bits 127:96 of flash word data register 7.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.

Figure 6-49 CMDDATA31
313029282726252423222120191817161514131211109876543210
VAL
R/W-0h
Table 6-59 CMDDATA31 Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhA 32-bit data value is placed in this field.
  • 0h = Minimum value of [VAL]
  • FFFFFFFFh = Maximum value of [VAL]

6.6.47 CMDDATAECC0 (Offset = 11B0h) [Reset = 00000000h]

CMDDATAECC0 is shown in Figure 6-50 and described in Table 6-60.

Return to the Summary Table.

Command Data Register 0
This register forms the ECC portion of the data for a command. This ECC data
in this register covers flash data register 0.
The hardware ECC generation in flash wrapper can be overridden and ECC data
developed elsewhere can be used. ECC data is placed in this register.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Figure 6-50 CMDDATAECC0
313029282726252423222120191817161514131211109876543210
RESERVEDVAL1VAL0
R-0hR/W-0hR/W-0h
Table 6-60 CMDDATAECC0 Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-8VAL1R/WFFhECC data for bits 127:64 of the data is placed here.
  • 0h = Minimum value
  • FFh = Maximum value
7-0VAL0R/WFFhECC data for bits 63:0 of the data is placed here.
  • 0h = Minimum value
  • FFh = Maximum value

6.6.48 CMDDATAECC1 (Offset = 11B4h) [Reset = 00000000h]

CMDDATAECC1 is shown in Figure 6-51 and described in Table 6-61.

Return to the Summary Table.

Command Data Register 1
This register forms the ECC portion of the data for a command. This ECC data
in this register covers flash data register 0.
The hardware ECC generation in flash wrapper can be overridden and ECC data
developed elsewhere can be used. ECC data is placed in this register.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Figure 6-51 CMDDATAECC1
313029282726252423222120191817161514131211109876543210
RESERVEDVAL1VAL0
R-0hR/W-0hR/W-0h
Table 6-61 CMDDATAECC1 Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-8VAL1R/WFFhECC data for bits 127:64 of the data is placed here.
  • 0h = Minimum value
  • FFh = Maximum value
7-0VAL0R/WFFhECC data for bits 63:0 of the data is placed here.
  • 0h = Minimum value
  • FFh = Maximum value

6.6.49 CMDDATAECC2 (Offset = 11B8h) [Reset = 00000000h]

CMDDATAECC2 is shown in Figure 6-52 and described in Table 6-62.

Return to the Summary Table.

Command Data Register 2
This register forms the ECC portion of the data for a command. This ECC data
in this register covers flash data register 2.
The hardware ECC generation in flash wrapper can be overridden and ECC data
developed elsewhere can be used. ECC data is placed in this register.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Figure 6-52 CMDDATAECC2
313029282726252423222120191817161514131211109876543210
RESERVEDVAL1VAL0
R-0hR/W-0hR/W-0h
Table 6-62 CMDDATAECC2 Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-8VAL1R/WFFhECC data for bits 127:64 of the data is placed here.
  • 0h = Minimum value
  • FFh = Maximum value
7-0VAL0R/WFFhECC data for bits 63:0 of the data is placed here.
  • 0h = Minimum value
  • FFh = Maximum value

6.6.50 CMDDATAECC3 (Offset = 11BCh) [Reset = 00000000h]

CMDDATAECC3 is shown in Figure 6-53 and described in Table 6-63.

Return to the Summary Table.

Command Data Register 3
This register forms the ECC portion of the data for a command. This ECC data
in this register covers flash data register 3.
The hardware ECC generation in flash wrapper can be overridden and ECC data
developed elsewhere can be used. ECC data is placed in this register.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Figure 6-53 CMDDATAECC3
313029282726252423222120191817161514131211109876543210
RESERVEDVAL1VAL0
R-0hR/W-0hR/W-0h
Table 6-63 CMDDATAECC3 Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-8VAL1R/WFFhECC data for bits 127:64 of the data is placed here.
  • 0h = Minimum value
  • FFh = Maximum value
7-0VAL0R/WFFhECC data for bits 63:0 of the data is placed here.
  • 0h = Minimum value
  • FFh = Maximum value

6.6.51 CMDDATAECC4 (Offset = 11C0h) [Reset = 00000000h]

CMDDATAECC4 is shown in Figure 6-54 and described in Table 6-64.

Return to the Summary Table.

Command Data Register 4
This register forms the ECC portion of the data for a command. This ECC data
in this register covers flash data register 4.
The hardware ECC generation in flash wrapper can be overridden and ECC data
developed elsewhere can be used. ECC data is placed in this register.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Figure 6-54 CMDDATAECC4
313029282726252423222120191817161514131211109876543210
RESERVEDVAL1VAL0
R-0hR/W-0hR/W-0h
Table 6-64 CMDDATAECC4 Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-8VAL1R/WFFhECC data for bits 127:64 of the data is placed here.
  • 0h = Minimum value
  • FFh = Maximum value
7-0VAL0R/WFFhECC data for bits 63:0 of the data is placed here.
  • 0h = Minimum value
  • FFh = Maximum value

6.6.52 CMDDATAECC5 (Offset = 11C4h) [Reset = 00000000h]

CMDDATAECC5 is shown in Figure 6-55 and described in Table 6-65.

Return to the Summary Table.

Command Data Register 5
This register forms the ECC portion of the data for a command. This ECC data
in this register covers flash data register 5.
The hardware ECC generation in flash wrapper can be overridden and ECC data
developed elsewhere can be used. ECC data is placed in this register.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Figure 6-55 CMDDATAECC5
313029282726252423222120191817161514131211109876543210
RESERVEDVAL1VAL0
R-0hR/W-0hR/W-0h
Table 6-65 CMDDATAECC5 Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-8VAL1R/WFFhECC data for bits 127:64 of the data is placed here.
  • 0h = Minimum value
  • FFh = Maximum value
7-0VAL0R/WFFhECC data for bits 63:0 of the data is placed here.
  • 0h = Minimum value
  • FFh = Maximum value

6.6.53 CMDDATAECC6 (Offset = 11C8h) [Reset = 00000000h]

CMDDATAECC6 is shown in Figure 6-56 and described in Table 6-66.

Return to the Summary Table.

Command Data Register 6
This register forms the ECC portion of the data for a command. This ECC data
in this register covers flash data register 6.
The hardware ECC generation in flash wrapper can be overridden and ECC data
developed elsewhere can be used. ECC data is placed in this register.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Figure 6-56 CMDDATAECC6
313029282726252423222120191817161514131211109876543210
RESERVEDVAL1VAL0
R-0hR/W-0hR/W-0h
Table 6-66 CMDDATAECC6 Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-8VAL1R/WFFhECC data for bits 127:64 of the data is placed here.
  • 0h = Minimum value
  • FFh = Maximum value
7-0VAL0R/WFFhECC data for bits 63:0 of the data is placed here.
  • 0h = Minimum value
  • FFh = Maximum value

6.6.54 CMDDATAECC7 (Offset = 11CCh) [Reset = 00000000h]

CMDDATAECC7 is shown in Figure 6-57 and described in Table 6-67.

Return to the Summary Table.

Command Data Register 7
This register forms the ECC portion of the data for a command. This ECC data
in this register covers flash data register 7.
The hardware ECC generation in flash wrapper can be overridden and ECC data
developed elsewhere can be used. ECC data is placed in this register.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
Use cases for the CMDDATA* registers are as follows:
1) Program - These registers contain the data to be programmed.
2) Erase - These registers are not used.
3) Read Verify - These registers contain data to be verified.
This register is used to aggregate masking for bits that do not
require additional program pulses during program operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Figure 6-57 CMDDATAECC7
313029282726252423222120191817161514131211109876543210
RESERVEDVAL1VAL0
R-0hR/W-0hR/W-0h
Table 6-67 CMDDATAECC7 Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0hReserved
15-8VAL1R/WFFhECC data for bits 127:64 of the data is placed here.
  • 0h = Minimum value
  • FFh = Maximum value
7-0VAL0R/WFFhECC data for bits 63:0 of the data is placed here.
  • 0h = Minimum value
  • FFh = Maximum value

6.6.55 CMDWEPROTA (Offset = 11D0h) [Reset = 00000000h]

CMDWEPROTA is shown in Figure 6-58 and described in Table 6-68.

Return to the Summary Table.

Command WriteErase Protect A Register
This register allows the first 32 sectors of the main region to be protected from
program or erase, with 1 bit protecting each sector. If the main region size is smaller than 32
sectors, then this register provides protection for the whole region.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
In addition, this register is used to aggregate masking for sectors that do not
require additional erase pulses during bank erase operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Figure 6-58 CMDWEPROTA
313029282726252423222120191817161514131211109876543210
VAL
R/W-0h
Table 6-68 CMDWEPROTA Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhEach bit protects 1 sector. bit [0]: When 1, sector 0 of the flash memory will be protected from program and erase. bit [1]: When 1, sector 1 of the flash memory will be protected from program and erase. : : bit [31]: When 1, sector 31 of the flash memory will be protected from program and erase.
  • 0h = Minimum value of [VAL]
  • FFFFFFFFh = Maximum value of [VAL]

6.6.56 CMDWEPROTB (Offset = 11D4h) [Reset = 00000000h]

CMDWEPROTB is shown in Figure 6-59 and described in Table 6-69.

Return to the Summary Table.

Command WriteErase Protect B Register
This register allows main region sectors to be protected from program and
erase. Each bit corresponds to a group of 8 sectors.
There are 3 cases for how these protect bits are applied:
1. Single-bank system:
In the case where only a single flash bank is present,
the first 32 sectors are protected via the CMDWEPROTA register. Thus, the
protection give by the bits in CMDWEPROTB begin with sector 32.
2. Multi-bank system, Bank 0:
When multiple flash banks are present, the first
32 sectors of bank 0 are protected via the CMDWEPROTA register. Thus, only
bits 4 and above of CMDWEPROTB would be applicable to bank 0. The protection of
bit 4 and above would begin at sector 32. Bits 3:0
of WEPROTB are ignored for bank 0.
3. Multi-bank system, Banks 1-N:
For banks other than bank 0 in a multi-bank system, CMDWEPROTA has
no effect, so the bits in CMDWEPROTB will protect these banks starting
from sector 0.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
In addition, this register is used to aggregate masking for sectors that do not
require additional erase pulses during bank erase operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Figure 6-59 CMDWEPROTB
313029282726252423222120191817161514131211109876543210
VAL
R/W-0h
Table 6-69 CMDWEPROTB Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhEach bit protects a group of 8 sectors. When a bit is 1, the associated 8 sectors in the flash will be protected from program and erase. A maximum of 256 sectors can be protected with this register.
  • 0h = Minimum value of [VAL]
  • FFFFFFFFh = Maximum value of [VAL]

6.6.57 CMDWEPROTC (Offset = 11D8h) [Reset = 00000000h]

CMDWEPROTC is shown in Figure 6-60 and described in Table 6-70.

Return to the Summary Table.

Command WriteErase Protect C Register
This register allows main region sectors to be protected from program and
erase. Each bit corresponds to a group of 8 sectors.
This register extends the protection bits from the CMDWEPROTB
register to cover bank sizes larger than 32*8=256 sectors.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
In addition, this register is used to aggregate masking for sectors that do not
require additional erase pulses during bank erase operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Figure 6-60 CMDWEPROTC
313029282726252423222120191817161514131211109876543210
VAL
R/W-0h
Table 6-70 CMDWEPROTC Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhEach bit protects a group of 8 sectors. When a bit is 1, the associated 8 sectors in the flash will be protected from program and erase. Note that the sectors protected with this register start at sector 256 in the flash, where the sectors protected by the CMDWEPROTB register end.
  • 0h = Minimum value of [VAL]
  • FFFFFFFFh = Maximum value of [VAL]

6.6.58 CMDWEPROTNM (Offset = 1210h) [Reset = 00000000h]

CMDWEPROTNM is shown in Figure 6-61 and described in Table 6-71.

Return to the Summary Table.

Command WriteErase Protect Non-Main
Register
This register allows non-main region region sectors to be protected
from program and erase. Each bit corresponds to 1 sector.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
In addition, this register is used to aggregate masking for sectors that do not
require additional erase pulses during bank erase operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Figure 6-61 CMDWEPROTNM
313029282726252423222120191817161514131211109876543210
VAL
R/W-0h
Table 6-71 CMDWEPROTNM Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhEach bit protects 1 sector. bit [0]: When 1, sector 0 of the non-main region will be protected from program and erase. bit [1]: When 1, sector 1 of the non-main region will be protected from program and erase. : : bit [31]: When 1, sector 31 of the non-main will be protected from program and erase.
  • 0h = Minimum value of [VAL]
  • FFFFFFFFh = Maximum value of [VAL]

6.6.59 CMDWEPROTTR (Offset = 1214h) [Reset = 00000000h]

CMDWEPROTTR is shown in Figure 6-62 and described in Table 6-72.

Return to the Summary Table.

Command WriteErase Protect Trim
Register
This register allows trim region sectors to be protected
from program and erase. Each bit corresponds to 1 sector.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
In addition, this register is used to aggregate masking for sectors that do not
require additional erase pulses during bank erase operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Figure 6-62 CMDWEPROTTR
313029282726252423222120191817161514131211109876543210
VAL
R/W-0h
Table 6-72 CMDWEPROTTR Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhEach bit protects 1 sector. bit [0]: When 1, sector 0 of the engr region will be protected from program and erase. bit [1]: When 1, sector 1 of the engr region will be protected from program and erase. : : bit [31]: When 1, sector 31 of the engr region will be protected from program and erase.
  • 0h = Minimum value of [VAL]
  • FFFFFFFFh = Maximum value of [VAL]

6.6.60 CMDWEPROTEN (Offset = 1218h) [Reset = 00000000h]

CMDWEPROTEN is shown in Figure 6-63 and described in Table 6-73.

Return to the Summary Table.

Command WriteErase Protect Engr
Register
This register allows engr region sectors to be protected
from program and erase. Each bit corresponds to 1 sector.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.
In addition, this register is used to aggregate masking for sectors that do not
require additional erase pulses during bank erase operations, and will be
written to all 1 after the completion of all flash wrapper commands.

Figure 6-63 CMDWEPROTEN
313029282726252423222120191817161514131211109876543210
VAL
R/W-0h
Table 6-73 CMDWEPROTEN Field Descriptions
BitFieldTypeResetDescription
31-0VALR/WFFFFFFFFhEach bit protects 1 sector. bit [0]: When 1, sector 0 of the engr region will be protected from program and erase. bit [1]: When 1, sector 1 of the engr region will be protected from program and erase. : : bit [31]: When 1, sector 31 of the engr region will be protected from program and erase.
  • 0h = Minimum value of [VAL]
  • FFFFFFFFh = Maximum value of [VAL]

6.6.61 CFGCMD (Offset = 13B0h) [Reset = 00000000h]

CFGCMD is shown in Figure 6-64 and described in Table 6-74.

Return to the Summary Table.

Command Configuration Register This register configures specific capabilities of the state machine for related to the execution of a command. This register is blocked for writes after CMDEXEC is written to a 1 and prior to STATCMD.DONE being set by the hardware to indicate that command execution has completed.

Figure 6-64 CFGCMD
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDHOLDCLKSTRENCTRLCLKSTRENRDCLKSTRENWAITSTATE
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 6-74 CFGCMD Field Descriptions
BitFieldTypeResetDescription
31-7RESERVEDR0hReserved
6HOLDCLKSTRENR/W1hEnable pulse stretching for the clocking of the hold latches for inputs to the flash bank. This effectively divides the flash controller internal clock in order to create a 50/50 duty cycle clock for hold latching.
  • 0h = Disable
  • 1h = Enable
5CTRLCLKSTRENR/W1hEnable pulse stretching when generating a control clock to the flash bank from the
flash wrapper. This effectively divides the control clock driven to the bank in order
to avoid minimum pulse width requirements at the bank.
  • 0h = Disable
  • 1h = Enable
4RDCLKSTRENR/W1hEnable pulse stretching when generating a read clock to the flash bank from the
flash wrapper. This effectively divides the read clock driven to the bank in order
to avoid minimum pulse width requirements at the bank.
  • 0h = Disable
  • 1h = Enable
3-0WAITSTATER/W2hWait State setting for program verify, erase verify and read verify
  • 0h = Minimum value
  • Fh = Maximum value

6.6.62 CFGPCNT (Offset = 13B4h) [Reset = 00000000h]

CFGPCNT is shown in Figure 6-65 and described in Table 6-75.

Return to the Summary Table.

Pulse Counter Configuration Register
This register allows further configuration of maximum pulse counts for
program and erase operations.
This register is blocked for writes after a 1 is written to the CMDEXEC
register and prior to STATCMD.DONE being set by the flash wrapper
hardware.

Figure 6-65 CFGPCNT
3130292827262524
MAXERSPCNTVAL
R/W-0h
2322212019181716
MAXERSPCNTVALRESERVEDMAXERSPCNTOVR
R/W-0hR-0hR/W-0h
15141312111098
RESERVEDMAXPCNTVAL
R-0hR/W-0h
76543210
MAXPCNTVALRESERVEDMAXPCNTOVR
R/W-0hR-0hR/W-0h
Table 6-75 CFGPCNT Field Descriptions
BitFieldTypeResetDescription
31-20MAXERSPCNTVALR/W0hOverride maximum pulse count for erase with this value. If MAXERSPCNTOVR = 0, then this field is ignored. If MAXERSPCNTOVR = 1, then this value will be used to override the max pulse count for erase.
  • 0h = Minimum value
  • FFFh = Maximum value
19-17RESERVEDR0hReserved
16MAXERSPCNTOVRR/W0hOverride hard-wired maximum pulse count for erase. If set, then the value in MAXERSPCNTVAL will be used as the max pulse count for erase operations. By default, this bit is 0, and a hard-wired max pulse count is used.
  • 0h = Use hard-wired (default) value for maximum pulse count
  • 1h = Use value from MAXERSPCNTVAL field as maximum erase pulse count
15-12RESERVEDR0hReserved
11-4MAXPCNTVALR/W0hOverride maximum pulse counter with this value. If MAXPCNTOVR = 0, then this field is ignored. If MAXPCNTOVR = 1 and MAXERSPCNTOVR = 0, then this value will be used to override the max pulse count for both program and erase. Full max value will be {4'h0, MAXPCNTVAL} . If MAXPCNTOVR = 1 and MAXERSPCNTOVR = 1, then this value will be used to override the max pulse count for program only. Full max value will be {4'h0, MAXPCNTVAL}.
  • 0h = Minimum value
  • FFh = Maximum value
3-1RESERVEDR0hReserved
0MAXPCNTOVRR/W0hOverride hard-wired maximum pulse count. If MAXERSPCNTOVR is not set, then setting this value alone will override the max pulse count for both program and erase. If MAXERSPCNTOVR is set, then this bit will only control the max pulse count setting for program. By default, this bit is 0, and a hard-wired max pulse count is used.
  • 0h = Use hard-wired (default) value for maximum pulse count
  • 1h = Use value from MAXPCNTVAL field as maximum puse count

6.6.63 STATCMD (Offset = 13D0h) [Reset = 00000000h]

STATCMD is shown in Figure 6-66 and described in Table 6-76.

Return to the Summary Table.

Command Status Register This register contains status regarding completion and errors of command execution.

Figure 6-66 STATCMD
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDFAILMISCRESERVEDFAILINVDATA
R-0hR-0hR-0hR-0h
76543210
FAILMODEFAILILLADDRFAILVERIFYFAILWEPROTRESERVEDCMDINPROGRESSCMDPASSCMDDONE
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 6-76 STATCMD Field Descriptions
BitFieldTypeResetDescription
31-13RESERVEDR0hReserved
12FAILMISCR0hCommand failed due to error other than write/erase protect violation or verify error. This is an extra bit in case a new failure mechanism is added which requires a status bit.
  • 0h = No Fail
  • 1h = Fail
11-9RESERVEDR0hReserved
8FAILINVDATAR0hProgram command failed because an attempt was made to program a stored 0 value to a 1.
  • 0h = No Fail
  • 1h = Fail
7FAILMODER0hCommand failed because a bank has been set to a mode other than READ. Program and Erase commands cannot be initiated unless all banks are in READ mode.
  • 0h = No Fail
  • 1h = Fail
6FAILILLADDRR0hCommand failed due to the use of an illegal address
  • 0h = No Fail
  • 1h = Fail
5FAILVERIFYR0hCommand failed due to verify error
  • 0h = No Fail
  • 1h = Fail
4FAILWEPROTR0hCommand failed due to Write/Erase Protect Sector Violation
  • 0h = No Fail
  • 1h = Fail
3RESERVEDR0hReserved
2CMDINPROGRESSR0hCommand In Progress
  • 0h = Complete
  • 1h = In Progress
1CMDPASSR0hCommand Pass - valid when CMD_DONE field is 1
  • 0h = Fail
  • 1h = Pass
0CMDDONER0hCommand Done
  • 0h = Not Done
  • 1h = Done

6.6.64 STATADDR (Offset = 13D4h) [Reset = 00000000h]

STATADDR is shown in Figure 6-67 and described in Table 6-77.

Return to the Summary Table.

Current Address Counter Value Read only register giving read access to the state machine current address. A bank id, region id and address are stored in this register and are incremented as necessary during execution of a command.

Figure 6-67 STATADDR
31302928272625242322212019181716
RESERVEDBANKIDREGIONID
R-0hR-0hR-0h
1514131211109876543210
BANKADDR
R-0h
Table 6-77 STATADDR Field Descriptions
BitFieldTypeResetDescription
31-26RESERVEDR0hReserved
25-21BANKIDR0hCurrent Bank ID A bank indicator is stored in this register which represents the current bank on which the state machine is operating. There is 1 bit per bank.
  • 1h (R/W) = Bank 0
  • 2h (R/W) = Bank 1
  • 4h (R/W) = Bank 2
  • 8h (R/W) = Bank 3
  • 10h (R/W) = Bank 4
20-16REGIONIDR1hCurrent Region ID A region indicator is stored in this register which represents the current flash region on which the state machine is operating.
  • 1h (R/W) = Main Region
  • 2h (R/W) = Non-Main Region
  • 4h (R/W) = Trim Region
  • 8h (R/W) = Engr Region
15-0BANKADDRR0hCurrent Bank Address A bank offset address is stored in this register.
  • 0h = Minimum value
  • FFFFh = Maximum value

6.6.65 STATPCNT (Offset = 13D8h) [Reset = 00000000h]

STATPCNT is shown in Figure 6-68 and described in Table 6-78.

Return to the Summary Table.

Current Pulse Count Register: Read only register giving read access to the state machine current pulse count value for program/erase operations.

Figure 6-68 STATPCNT
313029282726252423222120191817161514131211109876543210
RESERVEDPULSECNT
R-0hR-0h
Table 6-78 STATPCNT Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11-0PULSECNTR0hCurrent Pulse Counter Value
  • 0h = Minimum value
  • FFFh = Maximum value

6.6.66 STATMODE (Offset = 13DCh) [Reset = 00000000h]

STATMODE is shown in Figure 6-69 and described in Table 6-79.

Return to the Summary Table.

Mode Status Register Indicates any banks which not in READ mode, and it indicates the mode which the bank(s) are in.

Figure 6-69 STATMODE
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDBANK1TRDYBANK2TRDY
R-0hR-0hR-0h
15141312111098
RESERVEDBANKMODE
R-0hR-0h
76543210
RESERVEDRESERVEDBANKNOTINRD
R-0hR-0hR-0h
Table 6-79 STATMODE Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0hReserved
17BANK1TRDYR0hBank 1T Ready. Bank(s) are ready for 1T access. This is accomplished when the bank and pump have been trimmed.
  • 0h = Not ready
  • 1h = Ready
16BANK2TRDYR0hBank 2T Ready. Bank(s) are ready for 2T access. This is accomplished when the pump has fully driven power rails to the bank(s).
  • 0h = Not ready
  • 1h = Ready
15-12RESERVEDR0hReserved
11-8BANKMODER0hIndicates mode of bank(s) that are not in READ mode
  • 0h = Read Mode
  • 2h = Read Margin 0 Mode
  • 4h = Read Margin 1 Mode
  • 6h = Read Margin 0B Mode
  • 7h = Read Margin 1B Mode
  • 9h = Program Verify Mode
  • Ah = Program Single Word
  • Bh = Erase Verify Mode
  • Ch = Erase Sector
  • Eh = Program Multiple Word
  • Fh = Erase Bank
7-5RESERVEDR0hReserved
4-1RESERVEDR0h
0BANKNOTINRDR0hBank not in read mode. Indicates which banks are not in READ mode. There is 1 bit per bank.
  • 1h (R/W) = Bank 0
  • 2h (R/W) = Bank 1
  • 4h (R/W) = Bank 2
  • 8h (R/W) = Bank 3
  • 10h (R/W) = Bank 4

6.6.67 GBLINFO0 (Offset = 13F0h) [Reset = 00000000h]

GBLINFO0 is shown in Figure 6-70 and described in Table 6-80.

Return to the Summary Table.

Global Info 0 Register Read only register detailing information about sector size and number of banks present.

Figure 6-70 GBLINFO0
31302928272625242322212019181716
RESERVEDNUMBANKS
R-0hR-0h
1514131211109876543210
SECTORSIZE
R-0h
Table 6-80 GBLINFO0 Field Descriptions
BitFieldTypeResetDescription
31-19RESERVEDR0hReserved
18-16NUMBANKSR0hNumber of banks instantiated Minimum: 1 Maximum: 5
  • 1h = Minimum value
  • 5h = Maximum value
15-0SECTORSIZER800hSector size in bytes
  • 400h (R) = Sector size is ONEKB
  • 800h (R) = Sector size is TWOKB

6.6.68 GBLINFO1 (Offset = 13F4h) [Reset = 00000000h]

GBLINFO1 is shown in Figure 6-71 and described in Table 6-81.

Return to the Summary Table.

Global Info 1 Register Read only register detailing information about data, ecc and redundant data widths in bits.

Figure 6-71 GBLINFO1
31302928272625242322212019181716
RESERVEDREDWIDTH
R-0hR-0h
1514131211109876543210
RESERVEDECCWIDTHDATAWIDTH
R-0hR-0hR-0h
Table 6-81 GBLINFO1 Field Descriptions
BitFieldTypeResetDescription
31-19RESERVEDR0hReserved
18-16REDWIDTHR4hRedundant data width in bits
  • 0h (R) = Redundant data width is 0. Redundancy/Repair not present.
  • 2h (R) = Redundant data width is 2 bits
  • 4h (R) = Redundant data width is 4 bits
15-13RESERVEDR0hReserved
12-8ECCWIDTHR10hECC data width in bits
  • 0h (R) = ECC data width is 0. ECC not used.
  • 8h (R) = ECC data width is 8 bits
  • 10h (R) = ECC data width is 16 bits
7-0DATAWIDTHR80hData width in bits
  • 40h (R) = Data width is 64 bits
  • 80h (R) = Data width is 128 bits

6.6.69 GBLINFO2 (Offset = 13F8h) [Reset = 00000000h]

GBLINFO2 is shown in Figure 6-72 and described in Table 6-82.

Return to the Summary Table.

Global Info 2 Register Read only register detailing information about the number of data registers present.

Figure 6-72 GBLINFO2
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDDATAREGISTERS
R-0hR-0h
Table 6-82 GBLINFO2 Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3-0DATAREGISTERSR1hNumber of data registers present.

6.6.70 BANK0INFO0 (Offset = 1400h) [Reset = 00000000h]

BANK0INFO0 is shown in Figure 6-73 and described in Table 6-83.

Return to the Summary Table.

Bank Info 0 Register for bank 0. Read only register detailing information about Main region size in the bank.

Figure 6-73 BANK0INFO0
313029282726252423222120191817161514131211109876543210
RESERVEDMAINSIZE
R-0hR-0h
Table 6-83 BANK0INFO0 Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11-0MAINSIZER0hMain region size in sectors Minimum: 0x8 (8) Maximum: 0x200 (512)
  • 8h = Minimum value of [MAINSIZE]
  • 200h = Maximum value of [MAINSIZE]

6.6.71 BANK0INFO1 (Offset = 1404h) [Reset = 00000000h]

BANK0INFO1 is shown in Figure 6-74 and described in Table 6-84.

Return to the Summary Table.

Bank Info1 Register for bank 0. Read only register detailing information about Non-Main, Trim, and Engr region sizes in the bank.

Figure 6-74 BANK0INFO1
31302928272625242322212019181716
RESERVEDENGRSIZE
R-0hR-0h
1514131211109876543210
TRIMSIZENONMAINSIZE
R-0hR-0h
Table 6-84 BANK0INFO1 Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-16ENGRSIZER20hEngr region size in sectors Minimum: 0x0 (0) Maximum: 0x10 (16)
  • 0h = Minimum value of [ENGRSIZE]
  • 20h = Maximum value of [ENGRSIZE]
15-8TRIMSIZER20hTrim region size in sectors Minimum: 0x0 (0) Maximum: 0x10 (16)
  • 0h = Minimum value of [TRIMSIZE]
  • 20h = Maximum value of [TRIMSIZE]
7-0NONMAINSIZER20hNon-main region size in sectors Minimum: 0x0 (0) Maximum: 0x10 (16)
  • 0h = Minimum value of [NONMAINSIZE]
  • 20h = Maximum value of [NONMAINSIZE]

6.6.72 BANK1INFO0 (Offset = 1410h) [Reset = 00000000h]

BANK1INFO0 is shown in Figure 6-75 and described in Table 6-85.

Return to the Summary Table.

Bank Info 0 Register for bank 1. Read only register detailing information about Main region size in the bank.

Figure 6-75 BANK1INFO0
313029282726252423222120191817161514131211109876543210
RESERVEDMAINSIZE
R-0hR-0h
Table 6-85 BANK1INFO0 Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11-0MAINSIZER200hMain region size in sectors Minimum: 0x8 (8) Maximum: 0x200 (512)
  • 8h = Minimum value of [MAINSIZE]
  • 200h = Maximum value of [MAINSIZE]

6.6.73 BANK1INFO1 (Offset = 1414h) [Reset = 00000000h]

BANK1INFO1 is shown in Figure 6-76 and described in Table 6-86.

Return to the Summary Table.

Bank Info1 Register for bank 1. Read only register detailing information about Non-Main, Trim, and Engr region sizes in the bank.

Figure 6-76 BANK1INFO1
31302928272625242322212019181716
RESERVEDENGRSIZE
R-0hR-0h
1514131211109876543210
TRIMSIZENONMAINSIZE
R-0hR-0h
Table 6-86 BANK1INFO1 Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-16ENGRSIZER20hEngr region size in sectors Minimum: 0x0 (0) Maximum: 0x10 (16)
  • 0h = Minimum value of [ENGRSIZE]
  • 20h = Maximum value of [ENGRSIZE]
15-8TRIMSIZER20hTrim region size in sectors
  • 0h = Minimum value of [TRIMSIZE]
  • 20h = Maximum value of [TRIMSIZE]
7-0NONMAINSIZER20hNon-main region size in sectors
  • 0h = Minimum value of [NONMAINSIZE]
  • 20h = Maximum value of [NONMAINSIZE]

6.6.74 BANK2INFO0 (Offset = 1420h) [Reset = 00000000h]

BANK2INFO0 is shown in Figure 6-77 and described in Table 6-87.

Return to the Summary Table.

Bank Info 0 Register for bank 2. Read only register detailing information about Main region size in the bank.

Figure 6-77 BANK2INFO0
313029282726252423222120191817161514131211109876543210
RESERVEDMAINSIZE
R-0hR-0h
Table 6-87 BANK2INFO0 Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11-0MAINSIZER200hMain region size in sectors Minimum: 0x8 (8) Maximum: 0x200 (512)
  • 8h = Minimum value of [MAINSIZE]
  • 200h = Maximum value of [MAINSIZE]

6.6.75 BANK2INFO1 (Offset = 1424h) [Reset = 00000000h]

BANK2INFO1 is shown in Figure 6-78 and described in Table 6-88.

Return to the Summary Table.

Bank Info1 Register for bank 2. Read only register detailing information about Non-Main, Trim, and Engr region sizes in the bank.

Figure 6-78 BANK2INFO1
31302928272625242322212019181716
RESERVEDENGRSIZE
R-0hR-0h
1514131211109876543210
TRIMSIZENONMAINSIZE
R-0hR-0h
Table 6-88 BANK2INFO1 Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-16ENGRSIZER20hEngr region size in sectors
  • 0h = Minimum value of [ENGRSIZE]
  • 20h = Maximum value of [ENGRSIZE]
15-8TRIMSIZER20hTrim region size in sectors
  • 0h = Minimum value of [TRIMSIZE]
  • 20h = Maximum value of [TRIMSIZE]
7-0NONMAINSIZER20hNon-main region size in sectors
  • 0h = Minimum value of [NONMAINSIZE]
  • 20h = Maximum value of [NONMAINSIZE]

6.6.76 BANK3INFO0 (Offset = 1430h) [Reset = 00000000h]

BANK3INFO0 is shown in Figure 6-79 and described in Table 6-89.

Return to the Summary Table.

Bank Info 0 Register for bank 3. Read only register detailing information about Main region size in the bank.

Figure 6-79 BANK3INFO0
313029282726252423222120191817161514131211109876543210
RESERVEDMAINSIZE
R-0hR-0h
Table 6-89 BANK3INFO0 Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11-0MAINSIZER200hMain region size in sectors
  • 8h = Minimum value of [MAINSIZE]
  • 200h = Maximum value of [MAINSIZE]

6.6.77 BANK3INFO1 (Offset = 1434h) [Reset = 00000000h]

BANK3INFO1 is shown in Figure 6-80 and described in Table 6-90.

Return to the Summary Table.

Bank Info1 Register for bank 3. Read only register detailing information about Non-Main, Trim, and Engr region sizes in the bank.

Figure 6-80 BANK3INFO1
31302928272625242322212019181716
RESERVEDENGRSIZE
R-0hR-0h
1514131211109876543210
TRIMSIZENONMAINSIZE
R-0hR-0h
Table 6-90 BANK3INFO1 Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-16ENGRSIZER20hEngr region size in sectors
  • 0h = Minimum value of [ENGRSIZE]
  • 20h = Maximum value of [ENGRSIZE]
15-8TRIMSIZER20hTrim region size in sectors
  • 0h = Minimum value of [TRIMSIZE]
  • 20h = Maximum value of [TRIMSIZE]
7-0NONMAINSIZER20hNon-main region size in sectors
  • 0h = Minimum value of [NONMAINSIZE]
  • 20h = Maximum value of [NONMAINSIZE]

6.6.78 BANK4INFO0 (Offset = 1440h) [Reset = 00000000h]

BANK4INFO0 is shown in Figure 6-81 and described in Table 6-91.

Return to the Summary Table.

Bank Info 0 Register for bank 4. Read only register detailing information about Main region size in the bank.

Figure 6-81 BANK4INFO0
313029282726252423222120191817161514131211109876543210
RESERVEDMAINSIZE
R-0hR-0h
Table 6-91 BANK4INFO0 Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0hReserved
11-0MAINSIZER200hMain region size in sectors
  • 8h = Minimum value of [MAINSIZE]
  • 200h = Maximum value of [MAINSIZE]

6.6.79 BANK4INFO1 (Offset = 1444h) [Reset = 00000000h]

BANK4INFO1 is shown in Figure 6-82 and described in Table 6-92.

Return to the Summary Table.

Bank Info1 Register for bank 4. Read only register detailing information about Non-Main, Trim, and Engr region sizes in the bank.

Figure 6-82 BANK4INFO1
31302928272625242322212019181716
RESERVEDENGRSIZE
R-0hR-0h
1514131211109876543210
TRIMSIZENONMAINSIZE
R-0hR-0h
Table 6-92 BANK4INFO1 Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0hReserved
23-16ENGRSIZER10hEngr region size in sectors
  • 0h = Minimum value of [ENGRSIZE]
  • 20h = Maximum value of [ENGRSIZE]
15-8TRIMSIZER10hTrim region size in sectors
  • 0h = Minimum value of [TRIMSIZE]
  • 20h = Maximum value of [TRIMSIZE]
7-0NONMAINSIZER20hNon-main region size in sectors
  • 0h = Minimum value of [NONMAINSIZE]
  • 20h = Maximum value of [NONMAINSIZE]