SLAU847F October   2022  – March 2026 MSPM0L1105 , MSPM0L1106 , MSPM0L1116 , MSPM0L1117 , MSPM0L1227 , MSPM0L1227-Q1 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346 , MSPM0L2116 , MSPM0L2117 , MSPM0L2227 , MSPM0L2227-Q1 , MSPM0L2228 , MSPM0L2228-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation
    5.     Support Resources
    6.     Trademarks
  3. 1 Architecture
    1. 1.1 Architecture Overview
    2. 1.2 Bus Organization
    3. 1.3 Platform Memory Map
      1. 1.3.1 Code Region
      2. 1.3.2 SRAM Region
      3. 1.3.3 Peripheral Region
      4. 1.3.4 Subsystem Region
      5. 1.3.5 System PPB Region
    4. 1.4 Boot Configuration
      1. 1.4.1 Configuration Memory (NONMAIN)
        1. 1.4.1.1 CRC-Backed Configuration Data
        2. 1.4.1.2 16-bit Pattern Match for Critical Fields
      2. 1.4.2 Boot Configuration Routine (BCR)
        1. 1.4.2.1 Serial Wire Debug Related Policies
          1. 1.4.2.1.1 SWD Security Level 0
          2. 1.4.2.1.2 SWD Security Level 1
          3. 1.4.2.1.3 SWD Security Level 2
        2. 1.4.2.2 SWD Mass Erase and Factory Reset Commands
        3. 1.4.2.3 Flash Memory Protection and Integrity Related Policies
          1. 1.4.2.3.1 Locking the Application (MAIN) Flash Memory
          2. 1.4.2.3.2 Locking the Configuration (NONMAIN) Flash Memory
          3. 1.4.2.3.3 Static Write Protection NONMAIN Fields
        4. 1.4.2.4 Application CRC Verification
        5. 1.4.2.5 Fast Boot
        6. 1.4.2.6 Bootstrap Loader (BSL) Enable/Disable Policy
          1. 1.4.2.6.1 BSL Enable
      3. 1.4.3 Bootstrap Loader (BSL)
        1. 1.4.3.1 GPIO Invoke
        2. 1.4.3.2 Bootstrap Loader (BSL) Security Policies
          1. 1.4.3.2.1 BSL Access Password
          2. 1.4.3.2.2 BSL Read-out Policy
          3. 1.4.3.2.3 BSL Security Alert Policy
        3. 1.4.3.3 Application Version
        4. 1.4.3.4 BSL Triggered Mass Erase and Factory Reset
      4. 1.4.4 NONMAIN Layout Types
      5. 1.4.5 NONMAIN_TYPEA Registers
      6. 1.4.6 NONMAIN_TYPEC Registers
      7. 1.4.7 NONMAIN_TYPEE Registers
    5. 1.5 Factory Constants
      1. 1.5.1 FACTORYREGION Layout Types
      2. 1.5.2 FACTORYREGION_TYPEA Registers
      3. 1.5.3 FACTORYREGION_TYPEC Registers
      4. 1.5.4 FACTORYREGION_TYPED Registers
      5. 1.5.5 FACTORYREGION_TYPEE Registers
  4. 2 PMCU
    1. 2.1 PMCU Overview
      1. 2.1.1 Power Domains
      2. 2.1.2 Operating Modes
        1. 2.1.2.1 RUN Mode
        2. 2.1.2.2 SLEEP Mode
        3. 2.1.2.3 STOP Mode
        4. 2.1.2.4 STANDBY Mode
        5. 2.1.2.5 SHUTDOWN Mode
        6. 2.1.2.6 Supported Functionality by Operating Mode
        7. 2.1.2.7 Suspended Low-Power Mode Operation
    2. 2.2 Power Management (PMU)
      1. 2.2.1 Power Supply
      2. 2.2.2 Core Regulator
      3. 2.2.3 Supply Supervisors
        1. 2.2.3.1 Power-on Reset (POR)
        2. 2.2.3.2 Brownout Reset (BOR)
        3. 2.2.3.3 POR and BOR Behavior During Supply Changes
      4. 2.2.4 Bandgap Reference
      5. 2.2.5 VBOOST for Analog Muxes
      6. 2.2.6 Peripheral Enable
        1. 2.2.6.1 Automatic Peripheral Disable in Low Power Modes
    3. 2.3 Clock Module (CKM)
      1. 2.3.1 Oscillators
        1. 2.3.1.1 Internal Low-Frequency Oscillator (LFOSC)
        2. 2.3.1.2 Internal System Oscillator (SYSOSC)
          1. 2.3.1.2.1 SYSOSC Gear Shift
          2. 2.3.1.2.2 SYSOSC Frequency
          3. 2.3.1.2.3 SYSOSC Frequency Correction Loop
            1. 2.3.1.2.3.1 SYSOSC FCL in External Resistor Mode (ROSC)
            2. 2.3.1.2.3.2 SYSOSC FCL in Internal Resistor Mode
          4. 2.3.1.2.4 SYSOSC User Trim Procedure
          5. 2.3.1.2.5 Disabling SYSOSC
        3. 2.3.1.3 Low Frequency Crystal Oscillator (LFXT)
        4. 2.3.1.4 LFCLK_IN (Digital Clock)
        5. 2.3.1.5 High Frequency Crystal Oscillator (HFXT)
        6. 2.3.1.6 HFCLK_IN (Digital clock)
      2. 2.3.2 Clocks
        1. 2.3.2.1  MCLK (Main Clock) Tree
        2. 2.3.2.2  CPUCLK (Processor Clock)
        3. 2.3.2.3  ULPCLK (Low-Power Clock)
        4. 2.3.2.4  MFCLK (Middle Frequency Clock)
        5. 2.3.2.5  MFPCLK (Middle Frequency Precision Clock)
        6. 2.3.2.6  LFCLK (Low-Frequency Clock)
        7. 2.3.2.7  HFCLK (High-Frequency External Clock)
        8. 2.3.2.8  HSCLK (High Speed Clock)
        9. 2.3.2.9  ADCCLK (ADC Sample Period Clock)
        10. 2.3.2.10 CANCLK (CAN-FD Functional Clock)
        11. 2.3.2.11 RTCCLK (RTC Clock)
        12. 2.3.2.12 External Clock Output (CLK_OUT)
        13. 2.3.2.13 Direct Clock Connections for Infrastructure
      3. 2.3.3 Clock Tree
        1. 2.3.3.1 Peripheral Clock Source Selection
      4. 2.3.4 Clock Monitors
        1. 2.3.4.1 LFCLK Monitor
        2. 2.3.4.2 MCLK Monitor
        3. 2.3.4.3 Startup Monitors
          1. 2.3.4.3.1 LFOSC Startup Monitor
          2. 2.3.4.3.2 LFXT Startup Monitor
          3. 2.3.4.3.3 HFCLK Startup Monitor
          4. 2.3.4.3.4 HSCLK Status
      5. 2.3.5 Frequency Clock Counter (FCC)
        1. 2.3.5.1 Using the FCC
        2. 2.3.5.2 FCC Frequency Computation and Accuracy
    4. 2.4 System Controller (SYSCTL)
      1. 2.4.1  Resets and Device Initialization
        1. 2.4.1.1 Reset Levels
          1. 2.4.1.1.1 Power-on Reset (POR) Reset Level
          2. 2.4.1.1.2 Brownout Reset (BOR) Reset Level
          3. 2.4.1.1.3 Boot Reset (BOOTRST) Reset Level
          4. 2.4.1.1.4 System Reset (SYSRST) Reset Level
          5. 2.4.1.1.5 CPU-only Reset (CPURST) Reset Level
        2. 2.4.1.2 Initial Conditions After Power-Up
        3. 2.4.1.3 NRST Pin
        4. 2.4.1.4 SWD Pins
        5. 2.4.1.5 Generating Resets in Software
        6. 2.4.1.6 Reset Cause
        7. 2.4.1.7 Peripheral Reset Control
        8. 2.4.1.8 Boot Fail Handling
      2. 2.4.2  Operating Mode Selection
      3. 2.4.3  Asynchronous Fast Clock Requests
      4. 2.4.4  SRAM Write Protection
      5. 2.4.5  Flash Wait States
      6. 2.4.6  Flash Bank Address Swap
      7. 2.4.7  Shutdown Mode Handling (if present)
      8. 2.4.8  Configuration Lockout
      9. 2.4.9  System Status
      10. 2.4.10 Error Handling
      11. 2.4.11 SYSCTL Events
        1. 2.4.11.1 CPU Interrupt Event (CPU_INT)
        2. 2.4.11.2 Nonmaskable Interrupt Event (NMI)
    5. 2.5 SYSCTL Layout Types
    6. 2.6 SYSCTL_TYPEA Registers
    7. 2.7 SYSCTL_TYPEB Registers
    8. 2.8 SYSCTL_TYPEC Registers
    9. 2.9 Quick Start Reference
      1. 2.9.1 Default Device Configuration
      2. 2.9.2 Leveraging MFCLK
      3. 2.9.3 Optimizing Power Consumption in STOP Mode
      4. 2.9.4 Optimizing Power Consumption in STANDBY Mode
      5. 2.9.5 Increasing MCLK Precision
      6. 2.9.6 High Speed Clock (SYSPLL, HFCLK) Handling in Low-Power Modes
      7. 2.9.7 Optimizing for Lowest Wakeup Latency
      8. 2.9.8 Optimizing for Lowest Peak Current in RUN/SLEEP Mode
  5. 3 CPU
    1. 3.1 Overview
    2. 3.2 Arm Cortex-M0+ CPU
      1. 3.2.1 CPU Register File
      2. 3.2.2 Stack Behavior
      3. 3.2.3 Execution Modes and Privilege Levels
      4. 3.2.4 Address Space and Supported Data Sizes
    3. 3.3 Interrupts and Exceptions
      1. 3.3.1 Peripheral Interrupts (IRQs)
        1. 3.3.1.1 Nested Vectored Interrupt Controller (NVIC)
        2. 3.3.1.2 Interrupt Groups
        3. 3.3.1.3 Wake Up Controller (WUC)
      2. 3.3.2 Interrupt and Exception Table
      3. 3.3.3 Processor Lockup Scenario
    4. 3.4 CPU Peripherals
      1. 3.4.1 System Control Block (SCB)
      2. 3.4.2 System Tick Timer (SysTick)
    5. 3.5 Read-Only Memory (ROM)
    6. 3.6 CPUSS Registers
    7. 3.7 WUC Registers
  6. 4 SECURITY
    1. 4.1 Overview
      1. 4.1.1 Secure Boot
      2. 4.1.2 Customer Secure Code (CSC)
    2. 4.2 Boot and Startup Sequence
      1. 4.2.1 CSC Programming Overview
    3. 4.3 Secure Key Storage
    4. 4.4 Flash Memory Protection
      1. 4.4.1 Bank Swapping
      2. 4.4.2 Write Protection
      3. 4.4.3 Read-Execute Protection
      4. 4.4.4 IP Protection
      5. 4.4.5 Data Bank Protection
      6. 4.4.6 Hardware Monotonic Counter
    5. 4.5 SRAM Protection
    6. 4.6 SECURITY Registers
  7. 5 Direct Memory Access (DMA)
    1. 5.1 DMA Overview
    2. 5.2 DMA Operation
      1. 5.2.1  Addressing Modes
      2. 5.2.2  Channel Types
      3. 5.2.3  Transfer Modes
        1. 5.2.3.1 Single Transfer
        2. 5.2.3.2 Block Transfer
        3. 5.2.3.3 Repeated Single Transfer
        4. 5.2.3.4 Repeated Block Transfer
        5. 5.2.3.5 Stride Mode
      4. 5.2.4  Extended Modes
        1. 5.2.4.1 Fill Mode
        2. 5.2.4.2 Table Mode
      5. 5.2.5  Initiating DMA Transfers
      6. 5.2.6  Stopping DMA Transfers
      7. 5.2.7  Channel Priorities
      8. 5.2.8  Burst Block Mode
      9. 5.2.9  Using DMA with System Interrupts
      10. 5.2.10 DMA Controller Interrupts
      11. 5.2.11 DMA Trigger Event Status
      12. 5.2.12 DMA Operating Mode Support
        1. 5.2.12.1 Transfer in RUN Mode
        2. 5.2.12.2 Transfer in SLEEP Mode
        3. 5.2.12.3 Transfer in STOP Mode
        4. 5.2.12.4 Transfers in STANDBY Mode
      13. 5.2.13 DMA Address and Data Errors
      14. 5.2.14 Interrupt and Event Support
    3. 5.3 DMA Registers
  8. 6 NVM (Flash)
    1. 6.1 NVM Overview
      1. 6.1.1 Key Features
      2. 6.1.2 System Components
      3. 6.1.3 Terminology
    2. 6.2 Flash Memory Bank Organization
      1. 6.2.1 Banks
      2. 6.2.2 Flash Memory Regions
      3. 6.2.3 Addressing
        1. 6.2.3.1 Flash Memory Map
      4. 6.2.4 Memory Organization Examples
    3. 6.3 Flash Controller
      1. 6.3.1 Overview of Flash Controller Commands
      2. 6.3.2 NOOP Command
      3. 6.3.3 PROGRAM Command
        1. 6.3.3.1 Program Bit Masking Behavior
        2. 6.3.3.2 Programming Less Than One Flash Word
        3. 6.3.3.3 Target Data Alignment (Devices with Single Flash Word Programming Only)
        4. 6.3.3.4 Target Data Alignment (Devices With Multiword Programming)
        5. 6.3.3.5 Executing a PROGRAM Operation
      4. 6.3.4 ERASE Command
        1. 6.3.4.1 Erase Sector Masking Behavior
        2. 6.3.4.2 Executing an ERASE Operation
      5. 6.3.5 READVERIFY Command
        1. 6.3.5.1 Executing a READVERIFY Operation
      6. 6.3.6 BLANKVERIFY Command
        1. 6.3.6.1 Executing a BLANKVERIFY Operation
      7. 6.3.7 Command Diagnostics
        1. 6.3.7.1 Command Status
        2. 6.3.7.2 Address Translation
        3. 6.3.7.3 Pulse Counts
      8. 6.3.8 Overriding the System Address With a Bank ID, Region ID, and Bank Address
      9. 6.3.9 FLASHCTL Events
        1. 6.3.9.1 CPU Interrupt Event Publisher
    4. 6.4 Write Protection
      1. 6.4.1 Write Protection Resolution
      2. 6.4.2 Static Write Protection
      3. 6.4.3 Dynamic Write Protection
        1. 6.4.3.1 Configuring Protection for the MAIN Region
        2. 6.4.3.2 Configuring Protection for the NONMAIN Region
    5. 6.5 Read Interface
      1. 6.5.1 Bank Address Swapping
    6. 6.6 FLASHCTL Registers
  9. 7 Events
    1. 7.1 Events Overview
      1. 7.1.1 Event Publisher
      2. 7.1.2 Event Subscriber
      3. 7.1.3 Event Fabric Routing
        1. 7.1.3.1 CPU Interrupt Event Route (CPU_INT)
        2. 7.1.3.2 DMA Trigger Event Route (DMA_TRIGx)
        3. 7.1.3.3 Generic Event Route (GEN_EVENTx)
      4. 7.1.4 Event Routing Map
      5. 7.1.5 Event Propagation Latency
    2. 7.2 Events Operation
      1. 7.2.1 CPU Interrupt
      2. 7.2.2 DMA Trigger
      3. 7.2.3 Peripheral to Peripheral Event
      4. 7.2.4 Extended Module Description Register
      5. 7.2.5 Using Event Registers
        1. 7.2.5.1 Event Registers
        2. 7.2.5.2 Configuring Events
        3. 7.2.5.3 Responding to CPU Interrupts in Application Software
        4. 7.2.5.4 Hardware Event Handling
  10. 8 IOMUX
    1. 8.1 IOMUX Overview
      1. 8.1.1 IO Types and Analog Sharing
    2. 8.2 IOMUX Operation
      1. 8.2.1 Peripheral Function (PF) Assignment
      2. 8.2.2 Logic High to Hi-Z Conversion
      3. 8.2.3 Logic Inversion
      4. 8.2.4 SHUTDOWN Mode Wakeup Logic
      5. 8.2.5 Pullup/Pulldown Resistors
      6. 8.2.6 Drive Strength Control
      7. 8.2.7 Hysteresis and Logic Level Control
    3. 8.3 IOMUX Registers
  11. 9 General-Purpose Input/Output (GPIO)
    1. 9.1 GPIO Overview
    2. 9.2 GPIO Operation
      1. 9.2.1 GPIO Ports
      2. 9.2.2 GPIO Read/Write Interface
      3. 9.2.3 GPIO Input Glitch Filtering and Synchronization
      4. 9.2.4 GPIO Fast Wake
      5. 9.2.5 GPIO DMA Interface
      6. 9.2.6 Event Publishers and Subscribers
    3. 9.3 GPIO Registers
  12. 10AES
    1. 10.1 AES Overview
      1. 10.1.1 AESADV Performance
    2. 10.2 AESADV Operation
      1. 10.2.1 Loading the Key
      2. 10.2.2 Writing Input Data
      3. 10.2.3 Reading Output Data
      4. 10.2.4 Operation Descriptions
        1. 10.2.4.1 Single Block Operation
        2. 10.2.4.2 Electronic Codebook (ECB) Mode
          1. 10.2.4.2.1 ECB Encryption
          2. 10.2.4.2.2 ECB Decryption
        3. 10.2.4.3 Cipher Block Chaining (CBC) Mode
          1. 10.2.4.3.1 CBC Encryption
          2. 10.2.4.3.2 CBC Decryption
        4. 10.2.4.4 Output Feedback (OFB) Mode
          1. 10.2.4.4.1 OFB Encryption
          2. 10.2.4.4.2 OFB Decryption
        5. 10.2.4.5 Cipher Feedback (CFB) Mode
          1. 10.2.4.5.1 CFB Encryption
          2. 10.2.4.5.2 CFB Decryption
        6. 10.2.4.6 Counter (CTR) Mode
          1. 10.2.4.6.1 CTR Encryption
          2. 10.2.4.6.2 CTR Decryption
        7. 10.2.4.7 Galois Counter (GCM) Mode
          1. 10.2.4.7.1 GHASH Operation
          2. 10.2.4.7.2 GCM Operating Modes
            1. 10.2.4.7.2.1 Autonomous GCM Operation
              1. 10.2.4.7.2.1.1 GMAC
            2. 10.2.4.7.2.2 GCM With Pre-Calculations
            3. 10.2.4.7.2.3 GCM Operation With Precalculated H- and Y0-Encrypted Forced to Zero
        8. 10.2.4.8 Counter With Cipher Block Chaining Message Authentication Code (CCM)
          1. 10.2.4.8.1 CCM Operation
      5. 10.2.5 AES Events
        1. 10.2.5.1 CPU Interrupt Event Publisher (CPU_EVENT)
        2. 10.2.5.2 DMA Trigger Event Publisher (DMA_TRIG_DATAIN)
        3. 10.2.5.3 DMA Trigger Event Publisher (DMA_TRIG_DATAOUT)
    3. 10.3 AESADV Registers
  13. 11CRC
    1. 11.1 CRC Overview
      1. 11.1.1 CRC16-CCITT
      2. 11.1.2 CRC32-ISO3309
    2. 11.2 CRC Operation
      1. 11.2.1 CRC Generator Implementation
      2. 11.2.2 Configuration
        1. 11.2.2.1 Polynomial Selection
        2. 11.2.2.2 Bit Order
        3. 11.2.2.3 Byte Swap
        4. 11.2.2.4 Byte Order
        5. 11.2.2.5 CRC C Library Compatibility
    3. 11.3 CRCP0 Registers
  14. 12Keystore
    1. 12.1 Overview
    2. 12.2 Detailed Description
    3. 12.3 KEYSTORECTL Registers
  15. 13TRNG
    1. 13.1 TRNG Overview
    2. 13.2 TRNG Operation
      1. 13.2.1 TRNG Generation Data Path
      2. 13.2.2 Clock Configuration and Output Rate
      3. 13.2.3 Behavior in Low Power Modes
      4. 13.2.4 Health Tests
        1. 13.2.4.1 Digital Block Startup Self-Test
        2. 13.2.4.2 Analog Block Startup Self-Test
        3. 13.2.4.3 Runtime Health Test
          1. 13.2.4.3.1 Repetition Count Test
          2. 13.2.4.3.2 Adaptive Proportion Test
          3. 13.2.4.3.3 Handling Runtime Health Test Failures
      5. 13.2.5 Configuration
        1. 13.2.5.1 TRNG State Machine
          1. 13.2.5.1.1 Changing TRNG States
        2. 13.2.5.2 Using the TRNG
        3. 13.2.5.3 TRNG Events
          1. 13.2.5.3.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 13.3 TRNG Registers
  16. 14Temperature Sensor
  17. 15ADC
    1. 15.1 ADC Overview
    2. 15.2 ADC Operation
      1. 15.2.1  ADC Core
      2. 15.2.2  Voltage Reference Options
      3. 15.2.3  Generic Resolution Modes
      4. 15.2.4  Hardware Averaging
      5. 15.2.5  ADC Clocking
      6. 15.2.6  Common ADC Use Cases
      7. 15.2.7  Power Down Behavior
      8. 15.2.8  Sampling Trigger Sources and Sampling Modes
        1. 15.2.8.1 AUTO Sampling Mode
        2. 15.2.8.2 MANUAL Sampling Mode
      9. 15.2.9  Sampling Period
      10. 15.2.10 Conversion Modes
      11. 15.2.11 Data Format
      12. 15.2.12 Advanced Features
        1. 15.2.12.1 Window Comparator
        2. 15.2.12.2 DMA and FIFO Operation
        3. 15.2.12.3 Analog Peripheral Interconnection
      13. 15.2.13 Status Register
      14. 15.2.14 ADC Events
        1. 15.2.14.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 15.2.14.2 Generic Event Publisher (GEN_EVENT)
        3. 15.2.14.3 DMA Trigger Event Publisher (DMA_TRIG)
        4. 15.2.14.4 Generic Event Subscriber (FSUB_0)
    3. 15.3 ADC12 Registers
  18. 16COMP
    1. 16.1 Comparator Overview
    2. 16.2 Comparator Operation
      1. 16.2.1  Comparator Configuration
      2. 16.2.2  Comparator Channels Selection
      3. 16.2.3  Comparator Output
      4. 16.2.4  Output Filter
      5. 16.2.5  Sampled Output Mode
      6. 16.2.6  Blanking Mode
      7. 16.2.7  Reference Voltage Generator
      8. 16.2.8  Comparator Hysteresis
      9. 16.2.9  Input SHORT Switch
      10. 16.2.10 Interrupt and Events Support
        1. 16.2.10.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 16.2.10.2 Generic Event Publisher (GEN_EVENT)
        3. 16.2.10.3 Generic Event Subscribers
    3. 16.3 COMP0 Registers
  19. 17OPA
    1. 17.1 OPA Overview
    2. 17.2 OPA Operation
      1. 17.2.1 Analog Core
      2. 17.2.2 Power Up Behavior
      3. 17.2.3 Inputs
      4. 17.2.4 Output
      5. 17.2.5 Clock Requirements
      6. 17.2.6 Chopping
      7. 17.2.7 OPA Amplifier Modes
        1. 17.2.7.1 General-Purpose Mode
        2. 17.2.7.2 Buffer Mode
        3. 17.2.7.3 OPA PGA Mode
          1. 17.2.7.3.1 Inverting PGA Mode
          2. 17.2.7.3.2 Non-inverting PGA Mode
        4. 17.2.7.4 Difference Amplifier Mode
        5. 17.2.7.5 Cascade Amplifier Mode
      8. 17.2.8 OPA Configuration Selection
      9. 17.2.9 Burnout Current Source
    3. 17.3 OA Registers
  20. 18GPAMP
    1. 18.1 GPAMP Overview
    2. 18.2 GPAMP Operation
      1. 18.2.1 Analog Core
      2. 18.2.2 Power Up Behavior
      3. 18.2.3 Inputs
      4. 18.2.4 Output
      5. 18.2.5 GPAMP Amplifier Modes
        1. 18.2.5.1 General-Purpose Mode
        2. 18.2.5.2 ADC Buffer Mode
        3. 18.2.5.3 Unity Gain Mode
      6. 18.2.6 Chopping
    3. 18.3 GPAMP Registers
  21. 19VREF
    1. 19.1 VREF Overview
    2. 19.2 VREF Operation
      1. 19.2.1 Internal Reference Generation
      2. 19.2.2 External Reference Input
      3. 19.2.3 Analog Peripheral Interface
    3. 19.3 VREF Registers
  22. 20LCD
    1. 20.1 LCD Introduction
      1. 20.1.1 LCD Operating Principle
      2. 20.1.2 Static Mode
      3. 20.1.3 2-Mux Mode
      4. 20.1.4 3-Mux Mode
      5. 20.1.5 4-Mux Mode
      6. 20.1.6 6-Mux Mode
      7. 20.1.7 8-Mux Mode
      8. 20.1.8 Introduction
      9. 20.1.9 LCD Waveforms
    2. 20.2 LCD Clocking
    3. 20.3 Voltage Generation
      1. 20.3.1  Mode 0 - Voltage Generation from external reference and external resistor divider
      2. 20.3.2  Mode 1 - Voltage Generation from AVDD and external resistor divider
      3. 20.3.3  Mode 2 - Voltage Generation from external reference and internal resistor divider
      4. 20.3.4  Mode 3 - Voltage Generation From AVDD and Internal Resistor Ladder
      5. 20.3.5  Mode 4 - Voltage Generation from charge pump with external supply
      6. 20.3.6  Mode 5 - Voltage Generation From Charge Pump With AVDD
      7. 20.3.7  Mode 6 - Voltage Generation From Charge Pump With External Reference on R13
      8. 20.3.8  Mode 7 - Voltage Generation From Charge Pump With Internal Reference on R13
      9. 20.3.9  Charge pump
      10. 20.3.10 Internal Reference Generation
    4. 20.4 Analog Mux
      1. 20.4.1 Static Mode
      2. 20.4.2 Non-Static 1/3 bias mode
      3. 20.4.3 Non-Static 1/4 bias mode
      4. 20.4.4 Low power mode switch controls
    5. 20.5 LCD Memory and output drive
      1. 20.5.1 LCD Memory organization
        1. 20.5.1.1 Memory Organization in Mux-1 to Mux-4 Modes
        2. 20.5.1.2 Memory Organization in Mux-5 to Mux-8 Modes
        3. 20.5.1.3 Configuring memory
        4. 20.5.1.4 Accessing memory and output drive
        5. 20.5.1.5 Blinking Override
    6. 20.6 IO Muxing
    7. 20.7 Interrupt Generation
    8. 20.8 Power Domains and Power Modes
    9. 20.9 LCD Registers
  23. 21UART
    1. 21.1 UART Overview
      1. 21.1.1 Purpose of the Peripheral
      2. 21.1.2 Features
      3. 21.1.3 Functional Block Diagram
    2. 21.2 UART Operation
      1. 21.2.1 Clock Control
      2. 21.2.2 Signal Descriptions
      3. 21.2.3 General Architecture and Protocol
        1. 21.2.3.1  Transmit Receive Logic
        2. 21.2.3.2  Bit Sampling
        3. 21.2.3.3  Majority Voting Feature
        4. 21.2.3.4  Baud Rate Generation
        5. 21.2.3.5  Data Transmission
        6. 21.2.3.6  Error and Status
        7. 21.2.3.7  Local Interconnect Network (LIN) Support
          1. 21.2.3.7.1 LIN Responder Transmission Delay
        8. 21.2.3.8  Flow Control
        9. 21.2.3.9  Idle-Line Multiprocessor
        10. 21.2.3.10 9-Bit UART Mode
        11. 21.2.3.11 RS-485 Support
        12. 21.2.3.12 DALI Protocol
        13. 21.2.3.13 Manchester Encoding and Decoding
        14. 21.2.3.14 IrDA Encoding and Decoding
        15. 21.2.3.15 ISO7816 Smart Card Support
        16. 21.2.3.16 Address Detection
        17. 21.2.3.17 FIFO Operation
        18. 21.2.3.18 Loopback Operation
        19. 21.2.3.19 Glitch Suppression
      4. 21.2.4 Low Power Operation
      5. 21.2.5 Reset Considerations
      6. 21.2.6 Initialization
      7. 21.2.7 Interrupt and Events Support
        1. 21.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 21.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 21.2.8 Emulation Modes
    3. 21.3 UART Registers
  24. 22I2C
    1. 22.1 I2C Overview
      1. 22.1.1 Purpose of the Peripheral
      2. 22.1.2 Features
      3. 22.1.3 Functional Block Diagram
      4. 22.1.4 Environment and External Connections
    2. 22.2 I2C Operation
      1. 22.2.1 Clock Control
        1. 22.2.1.1 Clock Select and I2C Speed
        2. 22.2.1.2 Clock Startup
      2. 22.2.2 Signal Descriptions
      3. 22.2.3 General Architecture
        1. 22.2.3.1  I2C Bus Functional Overview
        2. 22.2.3.2  START and STOP Conditions
        3. 22.2.3.3  Data Format with 7-Bit Address
        4. 22.2.3.4  Acknowledge
        5. 22.2.3.5  Repeated Start
        6. 22.2.3.6  SCL Clock Low Timeout
        7. 22.2.3.7  Clock Stretching
        8. 22.2.3.8  Dual Address
        9. 22.2.3.9  Arbitration
        10. 22.2.3.10 Multiple Controller Mode
        11. 22.2.3.11 Glitch Suppression
        12. 22.2.3.12 FIFO operation
          1. 22.2.3.12.1 Flushing Stale Tx Data in Target Mode
        13. 22.2.3.13 Loopback mode
        14. 22.2.3.14 Burst Mode
        15. 22.2.3.15 DMA Operation
        16. 22.2.3.16 Low-Power Operation
      4. 22.2.4 Protocol Descriptions
        1. 22.2.4.1 I2C Controller Mode
          1. 22.2.4.1.1 Controller Configuration
          2. 22.2.4.1.2 Controller Mode Operation
          3. 22.2.4.1.3 Read On TX Empty
        2. 22.2.4.2 I2C Target Mode
          1. 22.2.4.2.1 Target Mode Operation
      5. 22.2.5 Reset Considerations
      6. 22.2.6 Initialization
      7. 22.2.7 Interrupt and Events Support
        1. 22.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 22.2.7.2 DMA Trigger Publisher (DMA_TRIG1, DMA_TRIG0)
      8. 22.2.8 Emulation Modes
    3. 22.3 I2C Registers
  25. 23SPI
    1. 23.1 SPI Overview
      1. 23.1.1 Purpose of the Peripheral
      2. 23.1.2 Features
      3. 23.1.3 Functional Block Diagram
      4. 23.1.4 External Connections and Signal Descriptions
    2. 23.2 SPI Operation
      1. 23.2.1 Clock Control
      2. 23.2.2 General Architecture
        1. 23.2.2.1 Chip Select and Command Handling
          1. 23.2.2.1.1 Chip Select Control
          2. 23.2.2.1.2 Command Data Control
        2. 23.2.2.2 Data Format
        3. 23.2.2.3 Delayed data sampling
        4. 23.2.2.4 Clock Generation
        5. 23.2.2.5 FIFO Operation
        6. 23.2.2.6 Loopback mode
        7. 23.2.2.7 DMA Operation
        8. 23.2.2.8 Repeat Transfer mode
        9. 23.2.2.9 Low Power Mode
      3. 23.2.3 Protocol Descriptions
        1. 23.2.3.1 Motorola SPI Frame Format
        2. 23.2.3.2 Texas Instruments Synchronous Serial Frame Format
      4. 23.2.4 Reset Considerations
      5. 23.2.5 Initialization
      6. 23.2.6 Interrupt and Events Support
        1. 23.2.6.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 23.2.6.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      7. 23.2.7 Emulation Modes
    3. 23.3 SPI Registers
  26. 24UNICOMM
    1. 24.1 Overview
      1. 24.1.1 Block Diagram
    2. 24.2 Unicomm Architecture
      1. 24.2.1 Serial Peripheral Group (SPG) Configurations
        1. 24.2.1.1 I2C Pairings
      2. 24.2.2 Enables & Resets
    3. 24.3 High-Level Initialization
    4. 24.4 UNICOMM/SPGSS Registers
      1. 24.4.1 UNICOMM Registers
        1. 24.4.1.1 UNICOMM Registers
      2. 24.4.2 SPG Registers
        1. 24.4.2.1 SPGSS Registers
  27. 25UNICOMM UART
    1. 25.1 UART Overview
      1. 25.1.1 Purpose of the Peripheral
      2. 25.1.2 Features
      3. 25.1.3 Functional Block Diagram
    2. 25.2 UART Operation
      1. 25.2.1 Clock Control
      2. 25.2.2 General Architecture and Protocol
        1. 25.2.2.1 Signal Descriptions
        2. 25.2.2.2 Transmit and Receive Logic
        3. 25.2.2.3 Bit Sampling
        4. 25.2.2.4 Baud Rate Generation
        5. 25.2.2.5 Data Transmission
        6. 25.2.2.6 Error and Status
        7. 25.2.2.7 DMA Operation
        8. 25.2.2.8 Internal Loopback Operation
      3. 25.2.3 Additional Protocol and Feature Support
        1. 25.2.3.1  Local Interconnect Network (LIN) Support
          1. 25.2.3.1.1 LIN Commander Transmit
          2. 25.2.3.1.2 LIN Responder Receive
          3. 25.2.3.1.3 LIN Responder Transmission Delay
        2. 25.2.3.2  Flow Control
        3. 25.2.3.3  RS485 Support
        4. 25.2.3.4  FIFO Operation
        5. 25.2.3.5  Idle-Line Multiprocessor
        6. 25.2.3.6  9-Bit UART Mode
        7. 25.2.3.7  DALI Protocol
        8. 25.2.3.8  Manchester Encoding and Decoding
        9. 25.2.3.9  IrDA Encoding and Decoding
        10. 25.2.3.10 ISO7816 Smart Card Support
        11. 25.2.3.11 Address Detection
        12. 25.2.3.12 Glitch Suppression
      4. 25.2.4 Low Power Operation
      5. 25.2.5 Reset Considerations
      6. 25.2.6 UART Initialization
      7. 25.2.7 Interrupt and Events Support
        1. 25.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 25.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 25.2.8 Emulation Modes
    3. 25.3 UNICOMMUART Registers
  28. 26UNICOMM-I2C
    1. 26.1 UNICOMM-I2C Overview
      1. 26.1.1 Purpose of the Peripheral
      2. 26.1.2 Features
      3. 26.1.3 Functional Block Diagram
      4. 26.1.4 Environment and External Connections
    2. 26.2 UNICOMM Common Infrastructure
    3. 26.3 Peripheral Functional Description
      1. 26.3.1 Clock Control
        1. 26.3.1.1 Clock Select and I2C Speed
        2. 26.3.1.2 Clock Startup
      2. 26.3.2 Signal Descriptions
      3. 26.3.3 General Architecture
        1. 26.3.3.1  I2C Bus Functional Overview
        2. 26.3.3.2  START and STOP Conditions
        3. 26.3.3.3  Dual Address
        4. 26.3.3.4  Address Format
          1. 26.3.3.4.1 Data Format with 7-Bit Address
          2. 26.3.3.4.2 Data Format with 10-Bit Address
        5. 26.3.3.5  Acknowledge
        6. 26.3.3.6  Repeated Start
        7. 26.3.3.7  Clock Stretching
        8. 26.3.3.8  Clock Low Timeout
        9. 26.3.3.9  Burst Mode
        10. 26.3.3.10 Arbitration
        11. 26.3.3.11 Multiple Controller Mode
        12. 26.3.3.12 Glitch Suppression
        13. 26.3.3.13 DMA Operation
        14. 26.3.3.14 FIFO Operation
          1. 26.3.3.14.1 FIFO Status Flags
          2. 26.3.3.14.2 FIFO Levels
          3. 26.3.3.14.3 Clearing FIFO Contents
        15. 26.3.3.15 Suspend Communication
        16. 26.3.3.16 Low Power Operation
        17. 26.3.3.17 SMBUS 3.0 Support
          1. 26.3.3.17.1 Quick Command
          2. 26.3.3.17.2 SMBUS Enhanced Acknowledge Control
          3. 26.3.3.17.3 Clock Low Timeout Detection
          4. 26.3.3.17.4 Clock High Timeout Detection
          5. 26.3.3.17.5 Cumulative Clock Low Extended Timeout
          6. 26.3.3.17.6 Packet Error Checking (PEC)
          7. 26.3.3.17.7 Host Notify Protocol
          8. 26.3.3.17.8 Alert Response Protocol
          9. 26.3.3.17.9 Address Resolution Protocol
      4. 26.3.4 Protocol Descriptions & Initialization
        1. 26.3.4.1 I2C Controller Mode
          1. 26.3.4.1.1 I2C Controller Initialization
          2. 26.3.4.1.2 I2C Controller Status
          3. 26.3.4.1.3 I2C Controller Receive Mode
          4. 26.3.4.1.4 I2C Controller Transmitter Mode
          5. 26.3.4.1.5 Controller Transaction Configurations
        2. 26.3.4.2 I2C Target Mode
          1. 26.3.4.2.1 I2C Target Initialization
          2. 26.3.4.2.2 I2C Target Status
          3. 26.3.4.2.3 I2C Target Receiver Mode
          4. 26.3.4.2.4 I2C Target Transmitter Mode
      5. 26.3.5 Reset Considerations
      6. 26.3.6 Initialization
      7. 26.3.7 Interrupt and Events Support
        1. 26.3.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 26.3.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 26.3.8 Emulation Modes
    4. 26.4 UNICOMM I2C Registers
      1. 26.4.1 UNICOMMI2CC Registers
      2. 26.4.2 UNICOMMI2CT Registers
  29. 27UNICOMM-SPI
    1. 27.1 UNICOMM-SPI Overview
      1. 27.1.1 Purpose of the Peripheral
      2. 27.1.2 Features
      3. 27.1.3 Functional Block Diagram
      4. 27.1.4 External Connections and Signal Descriptions
    2. 27.2 SPI Operation
      1. 27.2.1  Clock Frequency Support
        1. 27.2.1.1 SPI Clock Generation
      2. 27.2.2  General Architecture
        1. 27.2.2.1 Chip Select and Command Handling
          1. 27.2.2.1.1 Chip Select Control
        2. 27.2.2.2 Command Data Control
        3. 27.2.2.3 Data Format
        4. 27.2.2.4 Delayed data sampling
        5. 27.2.2.5 DMA Operation
      3. 27.2.3  FIFO Operation
        1. 27.2.3.1 FIFO Size
        2. 27.2.3.2 FIFO Status bits
          1. 27.2.3.2.1 RIS.RX based on FIFO threshold settings
          2. 27.2.3.2.2 RIS.TX based on FIFO threshold settings
        3. 27.2.3.3 Clearing FIFO contents
        4. 27.2.3.4 Hardware monitors empty, full and overflow conditions
      4. 27.2.4  Suspend communication
        1. 27.2.4.1 SPI IDLE State Requirements
      5. 27.2.5  Internal Loopback Operation
      6. 27.2.6  Repeat Transfer mode
      7. 27.2.7  Receive Timeout
      8. 27.2.8  Line Timeout
      9. 27.2.9  Protocol Descriptions
        1. 27.2.9.1 Motorola SPI Frame Format
        2. 27.2.9.2 Texas Instruments Synchronous Serial Frame Format
      10. 27.2.10 Status Flags
      11. 27.2.11 Module configuration
      12. 27.2.12 Reset Considerations
      13. 27.2.13 Initialization
      14. 27.2.14 Interrupt and Events Support
        1. 27.2.14.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 27.2.14.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      15. 27.2.15 Emulation Modes
        1. 27.2.15.1 Graceful Halt
    3. 27.3 UNICOMMSPI Registers
  30. 28Timers (TIMx)
    1. 28.1 TIMx Overview
      1. 28.1.1 TIMG Overview
        1. 28.1.1.1 TIMG Features
        2. 28.1.1.2 Functional Block Diagram
      2. 28.1.2 TIMA Overview
        1. 28.1.2.1 TIMA Features
        2. 28.1.2.2 Functional Block Diagram
      3. 28.1.3 TIMx Instance Configuration
    2. 28.2 TIMx Operation
      1. 28.2.1  Timer Counter
        1. 28.2.1.1 Clock Source Select and Prescaler
          1. 28.2.1.1.1 Internal Clock and Prescaler
          2. 28.2.1.1.2 External Signal Trigger
        2. 28.2.1.2 Repeat Counter (TIMA only)
      2. 28.2.2  Counting Mode Control
        1. 28.2.2.1 One-shot and Periodic Modes
        2. 28.2.2.2 Down Counting Mode
        3. 28.2.2.3 Up/Down Counting Mode
        4. 28.2.2.4 Up Counting Mode
        5. 28.2.2.5 Phase Load (TIMA only)
      3. 28.2.3  Capture/Compare Module
        1. 28.2.3.1 Capture Mode
          1. 28.2.3.1.1 Input Selection, Counter Conditions, and Inversion
            1. 28.2.3.1.1.1 CCP Input Edge Synchronization
            2. 28.2.3.1.1.2 CCP Input Pulse Conditions
            3. 28.2.3.1.1.3 Counter Control Operation
            4. 28.2.3.1.1.4 CCP Input Filtering
            5. 28.2.3.1.1.5 Input Selection
          2. 28.2.3.1.2 Use Cases
            1. 28.2.3.1.2.1 Edge Time Capture
            2. 28.2.3.1.2.2 Period Capture
            3. 28.2.3.1.2.3 Pulse Width Capture
            4. 28.2.3.1.2.4 Combined Pulse Width and Period Time
          3. 28.2.3.1.3 QEI Mode (TIMG with QEI support only)
            1. 28.2.3.1.3.1 QEI With 2-Signal
            2. 28.2.3.1.3.2 QEI With Index Input
            3. 28.2.3.1.3.3 QEI Error Detection
          4. 28.2.3.1.4 Hall Input Mode (TIMG with QEI support only)
        2. 28.2.3.2 Compare Mode
          1. 28.2.3.2.1 Edge Count
      4. 28.2.4  Shadow Load and Shadow Compare
        1. 28.2.4.1 Shadow Load (TIMG4-7, TIMA only)
        2. 28.2.4.2 Shadow Compare (TIMG4-7, TIMG12-13, TIMA only)
      5. 28.2.5  Output Generator
        1. 28.2.5.1 Configuration
        2. 28.2.5.2 Use Cases
          1. 28.2.5.2.1 Edge-Aligned PWM
          2. 28.2.5.2.2 Center-Aligned PWM
          3. 28.2.5.2.3 Asymmetric PWM (TIMA only)
          4. 28.2.5.2.4 Complementary PWM With Deadband Insertion (TIMA only)
        3. 28.2.5.3 Forced Output
      6. 28.2.6  Fault Handler (TIMA only)
        1. 28.2.6.1 Fault Input Conditioning
        2. 28.2.6.2 Fault Input Sources
        3. 28.2.6.3 Counter Behavior With Fault Conditions
        4. 28.2.6.4 Output Behavior With Fault Conditions
      7. 28.2.7  Synchronization With Cross Trigger
        1. 28.2.7.1 Main Timer Cross Trigger Configuration
        2. 28.2.7.2 Secondary Timer Cross Trigger Configuration
      8. 28.2.8  Low Power Operation
      9. 28.2.9  Interrupt and Event Support
        1. 28.2.9.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 28.2.9.2 Generic Event Publisher and Subscriber (GEN_EVENT0 and GEN_EVENT1)
        3. 28.2.9.3 Generic Subscriber Event Example (COMP to TIMx)
      10. 28.2.10 Debug Handler (TIMA Only)
    3. 28.3 TIMx Registers
  31. 29TIMB
    1. 29.1 TIMB Overview
      1. 29.1.1 Features
      2. 29.1.2 TIMB Block Diagram
    2. 29.2 TIMB Operation
      1. 29.2.1 Counter Block Operation
        1. 29.2.1.1 Clock Source Selection
        2. 29.2.1.2 Counter Reset Generation
        3. 29.2.1.3 Event Based Enable and Disable
        4. 29.2.1.4 Event Generation
        5. 29.2.1.5 Interrupt Generation
        6. 29.2.1.6 Counter Behavior on a Debug Halt
        7. 29.2.1.7 Hardware Locking of Configuration Registers
    3. 29.3 TIMB Example Applications
      1. 29.3.1 Periodic Interrupt Generation
      2. 29.3.2 Counter Chaining
      3. 29.3.3 Event Counting
      4. 29.3.4 Event Duration Measurement
      5. 29.3.5 Event Sequence Checking
      6. 29.3.6 PWM Generation
    4. 29.4 TIMB Registers
  32. 30Low Frequency Subsystem (LFSS)
    1. 30.1  Overview
    2. 30.2  Clock System
    3. 30.3  LFSS Reset Using VBAT
    4. 30.4  Power Domains and Supply Detection
      1. 30.4.1 Startup When VBAT Powers on First
      2. 30.4.2 Startup when VDD powers on first
      3. 30.4.3 Behavior When VDD is Lost
      4. 30.4.4 Behavior when VBAT is lost
      5. 30.4.5 Behavior when the device goes into SHUTDOWN mode
      6. 30.4.6 Supercapacitor Charging Circuit
    5. 30.5  Real Time Counter (RTC_x)
    6. 30.6  Independent Watchdog Timer (IWDT)
    7. 30.7  Tamper Input and Output
      1. 30.7.1 IOMUX Mode
      2. 30.7.2 Tamper Mode
        1. 30.7.2.1 Tamper Event Detection
        2. 30.7.2.2 Timestamp Event Output
        3. 30.7.2.3 Heartbeat Generator
        4. 30.7.2.4 RTC Clock Output
    8. 30.8  Scratchpad Memory
    9. 30.9  Lock Function of RTC, TIO, and IWDT
    10. 30.10 LFSS Registers
  33. 31Low Frequency Subsystem (LFSS_B)
    1. 31.1 Overview
    2. 31.2 Clock System
    3. 31.3 LFSS Reset
    4. 31.4 Real Time Counter (RTC_x)
    5. 31.5 Independent Watchdog Timer (IWDT)
    6. 31.6 Lock Function of RTC and IWDT
    7. 31.7 LFSS Registers
  34. 32RTC
    1. 32.1 Overview
      1. 32.1.1 RTC Instances
    2. 32.2 Basic Operation
    3. 32.3 Configuration
      1. 32.3.1  Clocking
      2. 32.3.2  Reading and Writing to RTC Peripheral Registers
      3. 32.3.3  Binary vs. BCD
      4. 32.3.4  Leap Year Handling
      5. 32.3.5  Calendar Alarm Configuration
      6. 32.3.6  Interval Alarm Configuration
      7. 32.3.7  Periodic Alarm Configuration
      8. 32.3.8  Calibration
        1. 32.3.8.1 Crystal Offset Error
          1. 32.3.8.1.1 Offset Error Correction Mechanism
        2. 32.3.8.2 Crystal Temperature Error
          1. 32.3.8.2.1 Temperature Drift Correction Mechanism
      9. 32.3.9  RTC Prescaler Extension
      10. 32.3.10 RTC Timestamp Capture
      11. 32.3.11 RTC Events
        1. 32.3.11.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 32.3.11.2 Generic Event Publisher (GEN_EVENT)
    4. 32.4 RTC Registers
  35. 33IWDT
    1. 33.1 920
    2. 33.2 IWDT Clock Configuration
    3. 33.3 IWDT Period Selection
    4. 33.4 Debug Behavior of the IWDT
    5. 33.5 IWDT Registers
  36. 34Window Watchdog Timer (WWDT)
    1. 34.1 WWDT Overview
      1. 34.1.1 Watchdog Mode
      2. 34.1.2 Interval Timer Mode
    2. 34.2 WWDT Operation
      1. 34.2.1 Mode Selection
      2. 34.2.2 Clock Configuration
      3. 34.2.3 Low-Power Mode Behavior
      4. 34.2.4 Debug Behavior
      5. 34.2.5 WWDT Events
        1. 34.2.5.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 34.3 WWDT Registers
  37. 35Debug
    1. 35.1 DEBUGSS Overview
      1. 35.1.1 Debug Interconnect
      2. 35.1.2 Physical Interface
      3. 35.1.3 Debug Access Ports
    2. 35.2 DEBUGSS Operation
      1. 35.2.1 Debug Features
        1. 35.2.1.1 Processor Debug
          1. 35.2.1.1.1 Breakpoint Unit (BPU)
          2. 35.2.1.1.2 Data Watchpoint and Trace Unit (DWT)
        2. 35.2.1.2 Peripheral Debug
        3. 35.2.1.3 EnergyTrace Technology
      2. 35.2.2 Behavior in Low Power Modes
      3. 35.2.3 Restricting Debug Access
      4. 35.2.4 Mailbox (DSSM)
        1. 35.2.4.1 DSSM Events
          1. 35.2.4.1.1 CPU Interrupt Event (CPU_INT)
        2. 35.2.4.2 Reference
    3. 35.3 DEBUGSS Registers
  38. 36Revision History

10.3 AESADV Registers

Table 10-6 lists the memory-mapped registers for the AESADV registers. All register offset addresses not listed in Table 10-6 should be considered as reserved locations and the register contents should not be modified.

Table 10-6 AESADV Registers
OffsetAcronymRegister NameGroupSection
480hCPU_CONNECT_0CPU ConnectGo
800hPWRENPower enableGo
804hRSTCTLReset ControlGo
814hSTATStatus RegisterGo
1018hPDBGCTLPeripheral Debug ControlGo
1020hIIDXInterrupt Index RegisterGo
1028hIMASKInterrupt maskGo
1030hRISRaw interrupt statusGo
1038hMISMasked interrupt statusGo
1040hISETInterrupt setGo
1048hICLRInterrupt clearGo
1050hIIDXInterrupt Index RegisterDMA_TRIG_DATAINGo
1058hIMASKInterrupt maskDMA_TRIG_DATAINGo
1060hRISRaw interrupt statusDMA_TRIG_DATAINGo
1068hMISMasked interrupt statusDMA_TRIG_DATAINGo
1070hISETInterrupt setDMA_TRIG_DATAINGo
1078hICLRInterrupt clearDMA_TRIG_DATAINGo
1080hIIDXInterrupt Index RegisterDMA_TRIG_DATAOUTGo
1088hIMASKInterrupt maskDMA_TRIG_DATAOUTGo
1090hRISRaw interrupt statusDMA_TRIG_DATAOUTGo
1098hMISMasked interrupt statusDMA_TRIG_DATAOUTGo
10A0hISETInterrupt setDMA_TRIG_DATAOUTGo
10A8hICLRInterrupt clearDMA_TRIG_DATAOUTGo
10E0hEVT_MODEEvent ModeGo
1100hGCMCCM_TAG0CBC-MAC third key (LSW) / GCM & CCM Intermediate TAG (LSW)Go
1104hGCMCCM_TAG1CBC-MAC third key / GCM & CCM Intermediate TAGGo
1108hGCMCCM_TAG2CBC-MAC third key / GCM & CCM Intermediate TAGGo
110ChGCMCCM_TAG3CBC-MAC third key (MSW) / GCM & CCM Intermediate TAG (MSW)Go
1110hGHASH_H0CCM & CBC-MAC second key (LSW) / GCM Hash Key input (LSW)Go
1114hGHASH_H1CCM & CBC-MAC second key / GCM Hash Key inputGo
1118hGHASH_H2CCM & CBC-MAC second key / GCM Hash Key inputGo
111ChGHASH_H3CCM & CBC-MAC second key (MSW) / GCM Hash Key input (MSW)Go
1120hKEY0KEY (LSW)Go
1124hKEY1KEYGo
1128hKEY2KEYGo
112ChKEY3KEYGo
1130hKEY4KEYGo
1134hKEY5KEYGo
1138hKEY6KEYGo
113ChKEY7KEY (MSW)Go
1140hIV0IV (LSW)Go
1144hIV1IVGo
1148hIV2IVGo
114ChIV3IVGo
1150hCTRLInput/Output Buffer Control and Mode selectionGo
1154hC_LENGTH_0Crypto data length (LSW)Go
1158hC_LENGTH_1Crypto data length (MSW)Go
115ChAAD_LENGTHAAD Data LengthGo
1160hDATA0Data input (LSW) / Data output (LSW)Go
1164hDATA1Data input / Data outputGo
1168hDATA2Data input / Data outputGo
116ChDATA3Data input (LSW) / Data output (MSW)Go
1170hTAG0Hash result (LSW)Go
1174hTAG1Hash resultGo
1178hTAG2Hash resultGo
117ChTAG3Hash result (MSW)Go
1180hSTATUSStatusGo
1184hDATA_INData in alias registerGo
1188hDATA_OUTData out alias registerGo
11D0hFORCE_IN_AVData control register for input dataGo
11D4hCCM_ALN_WRDAES-CCM AAD alignment data wordGo
11D8hBLK_CNT0Internal block counter (LSW)Go
11DChBLK_CNT1Internal block counter (MSW)Go
11F4hDMA_HSControl register for DMA handshakingGo

Complex bit access types are encoded to fit into small table cells. Table 10-7 shows the codes that are used for access types in this section.

Table 10-7 AESADV Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
WKW
K		Write
Write protected by a key
Reset or Default Value
-nValue after reset or the default value

10.3.1 CPU_CONNECT_0 (Offset = 480h) [Reset = 00000000h]

CPU_CONNECT_0 is shown in Figure 10-11 and described in Table 10-8.

Return to the Summary Table.

Directly connect peripheral publisher port to application processor

Figure 10-11 CPU_CONNECT_0
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCPUSS0_CONNRESERVED
R-0hR/W-0hR-0h
Table 10-8 CPU_CONNECT_0 Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0h
1CPUSS0_CONNR/W0hCPUSS0 connect bit.
0h = The CPU is not connected.
1h = The CPU is connected.
0RESERVEDR0h

10.3.2 PWREN (Offset = 800h) [Reset = 00000000h]

PWREN is shown in Figure 10-12 and described in Table 10-9.

Return to the Summary Table.

Register to control the power state

Figure 10-12 PWREN
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDENABLE
R-0hR/WK-0h
Table 10-9 PWREN Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hKEY to allow Power State Change
26h = KEY to allow write access to this register
23-1RESERVEDR0h
0ENABLER/WK0hEnable the power

KEY must be set to 26h to write to this bit.


0h = Disable Power
1h = Enable Power

10.3.3 RSTCTL (Offset = 804h) [Reset = 00000000h]

RSTCTL is shown in Figure 10-13 and described in Table 10-10.

Return to the Summary Table.

Register to control reset assertion and de-assertion

Figure 10-13 RSTCTL
3130292827262524
KEY
W-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRESETSTKYCLRRESETASSERT
R-0hWK-0hWK-0h
Table 10-10 RSTCTL Field Descriptions
BitFieldTypeResetDescription
31-24KEYW0hUnlock key
B1h = KEY to allow write access to this register
23-2RESERVEDR0h
1RESETSTKYCLRWK0hClear the RESETSTKY bit in the STAT register

KEY must be set to B1h to write to this bit.


0h = Writing 0 has no effect
1h = Clear reset sticky bit
0RESETASSERTWK0hAssert reset to the peripheral

KEY must be set to B1h to write to this bit.


0h = Writing 0 has no effect
1h = Assert reset

10.3.4 STAT (Offset = 814h) [Reset = 00000000h]

STAT is shown in Figure 10-14 and described in Table 10-11.

Return to the Summary Table.

peripheral enable and reset status

Figure 10-14 STAT
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDRESETSTKY
R-0hR-0h
15141312111098
RESERVED
R-0h
76543210
RESERVED
R-0h
Table 10-11 STAT Field Descriptions
BitFieldTypeResetDescription
31-17RESERVEDR0h
16RESETSTKYR0hThis bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register
1h = The peripheral was reset since the last bit clear
15-0RESERVEDR0h

10.3.5 PDBGCTL (Offset = 1018h) [Reset = 00000000h]

PDBGCTL is shown in Figure 10-15 and described in Table 10-12.

Return to the Summary Table.

AES can not be halted when the core is halted. In order to halt the AES, the DMA shall be halted.
This achieves the same effect as a halt feature in the AES: when the AES submits the next DMA trigger, if the DMA is halted, then the AES will automatically halt.

Figure 10-15 PDBGCTL
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDFREE
R-0hR-0h
Table 10-12 PDBGCTL Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h
0FREER0hFree run control
1h = The peripheral ignores the state of the Core Halted input

10.3.6 IIDX (Offset = 1020h) [Reset = 00000000h]

IIDX is shown in Figure 10-16 and described in Table 10-13.

Return to the Summary Table.

This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, … IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in [RIS] and [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.

Figure 10-16 IIDX
313029282726252423222120191817161514131211109876543210
RESERVEDSTAT
R-0hR-0h
Table 10-13 IIDX Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-0STATR0hInterrupt index status
00h = No interrupt pending
1h = This indicates that the core has an output available to be read out. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1)
2h = This indicates that the engine can take new input. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1)
3h = This bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the CPU to retrieve. This bit is only asserted if the ‘save_context’ bit is set to ‘1b’. The bit is mutually exclusive with the ‘context_ready’ bit.
4h = This bit indicates that the context data registers can be overwritten, and the CPU is permitted to write new context.

10.3.7 IMASK (Offset = 1028h) [Reset = 00000000h]

IMASK is shown in Figure 10-17 and described in Table 10-14.

Return to the Summary Table.

Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Figure 10-17 IMASK
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCNTXTRDYSAVEDCNTXTRDYINPUTRDYOUTPUTRDY
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 10-14 IMASK Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h
3CNTXTRDYR/W0hThis bit indicates that the context data registers can be overwritten, and the CPU is permitted to write next context.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
2SAVEDCNTXTRDYR/W0hThis bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the CPU to retrieve. This bit is only asserted if the ‘save_context’ bit is set to ‘1b’. The bit is mutually exclusive with the ‘context_ready’ bit.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
1INPUTRDYR/W0hThis indicates that the engine can take new input. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1)
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
0OUTPUTRDYR/W0hThis indicates that the core has an output available to be read out. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1)
0h = Clear Interrupt Mask
1h = Set Interrupt Mask

10.3.8 RIS (Offset = 1030h) [Reset = 00000000h]

RIS is shown in Figure 10-18 and described in Table 10-15.

Return to the Summary Table.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 10-18 RIS
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCNTXTRDYSAVEDCNTXTRDYINPUTRDYOUTPUTRDY
R-0hR-0hR-0hR-0hR-0h
Table 10-15 RIS Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h
3CNTXTRDYR0hThis bit indicates that the context data registers can be overwritten, and the CPU is permitted to write next context.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
2SAVEDCNTXTRDYR0hThis bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the CPU to retrieve. This bit is only asserted if the ‘save_context’ bit is set to ‘1b’. The bit is mutually exclusive with the ‘context_ready’ bit.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
1INPUTRDYR0hThis indicates that the engine can take new input. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1)
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
0OUTPUTRDYR0hThis indicates that the core has an output available to be read out. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1)
0h = Interrupt did not occur
1h = Interrupt occurred

10.3.9 MIS (Offset = 1038h) [Reset = 00000000h]

MIS is shown in Figure 10-19 and described in Table 10-16.

Return to the Summary Table.

Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 10-19 MIS
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCNTXTRDYSAVEDCNTXTRDYINPUTRDYOUTPUTRDY
R-0hR-0hR-0hR-0hR-0h
Table 10-16 MIS Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h
3CNTXTRDYR0hThis bit indicates that the context data registers can be overwritten, and the CPU is permitted to write next context.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
2SAVEDCNTXTRDYR0hThis bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the CPU to retrieve. This bit is only asserted if the ‘save_context’ bit is set to ‘1b’. The bit is mutually exclusive with the ‘context_ready’ bit.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
1INPUTRDYR0hThis indicates that the engine can take new input. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1)
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
0OUTPUTRDYR0hThis indicates that the core has an output available to be read out. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1)
0h = Interrupt did not occur
1h = Interrupt occurred

10.3.10 ISET (Offset = 1040h) [Reset = 00000000h]

ISET is shown in Figure 10-20 and described in Table 10-17.

Return to the Summary Table.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 10-20 ISET
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCNTXTRDYSAVEDCNTXTRDYINPUTRDYOUTPUTRDY
R-0hW-0hW-0hW-0hW-0h
Table 10-17 ISET Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h
3CNTXTRDYW0hThis bit indicates that the context data registers can be overwritten, and the CPU is permitted to write next context.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
2SAVEDCNTXTRDYW0hThis bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the CPU to retrieve. This bit is only asserted if the ‘save_context’ bit is set to ‘1b’. The bit is mutually exclusive with the ‘context_ready’ bit.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
1INPUTRDYW0hThis indicates that the engine can take new input. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1)
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
0OUTPUTRDYW0hThis indicates that the core has an output available to be read out. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1)
0h = Writing 0 has no effect
1h = Set Interrupt

10.3.11 ICLR (Offset = 1048h) [Reset = 00000000h]

ICLR is shown in Figure 10-21 and described in Table 10-18.

Return to the Summary Table.

Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 10-21 ICLR
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDCNTXTRDYSAVEDCNTXTRDYINPUTRDYOUTPUTRDY
R-0hW-0hW-0hW-0hW-0h
Table 10-18 ICLR Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0h
3CNTXTRDYW0hThis bit indicates that the context data registers can be overwritten, and the CPU is permitted to write next context.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
2SAVEDCNTXTRDYW0hThis bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the CPU to retrieve. This bit is only asserted if the ‘save_context’ bit is set to ‘1b’. The bit is mutually exclusive with the ‘context_ready’ bit.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
1INPUTRDYW0hThis indicates that the engine can take new input. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1)
0h = Clear Interrupt Mask
1h = Set Interrupt Mask
0OUTPUTRDYW0hThis indicates that the core has an output available to be read out. This should not be used if DMA handshake is used (AES_DMA_HS.DMA_DATA_ACK set to 1)
0h = Writing 0 has no effect
1h = Clear Interrupt

10.3.12 IIDX (Offset = 1050h) [Reset = 00000000h]

IIDX is shown in Figure 10-22 and described in Table 10-19.

Return to the Summary Table.

This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, … IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in [RIS] and [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.

Figure 10-22 IIDX
313029282726252423222120191817161514131211109876543210
RESERVEDSTAT
R-0hR-0h
Table 10-19 IIDX Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-0STATR0hInterrupt index status
00h = No interrupt pending
1h = AES trigger 0 DMA (Data Input trigger)

10.3.13 IMASK (Offset = 1058h) [Reset = 00000000h]

IMASK is shown in Figure 10-23 and described in Table 10-20.

Return to the Summary Table.

Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Figure 10-23 IMASK
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDTRIG0
R-0hR/W-0h
Table 10-20 IMASK Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h
0TRIG0R/W0hTRIG0 event mask.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask

10.3.14 RIS (Offset = 1060h) [Reset = 00000000h]

RIS is shown in Figure 10-24 and described in Table 10-21.

Return to the Summary Table.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 10-24 RIS
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDTRIG0
R-0hR-0h
Table 10-21 RIS Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h
0TRIG0R0hTRIG0 event
0h = Interrupt did not occur
1h = Interrupt occurred

10.3.15 MIS (Offset = 1068h) [Reset = 00000000h]

MIS is shown in Figure 10-25 and described in Table 10-22.

Return to the Summary Table.

Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 10-25 MIS
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDTRIG0
R-0hR-0h
Table 10-22 MIS Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h
0TRIG0R0hTRIG0 event
0h = Interrupt did not occur
1h = Interrupt occurred

10.3.16 ISET (Offset = 1070h) [Reset = 00000000h]

ISET is shown in Figure 10-26 and described in Table 10-23.

Return to the Summary Table.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 10-26 ISET
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDTRIG0
R-0hW-0h
Table 10-23 ISET Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h
0TRIG0W0hTRIG0
0h = Writing 0 has no effect
1h = Set Interrupt

10.3.17 ICLR (Offset = 1078h) [Reset = 00000000h]

ICLR is shown in Figure 10-27 and described in Table 10-24.

Return to the Summary Table.

Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 10-27 ICLR
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDTRIG0
R-0hW-0h
Table 10-24 ICLR Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h
0TRIG0W0hTRIG0 event
0h = Writing 0 has no effect
1h = Clear Interrupt

10.3.18 IIDX (Offset = 1080h) [Reset = 00000000h]

IIDX is shown in Figure 10-28 and described in Table 10-25.

Return to the Summary Table.

This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, … IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred.
On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in [RIS] and [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.

Figure 10-28 IIDX
313029282726252423222120191817161514131211109876543210
RESERVEDSTAT
R-0hR-0h
Table 10-25 IIDX Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-0STATR0hInterrupt index status
00h = No interrupt pending
1h = AES DMA Trigger 1 (Data Output trigger)

10.3.19 IMASK (Offset = 1088h) [Reset = 00000000h]

IMASK is shown in Figure 10-29 and described in Table 10-26.

Return to the Summary Table.

Interrupt Mask. If a bit is set, then corresponding interrupt is unmasked. Unmasking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Figure 10-29 IMASK
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDTRIG1
R-0hR/W-0h
Table 10-26 IMASK Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h
0TRIG1R/W0hTRIG1 event mask.
0h = Clear Interrupt Mask
1h = Set Interrupt Mask

10.3.20 RIS (Offset = 1090h) [Reset = 00000000h]

RIS is shown in Figure 10-30 and described in Table 10-27.

Return to the Summary Table.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 10-30 RIS
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDTRIG1
R-0hR-0h
Table 10-27 RIS Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h
0TRIG1R0hTRIG1 event
0h = Interrupt did not occur
1h = Interrupt occurred

10.3.21 MIS (Offset = 1098h) [Reset = 00000000h]

MIS is shown in Figure 10-31 and described in Table 10-28.

Return to the Summary Table.

Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 10-31 MIS
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDTRIG1
R-0hR-0h
Table 10-28 MIS Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h
0TRIG1R0hTRIG1 event
0h = Interrupt did not occur
1h = Interrupt occurred

10.3.22 ISET (Offset = 10A0h) [Reset = 00000000h]

ISET is shown in Figure 10-32 and described in Table 10-29.

Return to the Summary Table.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 10-32 ISET
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDTRIG1
R-0hW-0h
Table 10-29 ISET Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h
0TRIG1W0hTRIG1 event
0h = Writing 0 has no effect
1h = Set Interrupt

10.3.23 ICLR (Offset = 10A8h) [Reset = 00000000h]

ICLR is shown in Figure 10-33 and described in Table 10-30.

Return to the Summary Table.

Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 10-33 ICLR
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDTRIG1
R-0hW-0h
Table 10-30 ICLR Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h
0TRIG1W0hTRIG1 event
0h = Writing 0 has no effect
1h = Clear Interrupt

10.3.24 EVT_MODE (Offset = 10E0h) [Reset = 00000000h]

EVT_MODE is shown in Figure 10-34 and described in Table 10-31.

Return to the Summary Table.

Event mode register. It is used to select whether each line is disabled, in software mode (software clears the RIS) or in hardware mode (hardware clears the RIS)

Figure 10-34 EVT_MODE
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDEVT2_CFGEVT1_CFGINT0_CFG
R-0hR-0hR-0hR-0h
Table 10-31 EVT_MODE Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0h
5-4EVT2_CFGR0hEvent line mode select for event corresponding to INT_EVENT2
0h = The interrupt or event line is disabled.
1h = The interrupt or event line is in software mode. Software must clear the RIS.
2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.
3-2EVT1_CFGR0hEvent line mode select for event corresponding to INT_EVENT1
0h = The interrupt or event line is disabled.
1h = The interrupt or event line is in software mode. Software must clear the RIS.
2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.
1-0INT0_CFGR0hEvent line mode select for event corresponding to INT_EVENT0
0h = The interrupt or event line is disabled.
1h = The interrupt or event line is in software mode. Software must clear the RIS.
2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.

10.3.25 GCMCCM_TAG0 (Offset = 1100h) [Reset = 00000000h]

GCMCCM_TAG0 is shown in Figure 10-35 and described in Table 10-32.

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CBC-MAC third key (LSW) / GCM & CCM Intermediate TAG (LSW)
For CBC-MAC: Pre-calculated CBC-MAC third key used to perform a final XOR operation on the last input data block.
For CCM: This register is internally used to store intermediate values. This register must be initialized with zeroes when writing a new CCM context. To restore an interrupted CCM operation, this register needs to be loaded with the intermediate TAG.
For GCM: This register is internally used to store intermediate values. This register must be initialized with zeroes when writing a new GCM context. To restore an interrupted GCM operation, this register needs to be loaded with the intermediate TAG.

Figure 10-35 GCMCCM_TAG0
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 10-32 GCMCCM_TAG0 Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hKey data

10.3.26 GCMCCM_TAG1 (Offset = 1104h) [Reset = 00000000h]

GCMCCM_TAG1 is shown in Figure 10-36 and described in Table 10-33.

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CBC-MAC third key / GCM & CCM Intermediate TAG
For CBC-MAC: Pre-calculated CBC-MAC third key used to perform a final XOR operation on the last input data block.
For CCM: This register is internally used to store intermediate values. This register must be initialized with zeroes when writing a new CCM context. To restore an interrupted CCM operation, this register needs to be loaded with the intermediate TAG.
For GCM: This register is internally used to store intermediate values. This register must be initialized with zeroes when writing a new GCM context. To restore an interrupted GCM operation, this register needs to be loaded with the intermediate TAG.

Figure 10-36 GCMCCM_TAG1
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 10-33 GCMCCM_TAG1 Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hKey data

10.3.27 GCMCCM_TAG2 (Offset = 1108h) [Reset = 00000000h]

GCMCCM_TAG2 is shown in Figure 10-37 and described in Table 10-34.

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CBC-MAC third key / GCM & CCM Intermediate TAG
For CBC-MAC: Pre-calculated CBC-MAC third key used to perform a final XOR operation on the last input data block.
For CCM: This register is internally used to store intermediate values. This register must be initialized with zeroes when writing a new CCM context. To restore an interrupted CCM operation, this register needs to be loaded with the intermediate TAG.
For GCM: This register is internally used to store intermediate values. This register must be initialized with zeroes when writing a new GCM context. To restore an interrupted GCM operation, this register needs to be loaded with the intermediate TAG.

Figure 10-37 GCMCCM_TAG2
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 10-34 GCMCCM_TAG2 Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hKey data

10.3.28 GCMCCM_TAG3 (Offset = 110Ch) [Reset = 00000000h]

GCMCCM_TAG3 is shown in Figure 10-38 and described in Table 10-35.

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CBC-MAC third key (MSW) / GCM & CCM Intermediate TAG (MSW)
For CBC-MAC: Pre-calculated CBC-MAC third key used to perform a final XOR operation on the last input data block.
For CCM: This register is internally used to store intermediate values. This register must be initialized with zeroes when writing a new CCM context. To restore an interrupted CCM operation, this register needs to be loaded with the intermediate TAG.
For GCM: This register is internally used to store intermediate values. This register must be initialized with zeroes when writing a new GCM context. To restore an interrupted GCM operation, this register needs to be loaded with the intermediate TAG.

Figure 10-38 GCMCCM_TAG3
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 10-35 GCMCCM_TAG3 Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hKey data

10.3.29 GHASH_H0 (Offset = 1110h) [Reset = 00000000h]

GHASH_H0 is shown in Figure 10-39 and described in Table 10-36.

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CCM & CBC-MAC second key (LSW) / GCM Hash Key input (LSW)
For CBC-MAC: Pre-calculated CBC-MAC second key used to perform a final XOR operation on the last input data block.
For GCM: Hash key; can be calculated internal or written via these registers. Only used for GHASH (GCM) modes.
For a CPU write operation, these registers must be written with the new values to be subsequently transferred to the engine.

Figure 10-39 GHASH_H0
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 10-36 GHASH_H0 Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hKey data

10.3.30 GHASH_H1 (Offset = 1114h) [Reset = 00000000h]

GHASH_H1 is shown in Figure 10-40 and described in Table 10-37.

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CCM & CBC-MAC second key / GCM Hash Key input
For CBC-MAC: Pre-calculated CBC-MAC second key used to perform a final XOR operation on the last input data block.
For GCM: Hash key; can be calculated internal or written via these registers. Only used for GHASH (GCM) modes.
For a CPU write operation, these registers must be written with the new values to be subsequently transferred to the engine.

Figure 10-40 GHASH_H1
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 10-37 GHASH_H1 Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hKey data

10.3.31 GHASH_H2 (Offset = 1118h) [Reset = 00000000h]

GHASH_H2 is shown in Figure 10-41 and described in Table 10-38.

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CCM & CBC-MAC second key / GCM Hash Key input
For CBC-MAC: Pre-calculated CBC-MAC second key used to perform a final XOR operation on the last input data block.
For GCM: Hash key; can be calculated internal or written via these registers. Only used for GHASH (GCM) modes.
For a CPU write operation, these registers must be written with the new values to be subsequently transferred to the engine.

Figure 10-41 GHASH_H2
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 10-38 GHASH_H2 Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hKey data

10.3.32 GHASH_H3 (Offset = 111Ch) [Reset = 00000000h]

GHASH_H3 is shown in Figure 10-42 and described in Table 10-39.

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CCM & CBC-MAC second key (MSW) / GCM Hash Key input (MSW)
For CBC-MAC: Pre-calculated CBC-MAC second key used to perform a final XOR operation on the last input data block.
For GCM: Hash key; can be calculated internal or written via these registers. Only used for GHASH (GCM) modes.
For a CPU write operation, these registers must be written with the new values to be subsequently transferred to the engine.

Figure 10-42 GHASH_H3
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 10-39 GHASH_H3 Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hKey data

10.3.33 KEY0 (Offset = 1120h) [Reset = 00000000h]

KEY0 is shown in Figure 10-43 and described in Table 10-40.

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KEY (LSW)

Figure 10-43 KEY0
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 10-40 KEY0 Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hKey data

10.3.34 KEY1 (Offset = 1124h) [Reset = 00000000h]

KEY1 is shown in Figure 10-44 and described in Table 10-41.

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KEY

Figure 10-44 KEY1
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 10-41 KEY1 Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hKey data

10.3.35 KEY2 (Offset = 1128h) [Reset = 00000000h]

KEY2 is shown in Figure 10-45 and described in Table 10-42.

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KEY

Figure 10-45 KEY2
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 10-42 KEY2 Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hKey data

10.3.36 KEY3 (Offset = 112Ch) [Reset = 00000000h]

KEY3 is shown in Figure 10-46 and described in Table 10-43.

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KEY

Figure 10-46 KEY3
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 10-43 KEY3 Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hKey data

10.3.37 KEY4 (Offset = 1130h) [Reset = 00000000h]

KEY4 is shown in Figure 10-47 and described in Table 10-44.

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KEY

Figure 10-47 KEY4
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 10-44 KEY4 Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hKey data

10.3.38 KEY5 (Offset = 1134h) [Reset = 00000000h]

KEY5 is shown in Figure 10-48 and described in Table 10-45.

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KEY

Figure 10-48 KEY5
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 10-45 KEY5 Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hKey data

10.3.39 KEY6 (Offset = 1138h) [Reset = 00000000h]

KEY6 is shown in Figure 10-49 and described in Table 10-46.

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KEY

Figure 10-49 KEY6
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 10-46 KEY6 Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hKey data

10.3.40 KEY7 (Offset = 113Ch) [Reset = 00000000h]

KEY7 is shown in Figure 10-50 and described in Table 10-47.

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KEY (MSW)

Figure 10-50 KEY7
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 10-47 KEY7 Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hKey data

10.3.41 IV0 (Offset = 1140h) [Reset = 00000000h]

IV0 is shown in Figure 10-51 and described in Table 10-48.

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IV (LSW)

Figure 10-51 IV0
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 10-48 IV0 Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hKey data

10.3.42 IV1 (Offset = 1144h) [Reset = 00000000h]

IV1 is shown in Figure 10-52 and described in Table 10-49.

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IV

Figure 10-52 IV1
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 10-49 IV1 Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hKey data

10.3.43 IV2 (Offset = 1148h) [Reset = 00000000h]

IV2 is shown in Figure 10-53 and described in Table 10-50.

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IV

Figure 10-53 IV2
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 10-50 IV2 Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hKey data

10.3.44 IV3 (Offset = 114Ch) [Reset = 00000000h]

IV3 is shown in Figure 10-54 and described in Table 10-51.

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IV

Figure 10-54 IV3
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 10-51 IV3 Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hKey data

10.3.45 CTRL (Offset = 1150h) [Reset = 80000000h]

CTRL is shown in Figure 10-55 and described in Table 10-52.

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Input/Output Buffer Control and Mode selection. The content of this register determines the mode of operation of the engine.

Figure 10-55 CTRL
3130292827262524
CNTXT_RDYSAVED_CNTXT_RDYSAVE_CNTXTGCM_CONTGET_DIGESTOFB_GCM_CCM_CONTRESERVEDCCMM
R-1hR-0hR/W-0hR/W-0hR/W-0hR/W-0hR-0hR/W-0h
2322212019181716
CCMMCCMLCCMGCM
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
CBCMACRESERVEDCFBICMCTR_WIDTH
R/W-0hR-0hR/W-0hR/W-0hR/W-0h
76543210
CTR_WIDTHCTRCBCKEYSIZEDIRINPUT_RDYOUTPUT_RDY
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR-0hR-0h
Table 10-52 CTRL Field Descriptions
BitFieldTypeResetDescription
31CNTXT_RDYR1hIf ‘1b’, this read-only status bit indicates that the context data registers can be overwritten, and the CPU is permitted to write the next context.
0h = Not ready
1h = Ready
30SAVED_CNTXT_RDYR0hIf ‘1b’, this read-only status bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the Host to retrieve. This bit is only asserted if the ‘save_context’ bit is set to ‘1b’. The bit is mutually exclusive with the ‘context_ready’ bit.
0h = Not ready
1h = Ready
29SAVE_CNTXTR/W0hThis bit is used to indicate that an authentication TAG or result IV needs to be stored as a result context. If this bit is set, context output DMA and/or interrupt will be asserted if the operation is finished, and related signals are enabled.
Typically, this value must be set for authentication modes returning a TAG (CBC-MAC, GCM and CCM), or for basic encryption modes that require future continuation with the current result IV.
If this bit is set, the engine will hold its full context until the TAG and/or IV registers are read. Only after reading the TAG or IV, a new DMA request for a new (input) context will be asserted.
If this bit is not set, the engine will assert the context input DMA request signal directly after starting to process the last block with the current context.
0h = No effect
1h = Enable
28GCM_CONTR/W0hContinue processing of an interrupted AES-GCM or AES-CCM operation in the crypto/payload phase.
Set this write-only signal to ‘1b’ together with the regular mode bit settings for a GCM or CCM operation, to continue processing from the next full block (128 bits) boundary.
Before setting this bit all applicable context to resume processing must have been loaded into the engine: Keys, IV, intermediate digest/TAG and block counter. The mode can be written together with this bit, as it is part of the same register.
0h = No effect
1h = Enable
27GET_DIGESTR/W0hInterrupt processing and generate an intermediate digest during an AES-GCM or AES-CCM operation.
Set this write-only signal to ‘1b’ to interrupt GCM or CCM processing at the next full block (128 bits) boundary. An intermediate digest may be requested during the encryption/decryption data phase or in the AAD phase.
Note: Interruption can only be done on full block (128 bits) boundaries. The minimum number of remaining bytes to resume and finalize the operation, must be greater than or equal to 1.
0h = No effect
1h = Enable
26OFB_GCM_CCM_CONTR/W0hThis bit has a dual use, depending on the selection of CCM/GCM, see bits [18:16].
If CCM/GCM is not selected:
If this bit is set to ‘1b’, full block AES output feedback mode (OFB-128) is selected.
If CCM/GCM is selected:
Continue processing of an interrupted AES-GCM or AES-CCM operation in the AAD phase.
Set this write-only signal to ‘1b’ together with the regular mode bit settings for a GCM or CCM operation, to continue processing from the next full AAD block (128 bits) boundary.
Before setting this bit all applicable context to resume processing must have been loaded into the engine: Keys, IV, intermediate digest/TAG, block counter and the CCM align data word (the latter is for CCM mode only). The mode can be written together with this bit, as it is part of the same register.
1h = Continue GCM/CCM processing in AAD phase
25RESERVEDR0h
24-22CCMMR/W0hDefines “M” that indicates the length of the authentication field for CCM operations; the authentication field length equals two times (the value of CCM-M plus one). Note: The engine always returns a 128-bit authentication field, of which the M least significant bytes are valid. All values are supported.
0h = Length is 1
7h = Length is 8
21-19CCMLR/W0hDefines “L” that indicates the width of the length field for CCM operations; the length field in bytes equals the value of CMM-L plus one. All values are supported.
0h = Length is 1
7h = Length is 8
18CCMR/W0hIf set to ‘1b’, AES-CCM is selected, this is a combined mode, using AES for both authentication and encryption. In addition to the CCM bit, the CTR mode bit must be set such that AES-CTR is enabled. Other combinations with CCM are invalid.
0h = Disable CBC mode
1h = Select CBC mode
17-16GCMR/W0hIf not set to ‘00b’, AES-GCM mode is selected, this is a combined mode, using the Galois field multiplier GF(2128) for authentication and AES-CTR mode for encryption, the bits specify the GCM mode: 01b = GHASH with H loaded and Y0-encrypted forced to zero 10b = GHASH with H loaded and Y0-encrypted calculated internally 11b = Autonomous GHASH (both H and Y0-encrypted calculated internally) Note: Besides GCM, the CTR mode bits must also be set to ‘1b’ to enable GCM with AES-CTR; if the CTR bit is not set a GHASH (authentication) only operation is performed. A GHASH only operation is only allowed if the GCM mode is set to '01b' and the direction bit is set to '0b'. Other modes may not be selected in combination with GCM. Table 14 below shows the valid combinations for the GCM and CTR mode bits, all other options are invalid and must not be selected.
1h = GHASH with H loaded and Y0-encrypted forced to 0.
2h = GHASH with H loaded and Y0-encrypted calculated internally
3h = Autonomous GHASH (both H and Y0-encrypted calculated internally)
15CBCMACR/W0hIf set to ‘1b’, AES-CBC MAC is selected, the Direction bit must be set to ‘1’ for this mode.
0h = Disable CBC mode
1h = Select CBC mode
14-11RESERVEDR0h
10CFBR/W0hIf set to ‘1b’, AES cipher feedback mode CFB is selected. Use the ctr_width field to specify the feedback width.
0h = Disable CBC mode
1h = Select CBC mode
9ICMR/W0hWhen the CFB bit is set, specifies the CFB mode feedback width:
0h = Disable CBC mode
1h = Select CBC mode
8-7CTR_WIDTHR/W0hWhen the CTR bit is set, specifies the counter width for AES-CTR mode.
When the CFB bit is set, specifies the CFB mode feedback width:
0h = CFB-128 mode
1h = CFB-1 mode
2h = CFB-8 mode
3h = 128-bit counter
6CTRR/W0hIf set to ‘1b’, AES counter mode (CTR) is selected. Note: This bit must also be set for GCM and CCM, when encryption/decryption is required.
0h = Disable CBC mode
1h = Select CBC mode
5CBCR/W0hIf set to ‘1b’, cipher-block-chaining (CBC) mode is selected.
0h = Disable CBC mode
1h = Select CBC mode
4-3KEYSIZER/W0hSpecifies the encryption strength / key width
1h = 128-bit key
3h = 256-bit key
2DIRR/W0hDirection. If set to ‘1b’ an encrypt operation is performed. If set to ‘0b’ a decrypt operation is performed. Note: This bit must be written with a ‘1b’ when CBC-MAC is selected.
0h = Decryption
1h = Encryption
1INPUT_RDYR0hReady for input. If ‘1b’, this read-only status bit indicates that the 16-byte input buffer is empty, and the CPU is permitted to write the next block of data. After reset, this bit is ‘0’. After writing a context, this bit will become ‘1b’.
0h = Not Ready
1h = Ready
0OUTPUT_RDYR0hOutput Ready. If ‘1b’, this read-only status bit indicates that an AES output block is available for the CPU to retrieve.
0h = Not Ready
1h = Ready

10.3.46 C_LENGTH_0 (Offset = 1154h) [Reset = 00000000h]

C_LENGTH_0 is shown in Figure 10-56 and described in Table 10-53.

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Crypto data length (LSW). These registers buffer the Length values to the engine. While processing, the length values decrement to zero. If both lengths are zero, the data stream is finished, and a new context is requested. For basic AES modes (ECB/CBC/CTR/ICM/CFB/OFB), a crypto length of ‘0’ can be written if the context DMA is disabled. Writing a zero length results in continued data requests until a new context is written. For the other modes (GCM and CCM) no (new) data requests are done if the length decrements to or equals zero.
It is advised to write a new length per packet. If the length registers decrement to zero, no new data is processed until a new context or length value is written.
When writing a new context without writing the length registers, the length register values from the previous context are reused.

Figure 10-56 C_LENGTH_0
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 10-53 C_LENGTH_0 Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hBits [60:0] of the crypto length registers (LSW and MSW) store the cryptographic data length in bytes for all modes. Once processing with this context is started, this length decrements to zero. Data lengths up to (261-1) bytes are allowed.
For GCM, any value up to 236-32 bytes can be used. This is because a 32-bit counter mode is used; the maximum number of 128-bit blocks is 232-2, resulting in a maximum number of bytes of 236-32.
A write to this register triggers the engine to start using this context. This is valid for all modes except GCM and CCM.
Note that for the combined modes, this length does not include the authentication only data; the authentication length is specified in the AES_AAD_LENGTH register below.
All modes must have a length > 0. For the combined modes, it is allowed to have one of the lengths equal to zero.
For the basic encryption modes (ECB/CBC/CTR/ICM/CFB/OFB) it is allowed to program zero to the length field; in that case the length is assumed infinite.
All data must be byte (8-bit) aligned for stream cipher modes; bit aligned data streams are not supported. For block cipher modes, the data length must be programmed in multiples of the block cipher size, 16 bytes.

10.3.47 C_LENGTH_1 (Offset = 1158h) [Reset = 00000000h]

C_LENGTH_1 is shown in Figure 10-57 and described in Table 10-54.

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Crypto data length (MSW). These registers buffer the Length values to the engine. While processing, the length values decrement to zero. If both lengths are zero, the data stream is finished, and a new context is requested. For basic AES modes (ECB/CBC/CTR/ICM/CFB/OFB), a crypto length of ‘0’ can be written if the context DMA is disabled. Writing a zero length results in continued data requests until a new context is written. For the other modes (GCM and CCM) no (new) data requests are done if the length decrements to or equals zero.
It is advised to write a new length per packet. If the length registers decrement to zero, no new data is processed until a new context or length value is written.
When writing a new context without writing the length registers, the length register values from the previous context are reused.

Figure 10-57 C_LENGTH_1
313029282726252423222120191817161514131211109876543210
RESERVEDDATA
R-0hW-0h
Table 10-54 C_LENGTH_1 Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0h
28-0DATAW0hBits [60:0] of the crypto length registers (LSW and MSW) store the cryptographic data length in bytes for all modes. Once processing with this context is started, this length decrements to zero. Data lengths up to (261-1) bytes are allowed.
For GCM, any value up to 236-32 bytes can be used. This is because a 32-bit counter mode is used; the maximum number of 128-bit blocks is 232-2, resulting in a maximum number of bytes of 236-32.
A write to this register triggers the engine to start using this context. This is valid for all modes except GCM and CCM.
Note that for the combined modes, this length does not include the authentication only data; the authentication length is specified in the AES_AAD_LENGTH register below.
All modes must have a length > 0. For the combined modes, it is allowed to have one of the lengths equal to zero.
For the basic encryption modes (ECB/CBC/CTR/ICM/CFB/OFB) it is allowed to program zero to the length field; in that case the length is assumed infinite.
All data must be byte (8-bit) aligned for stream cipher modes; bit aligned data streams are not supported. For block cipher modes, the data length must be programmed in multiples of the block cipher size, 16 bytes.

10.3.48 AAD_LENGTH (Offset = 115Ch) [Reset = 00000000h]

AAD_LENGTH is shown in Figure 10-58 and described in Table 10-55.

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AAD Data Length

Figure 10-58 AAD_LENGTH
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 10-55 AAD_LENGTH Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hBits [31:0] of the authentication length register store the authentication data length in bytes for combined modes only (GCM or CCM)
Supported AAD-lengths for CCM are from 0 to (216-28) bytes. For GCM any value up to (232-1) bytes can be used. Once processing with this context is started, this length decrements to zero.
A write to this register triggers the engine to start using this context for GCM and CCM.

10.3.49 DATA0 (Offset = 1160h) [Reset = 00000000h]

DATA0 is shown in Figure 10-59 and described in Table 10-56.

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Data input (LSW) / Data output (LSW)\. The Data Input/Output Registers buffer the input/output data blocks to/from the engine. Notice that the data input buffer (AES_DATA_IN_n) and data output buffer (AES_DATA_OUT_n) are mapped to the same address locations. Writes to these addresses load the Input Buffer while reads pull from the Output Buffer. Therefore, for write access, the data input buffer is written; for read access, the data output buffer is read. The data input buffer must be written prior to starting an operation. The data output buffer contains valid data on completion of an operation. All writes from, and reads to, these registers are tracked independently per direction. Therefore, any 128-bit data block can be split over multiple 32-bit word transfers, which can be mixed with other transfers over the external interface.

Figure 10-59 DATA0
313029282726252423222120191817161514131211109876543210
DATA
R/W-0h
Table 10-56 DATA0 Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0hData

10.3.50 DATA1 (Offset = 1164h) [Reset = 00000000h]

DATA1 is shown in Figure 10-60 and described in Table 10-57.

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Data input / Data output. The Data Input/Output Registers buffer the input/output data blocks to/from the engine. Notice that the data input buffer (AES_DATA_IN_n) and data output buffer (AES_DATA_OUT_n) are mapped to the same address locations. Writes to these addresses load the Input Buffer while reads pull from the Output Buffer. Therefore, for write access, the data input buffer is written; for read access, the data output buffer is read. The data input buffer must be written prior to starting an operation. The data output buffer contains valid data on completion of an operation. All writes from, and reads to, these registers are tracked independently per direction. Therefore, any 128-bit data block can be split over multiple 32-bit word transfers, which can be mixed with other transfers over the external interface.

Figure 10-60 DATA1
313029282726252423222120191817161514131211109876543210
DATA
R/W-0h
Table 10-57 DATA1 Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0hData

10.3.51 DATA2 (Offset = 1168h) [Reset = 00000000h]

DATA2 is shown in Figure 10-61 and described in Table 10-58.

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Data input / Data output. The Data Input/Output Registers buffer the input/output data blocks to/from the engine. Notice that the data input buffer (AES_DATA_IN_n) and data output buffer (AES_DATA_OUT_n) are mapped to the same address locations. Writes to these addresses load the Input Buffer while reads pull from the Output Buffer. Therefore, for write access, the data input buffer is written; for read access, the data output buffer is read. The data input buffer must be written prior to starting an operation. The data output buffer contains valid data on completion of an operation. All writes from, and reads to, these registers are tracked independently per direction. Therefore, any 128-bit data block can be split over multiple 32-bit word transfers, which can be mixed with other transfers over the external interface.

Figure 10-61 DATA2
313029282726252423222120191817161514131211109876543210
DATA
R/W-0h
Table 10-58 DATA2 Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0hData

10.3.52 DATA3 (Offset = 116Ch) [Reset = 00000000h]

DATA3 is shown in Figure 10-62 and described in Table 10-59.

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Data input (MSW) / Data output (MSW). The Data Input/Output Registers buffer the input/output data blocks to/from the engine. Notice that the data input buffer (AES_DATA_IN_n) and data output buffer (AES_DATA_OUT_n) are mapped to the same address locations. Writes to these addresses load the Input Buffer while reads pull from the Output Buffer. Therefore, for write access, the data input buffer is written; for read access, the data output buffer is read. The data input buffer must be written prior to starting an operation. The data output buffer contains valid data on completion of an operation. All writes from, and reads to, these registers are tracked independently per direction. Therefore, any 128-bit data block can be split over multiple 32-bit word transfers, which can be mixed with other transfers over the external interface.

Figure 10-62 DATA3
313029282726252423222120191817161514131211109876543210
DATA
R/W-0h
Table 10-59 DATA3 Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0hData

10.3.53 TAG0 (Offset = 1170h) [Reset = 00000000h]

TAG0 is shown in Figure 10-63 and described in Table 10-60.

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Hash result (LSW). These registers buffer the TAG from the engine. The registers are shared with the intermediate authentication result registers but cannot be read until the processing is finished.

Figure 10-63 TAG0
313029282726252423222120191817161514131211109876543210
DATA
R-0h
Table 10-60 TAG0 Field Descriptions
BitFieldTypeResetDescription
31-0DATAR0hFor a CPU read operation, these registers contain the last 128-bit TAG output of the engine; the TAG is available until the next context is written.
This register will only contain valid data if the TAG is available, when the ‘saved_context_ready’ or ‘get_digest’ bit from AES_CTRL register is set. In case of get_digest, the output will be an intermediate TAG for CCM or GCM operation continuation. During processing or for operations/modes that do not return a TAG, reads from this register returns data from the IV register. For operations that do return a TAG in the IV register, the IV register must be accessed directly.

10.3.54 TAG1 (Offset = 1174h) [Reset = 00000000h]

TAG1 is shown in Figure 10-64 and described in Table 10-61.

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Hash result. These registers buffer the TAG from the engine. The registers are shared with the intermediate authentication result registers but cannot be read until the processing is finished.

Figure 10-64 TAG1
313029282726252423222120191817161514131211109876543210
DATA
R-0h
Table 10-61 TAG1 Field Descriptions
BitFieldTypeResetDescription
31-0DATAR0hFor a CPU read operation, these registers contain the last 128-bit TAG output of the engine; the TAG is available until the next context is written.
This register will only contain valid data if the TAG is available, when the ‘saved_context_ready’ or ‘get_digest’ bit from AES_CTRL register is set. In case of get_digest, the output will be an intermediate TAG for CCM or GCM operation continuation. During processing or for operations/modes that do not return a TAG, reads from this register returns data from the IV register. For operations that do return a TAG in the IV register, the IV register must be accessed directly.

10.3.55 TAG2 (Offset = 1178h) [Reset = 00000000h]

TAG2 is shown in Figure 10-65 and described in Table 10-62.

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Hash result. These registers buffer the TAG from the engine. The registers are shared with the intermediate authentication result registers but cannot be read until the processing is finished.

Figure 10-65 TAG2
313029282726252423222120191817161514131211109876543210
DATA
R-0h
Table 10-62 TAG2 Field Descriptions
BitFieldTypeResetDescription
31-0DATAR0hFor a CPU read operation, these registers contain the last 128-bit TAG output of the engine; the TAG is available until the next context is written.
This register will only contain valid data if the TAG is available, when the ‘saved_context_ready’ or ‘get_digest’ bit from AES_CTRL register is set. In case of get_digest, the output will be an intermediate TAG for CCM or GCM operation continuation. During processing or for operations/modes that do not return a TAG, reads from this register returns data from the IV register. For operations that do return a TAG in the IV register, the IV register must be accessed directly.

10.3.56 TAG3 (Offset = 117Ch) [Reset = 00000000h]

TAG3 is shown in Figure 10-66 and described in Table 10-63.

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Hash result (MSW). These registers buffer the TAG from the engine. The registers are shared with the intermediate authentication result registers but cannot be read until the processing is finished.

Figure 10-66 TAG3
313029282726252423222120191817161514131211109876543210
DATA
R-0h
Table 10-63 TAG3 Field Descriptions
BitFieldTypeResetDescription
31-0DATAR0hFor a CPU read operation, these registers contain the last 128-bit TAG output of the engine; the TAG is available until the next context is written.
This register will only contain valid data if the TAG is available, when the ‘saved_context_ready’ or ‘get_digest’ bit from AES_CTRL register is set. In case of get_digest, the output will be an intermediate TAG for CCM or GCM operation continuation. During processing or for operations/modes that do not return a TAG, reads from this register returns data from the IV register. For operations that do return a TAG in the IV register, the IV register must be accessed directly.

10.3.57 STATUS (Offset = 1180h) [Reset = 00000000h]

STATUS is shown in Figure 10-67 and described in Table 10-64.

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Status register

Figure 10-67 STATUS
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDKEYWR
R-0hR-0h
Table 10-64 STATUS Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h
0KEYWRR0hKey write status. 0 - user write to KEY register is allowed. 1 - user write to KEY register is ignored.
In order to allow user write, perform a module reset.
0h = User write to KEY MMR is allowed
1h = User write to KEY MMR is disabled. Writing has no effect.

10.3.58 DATA_IN (Offset = 1184h) [Reset = 00000000h]

DATA_IN is shown in Figure 10-68 and described in Table 10-65.

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Data-in register: alias for DATA0/1/2/3 at a single address for DMA addressing

Figure 10-68 DATA_IN
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 10-65 DATA_IN Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hData input word

10.3.59 DATA_OUT (Offset = 1188h) [Reset = 00000000h]

DATA_OUT is shown in Figure 10-69 and described in Table 10-66.

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Data-out register: alias for DATA0/1/2/3 at a single address for DMA addressing

Figure 10-69 DATA_OUT
313029282726252423222120191817161514131211109876543210
DATA
R-0h
Table 10-66 DATA_OUT Field Descriptions
BitFieldTypeResetDescription
31-0DATAR0hData output word

10.3.60 FORCE_IN_AV (Offset = 11D0h) [Reset = 00000000h]

FORCE_IN_AV is shown in Figure 10-70 and described in Table 10-67.

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Data control register for input data. This write-only register provides a means to force the availability of the input data buffer of the engine.

Figure 10-70 FORCE_IN_AV
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 10-67 FORCE_IN_AV Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hAny write to this register forces the input data buffer to valid and will force the engine to start processing this data. The data written here is not used. The core must be configured to have input and output data acknowledge be I/O register based

10.3.61 CCM_ALN_WRD (Offset = 11D4h) [Reset = 00000000h]

CCM_ALN_WRD is shown in Figure 10-71 and described in Table 10-68.

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AES-CCM AAD alignment data word. This register provides a means to access an internal register that stores alignment data bytes during the AAD phase of AES-CCM processing. This register needs to be read and stored when an AES-CCM operation is interrupted during the AAD phase. This value needs to be restored by writing this register, when resuming that AES-CCM operation in a later session.

Figure 10-71 CCM_ALN_WRD
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 10-68 CCM_ALN_WRD Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hThis register provides a means to access an internal register that stores alignment data bytes during the AAD phase of AES-CCM processing. This register needs to be read and stored when an AES-CCM operation is interrupted during the AAD phase. This value needs to be restored by writing this register, when resuming that AES-CCM operation in a later session.

10.3.62 BLK_CNT0 (Offset = 11D8h) [Reset = 00000000h]

BLK_CNT0 is shown in Figure 10-72 and described in Table 10-69.

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Internal block counter (LSW). This register along with BLK_CNT1 register provides access to the internal data block counter of the engine. This counter keeps track of the number of data blocks during AES-CCM and AES-GCM operations. Reading and writing this counter allows interruption and resuming of long CCM or GCM operations. Note that internally, the block counter is used for AAD data as well as encryption/decryption data. Interruption and resuming is only supported in the encryption/decryption data phase and not during AAD.

Figure 10-72 BLK_CNT0
313029282726252423222120191817161514131211109876543210
DATA
R/W-0h
Table 10-69 BLK_CNT0 Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0hInternal block counter for AES GCM and CCM operations.
These bits read the block count value that represents the number of blocks to go. This value is valid with saved_context_ready after a request for an intermediate GCM/CCM digest.
Writing these registers will restore the internal block counter to the programmed value. This only needs to be done to prepare the engine to continue processing of an interrupted GCM or CCM operation.
Also refer to the get_digest and gcm_ccm_continue bits in AES_CTRL register.

10.3.63 BLK_CNT1 (Offset = 11DCh) [Reset = 00000000h]

BLK_CNT1 is shown in Figure 10-73 and described in Table 10-70.

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Internal block counter (MSW). This register along with BLK_CNT0 register provides access to the internal data block counter of the engine. This counter keeps track of the number of data blocks during AES-CCM and AES-GCM operations. Reading and writing this counter allows interruption and resuming of long CCM or GCM operations. Note that internally, the block counter is used for AAD data as well as encryption/decryption data. Interruption and resuming is only supported in the encryption/decryption data phase and not during AAD.

Figure 10-73 BLK_CNT1
313029282726252423222120191817161514131211109876543210
RESERVEDDATA
R-0hR/W-0h
Table 10-70 BLK_CNT1 Field Descriptions
BitFieldTypeResetDescription
31-24RESERVEDR0h
23-0DATAR/W0hInternal block counter for AES GCM and CCM operations.
These bits read the block count value that represents the number of blocks to go. This value is valid with saved_context_ready after a request for an intermediate GCM/CCM digest.
Writing these registers will restore the internal block counter to the programmed value. This only needs to be done to prepare the engine to continue processing of an interrupted GCM or CCM operation.
Also refer to the get_digest and gcm_ccm_continue bits in AES_CTRL register.

10.3.64 DMA_HS (Offset = 11F4h) [Reset = 00000000h]

DMA_HS is shown in Figure 10-74 and described in Table 10-71.

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Control register for DMA handshaking

Figure 10-74 DMA_HS
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDDMA_DATA_ACK
R-0hR/W-0h
Table 10-71 DMA_HS Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h
0DMA_DATA_ACKR/W0hWhen this bit is 0b, input and output data acknowledge is I/O register based, as specified in the description of the AES_DATA_IN_n / AES_DATA_OUT_n registers.
When this bit is 1b, input and output data acknowledge is based on DMA handshake signals.
0h = Disable DMA based data handshake
1h = Enables DMA based handshake