SLAU847F October   2022  â€“ March 2026 MSPM0L1105 , MSPM0L1106 , MSPM0L1116 , MSPM0L1116-Q1 , MSPM0L1117 , MSPM0L1227 , MSPM0L1227-Q1 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346 , MSPM0L2116 , MSPM0L2117 , MSPM0L2227 , MSPM0L2227-Q1 , MSPM0L2228 , MSPM0L2228-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation
    5.     Support Resources
    6.     Trademarks
  3. 1 Architecture
    1. 1.1 Architecture Overview
    2. 1.2 Bus Organization
    3. 1.3 Platform Memory Map
      1. 1.3.1 Code Region
      2. 1.3.2 SRAM Region
      3. 1.3.3 Peripheral Region
      4. 1.3.4 Subsystem Region
      5. 1.3.5 System PPB Region
    4. 1.4 Boot Configuration
      1. 1.4.1 Configuration Memory (NONMAIN)
        1. 1.4.1.1 CRC-Backed Configuration Data
        2. 1.4.1.2 16-bit Pattern Match for Critical Fields
      2. 1.4.2 Boot Configuration Routine (BCR)
        1. 1.4.2.1 Serial Wire Debug Related Policies
          1. 1.4.2.1.1 SWD Security Level 0
          2. 1.4.2.1.2 SWD Security Level 1
          3. 1.4.2.1.3 SWD Security Level 2
        2. 1.4.2.2 SWD Mass Erase and Factory Reset Commands
        3. 1.4.2.3 Flash Memory Protection and Integrity Related Policies
          1. 1.4.2.3.1 Locking the Application (MAIN) Flash Memory
          2. 1.4.2.3.2 Locking the Configuration (NONMAIN) Flash Memory
          3. 1.4.2.3.3 Static Write Protection NONMAIN Fields
        4. 1.4.2.4 Application CRC Verification
        5. 1.4.2.5 Fast Boot
        6. 1.4.2.6 Bootstrap Loader (BSL) Enable/Disable Policy
          1. 1.4.2.6.1 BSL Enable
      3. 1.4.3 Bootstrap Loader (BSL)
        1. 1.4.3.1 GPIO Invoke
        2. 1.4.3.2 Bootstrap Loader (BSL) Security Policies
          1. 1.4.3.2.1 BSL Access Password
          2. 1.4.3.2.2 BSL Read-out Policy
          3. 1.4.3.2.3 BSL Security Alert Policy
        3. 1.4.3.3 Application Version
        4. 1.4.3.4 BSL Triggered Mass Erase and Factory Reset
      4. 1.4.4 NONMAIN Layout Types
      5. 1.4.5 NONMAIN_TYPEA Registers
      6. 1.4.6 NONMAIN_TYPEC Registers
      7. 1.4.7 NONMAIN_TYPEE Registers
    5. 1.5 Factory Constants
      1. 1.5.1 FACTORYREGION Layout Types
      2. 1.5.2 FACTORYREGION_TYPEA Registers
      3. 1.5.3 FACTORYREGION_TYPEC Registers
      4. 1.5.4 FACTORYREGION_TYPED Registers
      5. 1.5.5 FACTORYREGION_TYPEE Registers
  4. 2 PMCU
    1. 2.1 PMCU Overview
      1. 2.1.1 Power Domains
      2. 2.1.2 Operating Modes
        1. 2.1.2.1 RUN Mode
        2. 2.1.2.2 SLEEP Mode
        3. 2.1.2.3 STOP Mode
        4. 2.1.2.4 STANDBY Mode
        5. 2.1.2.5 SHUTDOWN Mode
        6. 2.1.2.6 Supported Functionality by Operating Mode
        7. 2.1.2.7 Suspended Low-Power Mode Operation
    2. 2.2 Power Management (PMU)
      1. 2.2.1 Power Supply
      2. 2.2.2 Core Regulator
      3. 2.2.3 Supply Supervisors
        1. 2.2.3.1 Power-on Reset (POR)
        2. 2.2.3.2 Brownout Reset (BOR)
        3. 2.2.3.3 POR and BOR Behavior During Supply Changes
      4. 2.2.4 Bandgap Reference
      5. 2.2.5 VBOOST for Analog Muxes
      6. 2.2.6 Peripheral Enable
        1. 2.2.6.1 Automatic Peripheral Disable in Low Power Modes
    3. 2.3 Clock Module (CKM)
      1. 2.3.1 Oscillators
        1. 2.3.1.1 Internal Low-Frequency Oscillator (LFOSC)
        2. 2.3.1.2 Internal System Oscillator (SYSOSC)
          1. 2.3.1.2.1 SYSOSC Gear Shift
          2. 2.3.1.2.2 SYSOSC Frequency
          3. 2.3.1.2.3 SYSOSC Frequency Correction Loop
            1. 2.3.1.2.3.1 SYSOSC FCL in External Resistor Mode (ROSC)
            2. 2.3.1.2.3.2 SYSOSC FCL in Internal Resistor Mode
          4. 2.3.1.2.4 SYSOSC User Trim Procedure
          5. 2.3.1.2.5 Disabling SYSOSC
        3. 2.3.1.3 Low Frequency Crystal Oscillator (LFXT)
        4. 2.3.1.4 LFCLK_IN (Digital Clock)
        5. 2.3.1.5 High Frequency Crystal Oscillator (HFXT)
        6. 2.3.1.6 HFCLK_IN (Digital clock)
      2. 2.3.2 Clocks
        1. 2.3.2.1  MCLK (Main Clock) Tree
        2. 2.3.2.2  CPUCLK (Processor Clock)
        3. 2.3.2.3  ULPCLK (Low-Power Clock)
        4. 2.3.2.4  MFCLK (Middle Frequency Clock)
        5. 2.3.2.5  MFPCLK (Middle Frequency Precision Clock)
        6. 2.3.2.6  LFCLK (Low-Frequency Clock)
        7. 2.3.2.7  HFCLK (High-Frequency External Clock)
        8. 2.3.2.8  HSCLK (High Speed Clock)
        9. 2.3.2.9  ADCCLK (ADC Sample Period Clock)
        10. 2.3.2.10 CANCLK (CAN-FD Functional Clock)
        11. 2.3.2.11 RTCCLK (RTC Clock)
        12. 2.3.2.12 External Clock Output (CLK_OUT)
        13. 2.3.2.13 Direct Clock Connections for Infrastructure
      3. 2.3.3 Clock Tree
        1. 2.3.3.1 Peripheral Clock Source Selection
      4. 2.3.4 Clock Monitors
        1. 2.3.4.1 LFCLK Monitor
        2. 2.3.4.2 MCLK Monitor
        3. 2.3.4.3 Startup Monitors
          1. 2.3.4.3.1 LFOSC Startup Monitor
          2. 2.3.4.3.2 LFXT Startup Monitor
          3. 2.3.4.3.3 HFCLK Startup Monitor
          4. 2.3.4.3.4 HSCLK Status
      5. 2.3.5 Frequency Clock Counter (FCC)
        1. 2.3.5.1 Using the FCC
        2. 2.3.5.2 FCC Frequency Computation and Accuracy
    4. 2.4 System Controller (SYSCTL)
      1. 2.4.1  Resets and Device Initialization
        1. 2.4.1.1 Reset Levels
          1. 2.4.1.1.1 Power-on Reset (POR) Reset Level
          2. 2.4.1.1.2 Brownout Reset (BOR) Reset Level
          3. 2.4.1.1.3 Boot Reset (BOOTRST) Reset Level
          4. 2.4.1.1.4 System Reset (SYSRST) Reset Level
          5. 2.4.1.1.5 CPU-only Reset (CPURST) Reset Level
        2. 2.4.1.2 Initial Conditions After Power-Up
        3. 2.4.1.3 NRST Pin
        4. 2.4.1.4 SWD Pins
        5. 2.4.1.5 Generating Resets in Software
        6. 2.4.1.6 Reset Cause
        7. 2.4.1.7 Peripheral Reset Control
        8. 2.4.1.8 Boot Fail Handling
      2. 2.4.2  Operating Mode Selection
      3. 2.4.3  Asynchronous Fast Clock Requests
      4. 2.4.4  SRAM Write Protection
      5. 2.4.5  Flash Wait States
      6. 2.4.6  Flash Bank Address Swap
      7. 2.4.7  Shutdown Mode Handling (if present)
      8. 2.4.8  Configuration Lockout
      9. 2.4.9  System Status
      10. 2.4.10 Error Handling
      11. 2.4.11 SYSCTL Events
        1. 2.4.11.1 CPU Interrupt Event (CPU_INT)
        2. 2.4.11.2 Nonmaskable Interrupt Event (NMI)
    5. 2.5 SYSCTL Layout Types
    6. 2.6 SYSCTL_TYPEA Registers
    7. 2.7 SYSCTL_TYPEB Registers
    8. 2.8 SYSCTL_TYPEC Registers
    9. 2.9 Quick Start Reference
      1. 2.9.1 Default Device Configuration
      2. 2.9.2 Leveraging MFCLK
      3. 2.9.3 Optimizing Power Consumption in STOP Mode
      4. 2.9.4 Optimizing Power Consumption in STANDBY Mode
      5. 2.9.5 Increasing MCLK Precision
      6. 2.9.6 High Speed Clock (SYSPLL, HFCLK) Handling in Low-Power Modes
      7. 2.9.7 Optimizing for Lowest Wakeup Latency
      8. 2.9.8 Optimizing for Lowest Peak Current in RUN/SLEEP Mode
  5. 3 CPU
    1. 3.1 Overview
    2. 3.2 Arm Cortex-M0+ CPU
      1. 3.2.1 CPU Register File
      2. 3.2.2 Stack Behavior
      3. 3.2.3 Execution Modes and Privilege Levels
      4. 3.2.4 Address Space and Supported Data Sizes
    3. 3.3 Interrupts and Exceptions
      1. 3.3.1 Peripheral Interrupts (IRQs)
        1. 3.3.1.1 Nested Vectored Interrupt Controller (NVIC)
        2. 3.3.1.2 Interrupt Groups
        3. 3.3.1.3 Wake Up Controller (WUC)
      2. 3.3.2 Interrupt and Exception Table
      3. 3.3.3 Processor Lockup Scenario
    4. 3.4 CPU Peripherals
      1. 3.4.1 System Control Block (SCB)
      2. 3.4.2 System Tick Timer (SysTick)
    5. 3.5 Read-Only Memory (ROM)
    6. 3.6 CPUSS Registers
    7. 3.7 WUC Registers
  6. 4 SECURITY
    1. 4.1 Overview
      1. 4.1.1 Secure Boot
      2. 4.1.2 Customer Secure Code (CSC)
    2. 4.2 Boot and Startup Sequence
      1. 4.2.1 CSC Programming Overview
    3. 4.3 Secure Key Storage
    4. 4.4 Flash Memory Protection
      1. 4.4.1 Bank Swapping
      2. 4.4.2 Write Protection
      3. 4.4.3 Read-Execute Protection
      4. 4.4.4 IP Protection
      5. 4.4.5 Data Bank Protection
      6. 4.4.6 Hardware Monotonic Counter
    5. 4.5 SRAM Protection
    6. 4.6 SECURITY Registers
  7. 5 Direct Memory Access (DMA)
    1. 5.1 DMA Overview
    2. 5.2 DMA Operation
      1. 5.2.1  Addressing Modes
      2. 5.2.2  Channel Types
      3. 5.2.3  Transfer Modes
        1. 5.2.3.1 Single Transfer
        2. 5.2.3.2 Block Transfer
        3. 5.2.3.3 Repeated Single Transfer
        4. 5.2.3.4 Repeated Block Transfer
        5. 5.2.3.5 Stride Mode
      4. 5.2.4  Extended Modes
        1. 5.2.4.1 Fill Mode
        2. 5.2.4.2 Table Mode
      5. 5.2.5  Initiating DMA Transfers
      6. 5.2.6  Stopping DMA Transfers
      7. 5.2.7  Channel Priorities
      8. 5.2.8  Burst Block Mode
      9. 5.2.9  Using DMA with System Interrupts
      10. 5.2.10 DMA Controller Interrupts
      11. 5.2.11 DMA Trigger Event Status
      12. 5.2.12 DMA Operating Mode Support
        1. 5.2.12.1 Transfer in RUN Mode
        2. 5.2.12.2 Transfer in SLEEP Mode
        3. 5.2.12.3 Transfer in STOP Mode
        4. 5.2.12.4 Transfers in STANDBY Mode
      13. 5.2.13 DMA Address and Data Errors
      14. 5.2.14 Interrupt and Event Support
    3. 5.3 DMA Registers
  8. 6 NVM (Flash)
    1. 6.1 NVM Overview
      1. 6.1.1 Key Features
      2. 6.1.2 System Components
      3. 6.1.3 Terminology
    2. 6.2 Flash Memory Bank Organization
      1. 6.2.1 Banks
      2. 6.2.2 Flash Memory Regions
      3. 6.2.3 Addressing
        1. 6.2.3.1 Flash Memory Map
      4. 6.2.4 Memory Organization Examples
    3. 6.3 Flash Controller
      1. 6.3.1 Overview of Flash Controller Commands
      2. 6.3.2 NOOP Command
      3. 6.3.3 PROGRAM Command
        1. 6.3.3.1 Program Bit Masking Behavior
        2. 6.3.3.2 Programming Less Than One Flash Word
        3. 6.3.3.3 Target Data Alignment (Devices with Single Flash Word Programming Only)
        4. 6.3.3.4 Target Data Alignment (Devices With Multiword Programming)
        5. 6.3.3.5 Executing a PROGRAM Operation
      4. 6.3.4 ERASE Command
        1. 6.3.4.1 Erase Sector Masking Behavior
        2. 6.3.4.2 Executing an ERASE Operation
      5. 6.3.5 READVERIFY Command
        1. 6.3.5.1 Executing a READVERIFY Operation
      6. 6.3.6 BLANKVERIFY Command
        1. 6.3.6.1 Executing a BLANKVERIFY Operation
      7. 6.3.7 Command Diagnostics
        1. 6.3.7.1 Command Status
        2. 6.3.7.2 Address Translation
        3. 6.3.7.3 Pulse Counts
      8. 6.3.8 Overriding the System Address With a Bank ID, Region ID, and Bank Address
      9. 6.3.9 FLASHCTL Events
        1. 6.3.9.1 CPU Interrupt Event Publisher
    4. 6.4 Write Protection
      1. 6.4.1 Write Protection Resolution
      2. 6.4.2 Static Write Protection
      3. 6.4.3 Dynamic Write Protection
        1. 6.4.3.1 Configuring Protection for the MAIN Region
        2. 6.4.3.2 Configuring Protection for the NONMAIN Region
    5. 6.5 Read Interface
      1. 6.5.1 Bank Address Swapping
    6. 6.6 FLASHCTL Registers
  9. 7 Events
    1. 7.1 Events Overview
      1. 7.1.1 Event Publisher
      2. 7.1.2 Event Subscriber
      3. 7.1.3 Event Fabric Routing
        1. 7.1.3.1 CPU Interrupt Event Route (CPU_INT)
        2. 7.1.3.2 DMA Trigger Event Route (DMA_TRIGx)
        3. 7.1.3.3 Generic Event Route (GEN_EVENTx)
      4. 7.1.4 Event Routing Map
      5. 7.1.5 Event Propagation Latency
    2. 7.2 Events Operation
      1. 7.2.1 CPU Interrupt
      2. 7.2.2 DMA Trigger
      3. 7.2.3 Peripheral to Peripheral Event
      4. 7.2.4 Extended Module Description Register
      5. 7.2.5 Using Event Registers
        1. 7.2.5.1 Event Registers
        2. 7.2.5.2 Configuring Events
        3. 7.2.5.3 Responding to CPU Interrupts in Application Software
        4. 7.2.5.4 Hardware Event Handling
  10. 8 IOMUX
    1. 8.1 IOMUX Overview
      1. 8.1.1 IO Types and Analog Sharing
    2. 8.2 IOMUX Operation
      1. 8.2.1 Peripheral Function (PF) Assignment
      2. 8.2.2 Logic High to Hi-Z Conversion
      3. 8.2.3 Logic Inversion
      4. 8.2.4 SHUTDOWN Mode Wakeup Logic
      5. 8.2.5 Pullup/Pulldown Resistors
      6. 8.2.6 Drive Strength Control
      7. 8.2.7 Hysteresis and Logic Level Control
    3. 8.3 IOMUX Registers
  11. 9 General-Purpose Input/Output (GPIO)
    1. 9.1 GPIO Overview
    2. 9.2 GPIO Operation
      1. 9.2.1 GPIO Ports
      2. 9.2.2 GPIO Read/Write Interface
      3. 9.2.3 GPIO Input Glitch Filtering and Synchronization
      4. 9.2.4 GPIO Fast Wake
      5. 9.2.5 GPIO DMA Interface
      6. 9.2.6 Event Publishers and Subscribers
    3. 9.3 GPIO Registers
  12. 10AES
    1. 10.1 AES Overview
      1. 10.1.1 AESADV Performance
    2. 10.2 AESADV Operation
      1. 10.2.1 Loading the Key
      2. 10.2.2 Writing Input Data
      3. 10.2.3 Reading Output Data
      4. 10.2.4 Operation Descriptions
        1. 10.2.4.1 Single Block Operation
        2. 10.2.4.2 Electronic Codebook (ECB) Mode
          1. 10.2.4.2.1 ECB Encryption
          2. 10.2.4.2.2 ECB Decryption
        3. 10.2.4.3 Cipher Block Chaining (CBC) Mode
          1. 10.2.4.3.1 CBC Encryption
          2. 10.2.4.3.2 CBC Decryption
        4. 10.2.4.4 Output Feedback (OFB) Mode
          1. 10.2.4.4.1 OFB Encryption
          2. 10.2.4.4.2 OFB Decryption
        5. 10.2.4.5 Cipher Feedback (CFB) Mode
          1. 10.2.4.5.1 CFB Encryption
          2. 10.2.4.5.2 CFB Decryption
        6. 10.2.4.6 Counter (CTR) Mode
          1. 10.2.4.6.1 CTR Encryption
          2. 10.2.4.6.2 CTR Decryption
        7. 10.2.4.7 Galois Counter (GCM) Mode
          1. 10.2.4.7.1 GHASH Operation
          2. 10.2.4.7.2 GCM Operating Modes
            1. 10.2.4.7.2.1 Autonomous GCM Operation
              1. 10.2.4.7.2.1.1 GMAC
            2. 10.2.4.7.2.2 GCM With Pre-Calculations
            3. 10.2.4.7.2.3 GCM Operation With Precalculated H- and Y0-Encrypted Forced to Zero
        8. 10.2.4.8 Counter With Cipher Block Chaining Message Authentication Code (CCM)
          1. 10.2.4.8.1 CCM Operation
      5. 10.2.5 AES Events
        1. 10.2.5.1 CPU Interrupt Event Publisher (CPU_EVENT)
        2. 10.2.5.2 DMA Trigger Event Publisher (DMA_TRIG_DATAIN)
        3. 10.2.5.3 DMA Trigger Event Publisher (DMA_TRIG_DATAOUT)
    3. 10.3 AESADV Registers
  13. 11CRC
    1. 11.1 CRC Overview
      1. 11.1.1 CRC16-CCITT
      2. 11.1.2 CRC32-ISO3309
    2. 11.2 CRC Operation
      1. 11.2.1 CRC Generator Implementation
      2. 11.2.2 Configuration
        1. 11.2.2.1 Polynomial Selection
        2. 11.2.2.2 Bit Order
        3. 11.2.2.3 Byte Swap
        4. 11.2.2.4 Byte Order
        5. 11.2.2.5 CRC C Library Compatibility
    3. 11.3 CRCP0 Registers
  14. 12Keystore
    1. 12.1 Overview
    2. 12.2 Detailed Description
    3. 12.3 KEYSTORECTL Registers
  15. 13TRNG
    1. 13.1 TRNG Overview
    2. 13.2 TRNG Operation
      1. 13.2.1 TRNG Generation Data Path
      2. 13.2.2 Clock Configuration and Output Rate
      3. 13.2.3 Behavior in Low Power Modes
      4. 13.2.4 Health Tests
        1. 13.2.4.1 Digital Block Startup Self-Test
        2. 13.2.4.2 Analog Block Startup Self-Test
        3. 13.2.4.3 Runtime Health Test
          1. 13.2.4.3.1 Repetition Count Test
          2. 13.2.4.3.2 Adaptive Proportion Test
          3. 13.2.4.3.3 Handling Runtime Health Test Failures
      5. 13.2.5 Configuration
        1. 13.2.5.1 TRNG State Machine
          1. 13.2.5.1.1 Changing TRNG States
        2. 13.2.5.2 Using the TRNG
        3. 13.2.5.3 TRNG Events
          1. 13.2.5.3.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 13.3 TRNG Registers
  16. 14Temperature Sensor
  17. 15ADC
    1. 15.1 ADC Overview
    2. 15.2 ADC Operation
      1. 15.2.1  ADC Core
      2. 15.2.2  Voltage Reference Options
      3. 15.2.3  Generic Resolution Modes
      4. 15.2.4  Hardware Averaging
      5. 15.2.5  ADC Clocking
      6. 15.2.6  Common ADC Use Cases
      7. 15.2.7  Power Down Behavior
      8. 15.2.8  Sampling Trigger Sources and Sampling Modes
        1. 15.2.8.1 AUTO Sampling Mode
        2. 15.2.8.2 MANUAL Sampling Mode
      9. 15.2.9  Sampling Period
      10. 15.2.10 Conversion Modes
      11. 15.2.11 Data Format
      12. 15.2.12 Advanced Features
        1. 15.2.12.1 Window Comparator
        2. 15.2.12.2 DMA and FIFO Operation
        3. 15.2.12.3 Analog Peripheral Interconnection
      13. 15.2.13 Status Register
      14. 15.2.14 ADC Events
        1. 15.2.14.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 15.2.14.2 Generic Event Publisher (GEN_EVENT)
        3. 15.2.14.3 DMA Trigger Event Publisher (DMA_TRIG)
        4. 15.2.14.4 Generic Event Subscriber (FSUB_0)
    3. 15.3 ADC12 Registers
  18. 16COMP
    1. 16.1 Comparator Overview
    2. 16.2 Comparator Operation
      1. 16.2.1  Comparator Configuration
      2. 16.2.2  Comparator Channels Selection
      3. 16.2.3  Comparator Output
      4. 16.2.4  Output Filter
      5. 16.2.5  Sampled Output Mode
      6. 16.2.6  Blanking Mode
      7. 16.2.7  Reference Voltage Generator
      8. 16.2.8  Comparator Hysteresis
      9. 16.2.9  Input SHORT Switch
      10. 16.2.10 Interrupt and Events Support
        1. 16.2.10.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 16.2.10.2 Generic Event Publisher (GEN_EVENT)
        3. 16.2.10.3 Generic Event Subscribers
    3. 16.3 COMP0 Registers
  19. 17OPA
    1. 17.1 OPA Overview
    2. 17.2 OPA Operation
      1. 17.2.1 Analog Core
      2. 17.2.2 Power Up Behavior
      3. 17.2.3 Inputs
      4. 17.2.4 Output
      5. 17.2.5 Clock Requirements
      6. 17.2.6 Chopping
      7. 17.2.7 OPA Amplifier Modes
        1. 17.2.7.1 General-Purpose Mode
        2. 17.2.7.2 Buffer Mode
        3. 17.2.7.3 OPA PGA Mode
          1. 17.2.7.3.1 Inverting PGA Mode
          2. 17.2.7.3.2 Non-inverting PGA Mode
        4. 17.2.7.4 Difference Amplifier Mode
        5. 17.2.7.5 Cascade Amplifier Mode
      8. 17.2.8 OPA Configuration Selection
      9. 17.2.9 Burnout Current Source
    3. 17.3 OA Registers
  20. 18GPAMP
    1. 18.1 GPAMP Overview
    2. 18.2 GPAMP Operation
      1. 18.2.1 Analog Core
      2. 18.2.2 Power Up Behavior
      3. 18.2.3 Inputs
      4. 18.2.4 Output
      5. 18.2.5 GPAMP Amplifier Modes
        1. 18.2.5.1 General-Purpose Mode
        2. 18.2.5.2 ADC Buffer Mode
        3. 18.2.5.3 Unity Gain Mode
      6. 18.2.6 Chopping
    3. 18.3 GPAMP Registers
  21. 19VREF
    1. 19.1 VREF Overview
    2. 19.2 VREF Operation
      1. 19.2.1 Internal Reference Generation
      2. 19.2.2 External Reference Input
      3. 19.2.3 Analog Peripheral Interface
    3. 19.3 VREF Registers
  22. 20LCD
    1. 20.1 LCD Introduction
      1. 20.1.1 LCD Operating Principle
      2. 20.1.2 Static Mode
      3. 20.1.3 2-Mux Mode
      4. 20.1.4 3-Mux Mode
      5. 20.1.5 4-Mux Mode
      6. 20.1.6 6-Mux Mode
      7. 20.1.7 8-Mux Mode
      8. 20.1.8 Introduction
      9. 20.1.9 LCD Waveforms
    2. 20.2 LCD Clocking
    3. 20.3 Voltage Generation
      1. 20.3.1  Mode 0 - Voltage Generation from external reference and external resistor divider
      2. 20.3.2  Mode 1 - Voltage Generation from AVDD and external resistor divider
      3. 20.3.3  Mode 2 - Voltage Generation from external reference and internal resistor divider
      4. 20.3.4  Mode 3 - Voltage Generation From AVDD and Internal Resistor Ladder
      5. 20.3.5  Mode 4 - Voltage Generation from charge pump with external supply
      6. 20.3.6  Mode 5 - Voltage Generation From Charge Pump With AVDD
      7. 20.3.7  Mode 6 - Voltage Generation From Charge Pump With External Reference on R13
      8. 20.3.8  Mode 7 - Voltage Generation From Charge Pump With Internal Reference on R13
      9. 20.3.9  Charge pump
      10. 20.3.10 Internal Reference Generation
    4. 20.4 Analog Mux
      1. 20.4.1 Static Mode
      2. 20.4.2 Non-Static 1/3 bias mode
      3. 20.4.3 Non-Static 1/4 bias mode
      4. 20.4.4 Low power mode switch controls
    5. 20.5 LCD Memory and output drive
      1. 20.5.1 LCD Memory organization
        1. 20.5.1.1 Memory Organization in Mux-1 to Mux-4 Modes
        2. 20.5.1.2 Memory Organization in Mux-5 to Mux-8 Modes
        3. 20.5.1.3 Configuring memory
        4. 20.5.1.4 Accessing memory and output drive
        5. 20.5.1.5 Blinking Override
    6. 20.6 IO Muxing
    7. 20.7 Interrupt Generation
    8. 20.8 Power Domains and Power Modes
    9. 20.9 LCD Registers
  23. 21UART
    1. 21.1 UART Overview
      1. 21.1.1 Purpose of the Peripheral
      2. 21.1.2 Features
      3. 21.1.3 Functional Block Diagram
    2. 21.2 UART Operation
      1. 21.2.1 Clock Control
      2. 21.2.2 Signal Descriptions
      3. 21.2.3 General Architecture and Protocol
        1. 21.2.3.1  Transmit Receive Logic
        2. 21.2.3.2  Bit Sampling
        3. 21.2.3.3  Majority Voting Feature
        4. 21.2.3.4  Baud Rate Generation
        5. 21.2.3.5  Data Transmission
        6. 21.2.3.6  Error and Status
        7. 21.2.3.7  Local Interconnect Network (LIN) Support
          1. 21.2.3.7.1 LIN Responder Transmission Delay
        8. 21.2.3.8  Flow Control
        9. 21.2.3.9  Idle-Line Multiprocessor
        10. 21.2.3.10 9-Bit UART Mode
        11. 21.2.3.11 RS-485 Support
        12. 21.2.3.12 DALI Protocol
        13. 21.2.3.13 Manchester Encoding and Decoding
        14. 21.2.3.14 IrDA Encoding and Decoding
        15. 21.2.3.15 ISO7816 Smart Card Support
        16. 21.2.3.16 Address Detection
        17. 21.2.3.17 FIFO Operation
        18. 21.2.3.18 Loopback Operation
        19. 21.2.3.19 Glitch Suppression
      4. 21.2.4 Low Power Operation
      5. 21.2.5 Reset Considerations
      6. 21.2.6 Initialization
      7. 21.2.7 Interrupt and Events Support
        1. 21.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 21.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 21.2.8 Emulation Modes
    3. 21.3 UART Registers
  24. 22I2C
    1. 22.1 I2C Overview
      1. 22.1.1 Purpose of the Peripheral
      2. 22.1.2 Features
      3. 22.1.3 Functional Block Diagram
      4. 22.1.4 Environment and External Connections
    2. 22.2 I2C Operation
      1. 22.2.1 Clock Control
        1. 22.2.1.1 Clock Select and I2C Speed
        2. 22.2.1.2 Clock Startup
      2. 22.2.2 Signal Descriptions
      3. 22.2.3 General Architecture
        1. 22.2.3.1  I2C Bus Functional Overview
        2. 22.2.3.2  START and STOP Conditions
        3. 22.2.3.3  Data Format with 7-Bit Address
        4. 22.2.3.4  Acknowledge
        5. 22.2.3.5  Repeated Start
        6. 22.2.3.6  SCL Clock Low Timeout
        7. 22.2.3.7  Clock Stretching
        8. 22.2.3.8  Dual Address
        9. 22.2.3.9  Arbitration
        10. 22.2.3.10 Multiple Controller Mode
        11. 22.2.3.11 Glitch Suppression
        12. 22.2.3.12 FIFO operation
          1. 22.2.3.12.1 Flushing Stale Tx Data in Target Mode
        13. 22.2.3.13 Loopback mode
        14. 22.2.3.14 Burst Mode
        15. 22.2.3.15 DMA Operation
        16. 22.2.3.16 Low-Power Operation
      4. 22.2.4 Protocol Descriptions
        1. 22.2.4.1 I2C Controller Mode
          1. 22.2.4.1.1 Controller Configuration
          2. 22.2.4.1.2 Controller Mode Operation
          3. 22.2.4.1.3 Read On TX Empty
        2. 22.2.4.2 I2C Target Mode
          1. 22.2.4.2.1 Target Mode Operation
      5. 22.2.5 Reset Considerations
      6. 22.2.6 Initialization
      7. 22.2.7 Interrupt and Events Support
        1. 22.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 22.2.7.2 DMA Trigger Publisher (DMA_TRIG1, DMA_TRIG0)
      8. 22.2.8 Emulation Modes
    3. 22.3 I2C Registers
  25. 23SPI
    1. 23.1 SPI Overview
      1. 23.1.1 Purpose of the Peripheral
      2. 23.1.2 Features
      3. 23.1.3 Functional Block Diagram
      4. 23.1.4 External Connections and Signal Descriptions
    2. 23.2 SPI Operation
      1. 23.2.1 Clock Control
      2. 23.2.2 General Architecture
        1. 23.2.2.1 Chip Select and Command Handling
          1. 23.2.2.1.1 Chip Select Control
          2. 23.2.2.1.2 Command Data Control
        2. 23.2.2.2 Data Format
        3. 23.2.2.3 Delayed data sampling
        4. 23.2.2.4 Clock Generation
        5. 23.2.2.5 FIFO Operation
        6. 23.2.2.6 Loopback mode
        7. 23.2.2.7 DMA Operation
        8. 23.2.2.8 Repeat Transfer mode
        9. 23.2.2.9 Low Power Mode
      3. 23.2.3 Protocol Descriptions
        1. 23.2.3.1 Motorola SPI Frame Format
        2. 23.2.3.2 Texas Instruments Synchronous Serial Frame Format
      4. 23.2.4 Reset Considerations
      5. 23.2.5 Initialization
      6. 23.2.6 Interrupt and Events Support
        1. 23.2.6.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 23.2.6.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      7. 23.2.7 Emulation Modes
    3. 23.3 SPI Registers
  26. 24UNICOMM
    1. 24.1 Overview
      1. 24.1.1 Block Diagram
    2. 24.2 Unicomm Architecture
      1. 24.2.1 Serial Peripheral Group (SPG) Configurations
        1. 24.2.1.1 I2C Pairings
      2. 24.2.2 Enables & Resets
    3. 24.3 High-Level Initialization
    4. 24.4 UNICOMM/SPGSS Registers
      1. 24.4.1 UNICOMM Registers
        1. 24.4.1.1 UNICOMM Registers
      2. 24.4.2 SPG Registers
        1. 24.4.2.1 SPGSS Registers
  27. 25UNICOMM UART
    1. 25.1 UART Overview
      1. 25.1.1 Purpose of the Peripheral
      2. 25.1.2 Features
      3. 25.1.3 Functional Block Diagram
    2. 25.2 UART Operation
      1. 25.2.1 Clock Control
      2. 25.2.2 General Architecture and Protocol
        1. 25.2.2.1 Signal Descriptions
        2. 25.2.2.2 Transmit and Receive Logic
        3. 25.2.2.3 Bit Sampling
        4. 25.2.2.4 Baud Rate Generation
        5. 25.2.2.5 Data Transmission
        6. 25.2.2.6 Error and Status
        7. 25.2.2.7 DMA Operation
        8. 25.2.2.8 Internal Loopback Operation
      3. 25.2.3 Additional Protocol and Feature Support
        1. 25.2.3.1  Local Interconnect Network (LIN) Support
          1. 25.2.3.1.1 LIN Commander Transmit
          2. 25.2.3.1.2 LIN Responder Receive
          3. 25.2.3.1.3 LIN Responder Transmission Delay
        2. 25.2.3.2  Flow Control
        3. 25.2.3.3  RS485 Support
        4. 25.2.3.4  FIFO Operation
        5. 25.2.3.5  Idle-Line Multiprocessor
        6. 25.2.3.6  9-Bit UART Mode
        7. 25.2.3.7  DALI Protocol
        8. 25.2.3.8  Manchester Encoding and Decoding
        9. 25.2.3.9  IrDA Encoding and Decoding
        10. 25.2.3.10 ISO7816 Smart Card Support
        11. 25.2.3.11 Address Detection
        12. 25.2.3.12 Glitch Suppression
      4. 25.2.4 Low Power Operation
      5. 25.2.5 Reset Considerations
      6. 25.2.6 UART Initialization
      7. 25.2.7 Interrupt and Events Support
        1. 25.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 25.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 25.2.8 Emulation Modes
    3. 25.3 UNICOMMUART Registers
  28. 26UNICOMM-I2C
    1. 26.1 UNICOMM-I2C Overview
      1. 26.1.1 Purpose of the Peripheral
      2. 26.1.2 Features
      3. 26.1.3 Functional Block Diagram
      4. 26.1.4 Environment and External Connections
    2. 26.2 UNICOMM Common Infrastructure
    3. 26.3 Peripheral Functional Description
      1. 26.3.1 Clock Control
        1. 26.3.1.1 Clock Select and I2C Speed
        2. 26.3.1.2 Clock Startup
      2. 26.3.2 Signal Descriptions
      3. 26.3.3 General Architecture
        1. 26.3.3.1  I2C Bus Functional Overview
        2. 26.3.3.2  START and STOP Conditions
        3. 26.3.3.3  Dual Address
        4. 26.3.3.4  Address Format
          1. 26.3.3.4.1 Data Format with 7-Bit Address
          2. 26.3.3.4.2 Data Format with 10-Bit Address
        5. 26.3.3.5  Acknowledge
        6. 26.3.3.6  Repeated Start
        7. 26.3.3.7  Clock Stretching
        8. 26.3.3.8  Clock Low Timeout
        9. 26.3.3.9  Burst Mode
        10. 26.3.3.10 Arbitration
        11. 26.3.3.11 Multiple Controller Mode
        12. 26.3.3.12 Glitch Suppression
        13. 26.3.3.13 DMA Operation
        14. 26.3.3.14 FIFO Operation
          1. 26.3.3.14.1 FIFO Status Flags
          2. 26.3.3.14.2 FIFO Levels
          3. 26.3.3.14.3 Clearing FIFO Contents
        15. 26.3.3.15 Suspend Communication
        16. 26.3.3.16 Low Power Operation
        17. 26.3.3.17 SMBUS 3.0 Support
          1. 26.3.3.17.1 Quick Command
          2. 26.3.3.17.2 SMBUS Enhanced Acknowledge Control
          3. 26.3.3.17.3 Clock Low Timeout Detection
          4. 26.3.3.17.4 Clock High Timeout Detection
          5. 26.3.3.17.5 Cumulative Clock Low Extended Timeout
          6. 26.3.3.17.6 Packet Error Checking (PEC)
          7. 26.3.3.17.7 Host Notify Protocol
          8. 26.3.3.17.8 Alert Response Protocol
          9. 26.3.3.17.9 Address Resolution Protocol
      4. 26.3.4 Protocol Descriptions & Initialization
        1. 26.3.4.1 I2C Controller Mode
          1. 26.3.4.1.1 I2C Controller Initialization
          2. 26.3.4.1.2 I2C Controller Status
          3. 26.3.4.1.3 I2C Controller Receive Mode
          4. 26.3.4.1.4 I2C Controller Transmitter Mode
          5. 26.3.4.1.5 Controller Transaction Configurations
        2. 26.3.4.2 I2C Target Mode
          1. 26.3.4.2.1 I2C Target Initialization
          2. 26.3.4.2.2 I2C Target Status
          3. 26.3.4.2.3 I2C Target Receiver Mode
          4. 26.3.4.2.4 I2C Target Transmitter Mode
      5. 26.3.5 Reset Considerations
      6. 26.3.6 Initialization
      7. 26.3.7 Interrupt and Events Support
        1. 26.3.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 26.3.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 26.3.8 Emulation Modes
    4. 26.4 UNICOMM I2C Registers
      1. 26.4.1 UNICOMMI2CC Registers
      2. 26.4.2 UNICOMMI2CT Registers
  29. 27UNICOMM-SPI
    1. 27.1 UNICOMM-SPI Overview
      1. 27.1.1 Purpose of the Peripheral
      2. 27.1.2 Features
      3. 27.1.3 Functional Block Diagram
      4. 27.1.4 External Connections and Signal Descriptions
    2. 27.2 SPI Operation
      1. 27.2.1  Clock Frequency Support
        1. 27.2.1.1 SPI Clock Generation
      2. 27.2.2  General Architecture
        1. 27.2.2.1 Chip Select and Command Handling
          1. 27.2.2.1.1 Chip Select Control
        2. 27.2.2.2 Command Data Control
        3. 27.2.2.3 Data Format
        4. 27.2.2.4 Delayed data sampling
        5. 27.2.2.5 DMA Operation
      3. 27.2.3  FIFO Operation
        1. 27.2.3.1 FIFO Size
        2. 27.2.3.2 FIFO Status bits
          1. 27.2.3.2.1 RIS.RX based on FIFO threshold settings
          2. 27.2.3.2.2 RIS.TX based on FIFO threshold settings
        3. 27.2.3.3 Clearing FIFO contents
        4. 27.2.3.4 Hardware monitors empty, full and overflow conditions
      4. 27.2.4  Suspend communication
        1. 27.2.4.1 SPI IDLE State Requirements
      5. 27.2.5  Internal Loopback Operation
      6. 27.2.6  Repeat Transfer mode
      7. 27.2.7  Receive Timeout
      8. 27.2.8  Line Timeout
      9. 27.2.9  Protocol Descriptions
        1. 27.2.9.1 Motorola SPI Frame Format
        2. 27.2.9.2 Texas Instruments Synchronous Serial Frame Format
      10. 27.2.10 Status Flags
      11. 27.2.11 Module configuration
      12. 27.2.12 Reset Considerations
      13. 27.2.13 Initialization
      14. 27.2.14 Interrupt and Events Support
        1. 27.2.14.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 27.2.14.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      15. 27.2.15 Emulation Modes
        1. 27.2.15.1 Graceful Halt
    3. 27.3 UNICOMMSPI Registers
  30. 28Timers (TIMx)
    1. 28.1 TIMx Overview
      1. 28.1.1 TIMG Overview
        1. 28.1.1.1 TIMG Features
        2. 28.1.1.2 Functional Block Diagram
      2. 28.1.2 TIMA Overview
        1. 28.1.2.1 TIMA Features
        2. 28.1.2.2 Functional Block Diagram
      3. 28.1.3 TIMx Instance Configuration
    2. 28.2 TIMx Operation
      1. 28.2.1  Timer Counter
        1. 28.2.1.1 Clock Source Select and Prescaler
          1. 28.2.1.1.1 Internal Clock and Prescaler
          2. 28.2.1.1.2 External Signal Trigger
        2. 28.2.1.2 Repeat Counter (TIMA only)
      2. 28.2.2  Counting Mode Control
        1. 28.2.2.1 One-shot and Periodic Modes
        2. 28.2.2.2 Down Counting Mode
        3. 28.2.2.3 Up/Down Counting Mode
        4. 28.2.2.4 Up Counting Mode
        5. 28.2.2.5 Phase Load (TIMA only)
      3. 28.2.3  Capture/Compare Module
        1. 28.2.3.1 Capture Mode
          1. 28.2.3.1.1 Input Selection, Counter Conditions, and Inversion
            1. 28.2.3.1.1.1 CCP Input Edge Synchronization
            2. 28.2.3.1.1.2 CCP Input Pulse Conditions
            3. 28.2.3.1.1.3 Counter Control Operation
            4. 28.2.3.1.1.4 CCP Input Filtering
            5. 28.2.3.1.1.5 Input Selection
          2. 28.2.3.1.2 Use Cases
            1. 28.2.3.1.2.1 Edge Time Capture
            2. 28.2.3.1.2.2 Period Capture
            3. 28.2.3.1.2.3 Pulse Width Capture
            4. 28.2.3.1.2.4 Combined Pulse Width and Period Time
          3. 28.2.3.1.3 QEI Mode (TIMG with QEI support only)
            1. 28.2.3.1.3.1 QEI With 2-Signal
            2. 28.2.3.1.3.2 QEI With Index Input
            3. 28.2.3.1.3.3 QEI Error Detection
          4. 28.2.3.1.4 Hall Input Mode (TIMG with QEI support only)
        2. 28.2.3.2 Compare Mode
          1. 28.2.3.2.1 Edge Count
      4. 28.2.4  Shadow Load and Shadow Compare
        1. 28.2.4.1 Shadow Load (TIMG4-7, TIMA only)
        2. 28.2.4.2 Shadow Compare (TIMG4-7, TIMG12-13, TIMA only)
      5. 28.2.5  Output Generator
        1. 28.2.5.1 Configuration
        2. 28.2.5.2 Use Cases
          1. 28.2.5.2.1 Edge-Aligned PWM
          2. 28.2.5.2.2 Center-Aligned PWM
          3. 28.2.5.2.3 Asymmetric PWM (TIMA only)
          4. 28.2.5.2.4 Complementary PWM With Deadband Insertion (TIMA only)
        3. 28.2.5.3 Forced Output
      6. 28.2.6  Fault Handler (TIMA only)
        1. 28.2.6.1 Fault Input Conditioning
        2. 28.2.6.2 Fault Input Sources
        3. 28.2.6.3 Counter Behavior With Fault Conditions
        4. 28.2.6.4 Output Behavior With Fault Conditions
      7. 28.2.7  Synchronization With Cross Trigger
        1. 28.2.7.1 Main Timer Cross Trigger Configuration
        2. 28.2.7.2 Secondary Timer Cross Trigger Configuration
      8. 28.2.8  Low Power Operation
      9. 28.2.9  Interrupt and Event Support
        1. 28.2.9.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 28.2.9.2 Generic Event Publisher and Subscriber (GEN_EVENT0 and GEN_EVENT1)
        3. 28.2.9.3 Generic Subscriber Event Example (COMP to TIMx)
      10. 28.2.10 Debug Handler (TIMA Only)
    3. 28.3 TIMx Registers
  31. 29TIMB
    1. 29.1 TIMB Overview
      1. 29.1.1 Features
      2. 29.1.2 TIMB Block Diagram
    2. 29.2 TIMB Operation
      1. 29.2.1 Counter Block Operation
        1. 29.2.1.1 Clock Source Selection
        2. 29.2.1.2 Counter Reset Generation
        3. 29.2.1.3 Event Based Enable and Disable
        4. 29.2.1.4 Event Generation
        5. 29.2.1.5 Interrupt Generation
        6. 29.2.1.6 Counter Behavior on a Debug Halt
        7. 29.2.1.7 Hardware Locking of Configuration Registers
    3. 29.3 TIMB Example Applications
      1. 29.3.1 Periodic Interrupt Generation
      2. 29.3.2 Counter Chaining
      3. 29.3.3 Event Counting
      4. 29.3.4 Event Duration Measurement
      5. 29.3.5 Event Sequence Checking
      6. 29.3.6 PWM Generation
    4. 29.4 TIMB Registers
  32. 30Low Frequency Subsystem (LFSS)
    1. 30.1  Overview
    2. 30.2  Clock System
    3. 30.3  LFSS Reset Using VBAT
    4. 30.4  Power Domains and Supply Detection
      1. 30.4.1 Startup When VBAT Powers on First
      2. 30.4.2 Startup when VDD powers on first
      3. 30.4.3 Behavior When VDD is Lost
      4. 30.4.4 Behavior when VBAT is lost
      5. 30.4.5 Behavior when the device goes into SHUTDOWN mode
      6. 30.4.6 Supercapacitor Charging Circuit
    5. 30.5  Real Time Counter (RTC_x)
    6. 30.6  Independent Watchdog Timer (IWDT)
    7. 30.7  Tamper Input and Output
      1. 30.7.1 IOMUX Mode
      2. 30.7.2 Tamper Mode
        1. 30.7.2.1 Tamper Event Detection
        2. 30.7.2.2 Timestamp Event Output
        3. 30.7.2.3 Heartbeat Generator
        4. 30.7.2.4 RTC Clock Output
    8. 30.8  Scratchpad Memory
    9. 30.9  Lock Function of RTC, TIO, and IWDT
    10. 30.10 LFSS Registers
  33. 31Low Frequency Subsystem (LFSS_B)
    1. 31.1 Overview
    2. 31.2 Clock System
    3. 31.3 LFSS Reset
    4. 31.4 Real Time Counter (RTC_x)
    5. 31.5 Independent Watchdog Timer (IWDT)
    6. 31.6 Lock Function of RTC and IWDT
    7. 31.7 LFSS Registers
  34. 32RTC
    1. 32.1 Overview
      1. 32.1.1 RTC Instances
    2. 32.2 Basic Operation
    3. 32.3 Configuration
      1. 32.3.1  Clocking
      2. 32.3.2  Reading and Writing to RTC Peripheral Registers
      3. 32.3.3  Binary vs. BCD
      4. 32.3.4  Leap Year Handling
      5. 32.3.5  Calendar Alarm Configuration
      6. 32.3.6  Interval Alarm Configuration
      7. 32.3.7  Periodic Alarm Configuration
      8. 32.3.8  Calibration
        1. 32.3.8.1 Crystal Offset Error
          1. 32.3.8.1.1 Offset Error Correction Mechanism
        2. 32.3.8.2 Crystal Temperature Error
          1. 32.3.8.2.1 Temperature Drift Correction Mechanism
      9. 32.3.9  RTC Prescaler Extension
      10. 32.3.10 RTC Timestamp Capture
      11. 32.3.11 RTC Events
        1. 32.3.11.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 32.3.11.2 Generic Event Publisher (GEN_EVENT)
    4. 32.4 RTC Registers
  35. 33IWDT
    1. 33.1 920
    2. 33.2 IWDT Clock Configuration
    3. 33.3 IWDT Period Selection
    4. 33.4 Debug Behavior of the IWDT
    5. 33.5 IWDT Registers
  36. 34Window Watchdog Timer (WWDT)
    1. 34.1 WWDT Overview
      1. 34.1.1 Watchdog Mode
      2. 34.1.2 Interval Timer Mode
    2. 34.2 WWDT Operation
      1. 34.2.1 Mode Selection
      2. 34.2.2 Clock Configuration
      3. 34.2.3 Low-Power Mode Behavior
      4. 34.2.4 Debug Behavior
      5. 34.2.5 WWDT Events
        1. 34.2.5.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 34.3 WWDT Registers
  37. 35Debug
    1. 35.1 DEBUGSS Overview
      1. 35.1.1 Debug Interconnect
      2. 35.1.2 Physical Interface
      3. 35.1.3 Debug Access Ports
    2. 35.2 DEBUGSS Operation
      1. 35.2.1 Debug Features
        1. 35.2.1.1 Processor Debug
          1. 35.2.1.1.1 Breakpoint Unit (BPU)
          2. 35.2.1.1.2 Data Watchpoint and Trace Unit (DWT)
        2. 35.2.1.2 Peripheral Debug
        3. 35.2.1.3 EnergyTrace Technology
      2. 35.2.2 Behavior in Low Power Modes
      3. 35.2.3 Restricting Debug Access
      4. 35.2.4 Mailbox (DSSM)
        1. 35.2.4.1 DSSM Events
          1. 35.2.4.1.1 CPU Interrupt Event (CPU_INT)
        2. 35.2.4.2 Reference
    3. 35.3 DEBUGSS Registers
  38. 36Revision History

1.4.5 NONMAIN_TYPEA Registers

Table 1-7 lists the memory-mapped registers for the NONMAIN_TYPEA registers. All register offset addresses not listed in Table 1-7 should be considered as reserved locations and the register contents should not be modified.

Table 1-7 NONMAIN_TYPEA Registers
OffsetAcronymRegister NameGroupSection
41C00000hBCRCONFIGIDConfiguration ID of BCR StructureGo
41C00004hBOOTCFG0Serial wire debug (SWD) lock policy.Go
41C00008hBOOTCFG1TI Failure Analysis (FA) mode and BSL invoke pin policies.Go
41C0000Ch + formulaPWDDEBUGLOCK[y]Debug Lock Password.
This password is used when the BOOTCFG0.DEBUGACCESS field is configured as Enable with password.		Go
41C0001ChBOOTCFG2Fast boot mode policy and BSL mode policyGo
41C00020hBOOTCFG3Mass erase and factory reset mode policies.
These policies affect SWD initiated and BSL initiated mass erase and factory reset commands.
If the SW-DP is disabled (SWDP_MODE is disabled), SWD initiated commands are not allowed as the SW-DP is fully disabled.
If the BSL is disabled (BSLMODE is disabled), these settings are a a don't care for BSL initiated commands as the BSL is not enabled to be invoked.		Go
41C00024h + formulaPWDMASSERASE[y]SWD mass erase command password (must be provided via DSSM to authenticate a mass erase command)Go
41C00034h + formulaPWDFACTORYRESET[y]SWD factory reset command password (must be provided via DSSM to authenticate a factory reset command)Go
41C00044hFLASHSWP0Static write protection policy for the first 32kB of flash memory.
When protected, sectors will not be available for program or erase by either the bootloader or application code		Go
41C00048hFLASHSWP1Static write protection policy for additional sectors of flash memory.
When protected, sectors will not be available for program or erase by either the bootloader or application code.		Go
41C0004ChBOOTCFG4Nonmain protection and Application CRC check policiesGo
41C00050hAPPCRCSTARTStart address of the application CRC check (must be an address in a MAIN flash region).Go
41C00054hAPPCRCLENGTHLength of the application area to include in the application CRC check (in bytes), starting from APPCRCSTART.Go
41C00058hAPPCRCExpected application CRC check digest (CRC-32) to test against during boot.Go
41C0005ChBOOTCRCCRC digest of the BCR configuration portion of the NONMAIN memory.Go
41C00100hBSLCONFIGIDConfiguration ID of BSL StructureGo
41C00104hBSLPINCFG0BSL UART PIN Configuration.
The reset value of these fields differ for each device, based on the pins used.		Go
41C00108hBSLPINCFG1BSL I2C PIN Configuration.
The reset value of these fields differ for each device, based on the pins used.		Go
41C0010ChBSLCONFIG0BSL invoke pin configuration and memory read-out policy.Go
41C00110h + formulaPWDBSL[y]BSL access passwordGo
41C00130hBSLPLUGINCFGDefines the presence and type of a BSL plug-in in MAIN flash memory.Go
41C00134h + formulaBSLPLUGINHOOK[y]Function pointers for plug-in init, receive, transmit, and de-init functions.Go
41C00144hBSLCONFIG1Go
41C00148hSBLADDRESSAddress of an alternate BSL.Go
41C0014ChBSLAPPVERAddress of the application version word.Go
41C00150hBSLCONFIG2Configures the BSL Alert Configuration and I2C Slave address of BSL.Go
41C00154hBSLCRCCRC digest of the BSL_CONFIG portion of the NONMAIN memory.Go

Complex bit access types are encoded to fit into small table cells. Table 1-8 shows the codes that are used for access types in this section.

Table 1-8 NONMAIN_TYPEA Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

1.4.5.1 BCRCONFIGID (Offset = 41C00000h) [Reset = 00000000h]

BCRCONFIGID is shown in Figure 1-2 and described in Table 1-9.

Return to the Summary Table.

Configuration ID of BCR Structure

Figure 1-2 BCRCONFIGID
313029282726252423222120191817161514131211109876543210
CONFIG
R/W-0h
Table 1-9 BCRCONFIGID Field Descriptions
BitFieldTypeResetDescription
31-0CONFIGR/W0hConfiguration ID of the BCR Structure

1.4.5.2 BOOTCFG0 (Offset = 41C00004h) [Reset = AABBAABBh]

BOOTCFG0 is shown in Figure 1-3 and described in Table 1-10.

Return to the Summary Table.

Serial wire debug (SWD) lock policy.

Figure 1-3 BOOTCFG0
313029282726252423222120191817161514131211109876543210
SWDP_MODEDEBUGACCESS
R/W-AABBhW-AABBh
Table 1-10 BOOTCFG0 Field Descriptions
BitFieldTypeResetDescription
31-16SWDP_MODER/WAABBhThe serial wire debug port (SW-DP) access policy. This policy sets whether any communication is allowed with the device via the SWD
pins (to any DAP). When disabled, no SWD communication is possible regardless of the configuration of the DEBUGACCESS field.
  • AABBh = The SW-DP is enabled and device access is set by the additional policies in NONMAIN
  • FFFFh = The SW-DP is fully disabled and no device access is possible via the SW-DP (Any value other than 0xAABB)
15-0DEBUGACCESSWAABBhThe debug access policy for accessing the AHB-AP, ET-AP, and PWR-AP debug access ports. Note that if SWDP_MODE is set to DISABLED, the value of this field is ignored and the debug port will remain fully locked
  • AABBh = Access to AHB-AP, ET-AP, and PWR-AP via SWD is enabled
  • CCDDh = Access to AHB-AP, ET-AP, and PWR-AP via SWD is only enabled when the correct password is provided via the DSSM before BCR execution
  • FFFFh = Access to AHB-AP, ET-AP, and PWR-AP via SWD is disabled (Any value other than 0xCCDD or 0xAABB)

1.4.5.3 BOOTCFG1 (Offset = 41C00008h) [Reset = AABBAABBh]

BOOTCFG1 is shown in Figure 1-4 and described in Table 1-11.

Return to the Summary Table.

TI Failure Analysis (FA) mode and BSL invoke pin policies.

Figure 1-4 BOOTCFG1
313029282726252423222120191817161514131211109876543210
BSL_PIN_INVOKETI_FA_MODE
R/W-AABBhR/W-AABBh
Table 1-11 BOOTCFG1 Field Descriptions
BitFieldTypeResetDescription
31-16BSL_PIN_INVOKER/WAABBhBoot strap loader (BSL) pin invoke method enable/disable policy
  • AABBh = The BSL_INVOKE pin is checked during boot
  • FFFFh = The BSL_INVOKE pin is not checked during boot (Any value other than 0xAABB)
15-0TI_FA_MODER/WAABBhSets the TI failure analysis enable/disable policy. If enabled, a re-test request through DSSM is allowed, else it is not allowed. Note that
if SWDP_MODE is set to disabled, this field is ignored and failure analysis is not possible.
  • AABBh = TI failure analysis is allowed
  • FFFFh = TI failure analysis is not allowed (Any value other than 0xAABB)

1.4.5.4 PWDDEBUGLOCK[y] (Offset = 41C0000Ch + formula) [Reset = FFFFFFFFh]

PWDDEBUGLOCK[y] is shown in Figure 1-5 and described in Table 1-12.

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Debug Lock Password. This password is used when the BOOTCFG0.DEBUGACCESS field is configured as Enable with password.

Offset = 41C0000Ch + (y * 4h); where y = 0h to 3h

Figure 1-5 PWDDEBUGLOCK[y]
313029282726252423222120191817161514131211109876543210
PASSWORD
R/W-FFFFFFFFh
Table 1-12 PWDDEBUGLOCK[y] Field Descriptions
BitFieldTypeResetDescription
31-0PASSWORDR/WFFFFFFFFhDebug Lock Password

1.4.5.5 BOOTCFG2 (Offset = 41C0001Ch) [Reset = AABBFFFFh]

BOOTCFG2 is shown in Figure 1-6 and described in Table 1-13.

Return to the Summary Table.

Fast boot mode policy and BSL mode policy

Figure 1-6 BOOTCFG2
313029282726252423222120191817161514131211109876543210
BSLMODEFASTBOOTMODE
R/W-AABBhR/W-FFFFh
Table 1-13 BOOTCFG2 Field Descriptions
BitFieldTypeResetDescription
31-16BSLMODER/WAABBhBSLMODE configures the boot strap loader enable/disable policy
  • AABBh = The BSL is enabled
  • FFFFh = The BSL is disabled (Any value other than 0xAABB)
15-0FASTBOOTMODER/WFFFFhFASTBOOTMODE configures the fast boot mode enable/disable policy
  • AABBh = Fast boot mode is enabled
  • FFFFh = Fast boot mode is disabled. (Any value other than 0xAABB)

1.4.5.6 BOOTCFG3 (Offset = 41C00020h) [Reset = AABBAABBh]

BOOTCFG3 is shown in Figure 1-7 and described in Table 1-14.

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Mass erase and factory reset mode policies. These policies affect SWD initiated and BSL initiated mass erase and factory reset commands. If the SW-DP is disabled (SWDP_MODE is disabled), SWD initiated commands are not allowed as the SW-DP is fully disabled. If the BSL is disabled (BSLMODE is disabled), these settings are a a don't care for BSL initiated commands as the BSL is not enabled to be invoked.

Figure 1-7 BOOTCFG3
31302928272625242322212019181716
FACTORYRESETCMDACCESS
R/W-AABBh
1514131211109876543210
MASSERASECMDACCESS
R/W-AABBh
Table 1-14 BOOTCFG3 Field Descriptions
BitFieldTypeResetDescription
31-16FACTORYRESETCMDACCESSR/WAABBhThe factory reset command policy
  • AABBh = The factory reset command is allowed
  • CCDDh = The factory reset command is allowed only when the matching password is provided via the DSSM
  • FFFFh = The factory reset command is not allowed (Any value other than 0xAABB or 0xCCDD)
15-0MASSERASECMDACCESSR/WAABBhThe mass erase command policy
  • AABBh = The mass erase command is allowed
  • CCDDh = The mass erase command is allowed only when the matching password is provided via the DSSM
  • FFFFh = The mass erase command is not allowed (Any value other than 0xAABB or 0xCCDD)

1.4.5.7 PWDMASSERASE[y] (Offset = 41C00024h + formula) [Reset = FFFFFFFFh]

PWDMASSERASE[y] is shown in Figure 1-8 and described in Table 1-15.

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SWD mass erase command password (must be provided via DSSM to authenticate a mass erase command)

Offset = 41C00024h + (y * 4h); where y = 0h to 3h

Figure 1-8 PWDMASSERASE[y]
313029282726252423222120191817161514131211109876543210
PASSWORD
R/W-FFFFFFFFh
Table 1-15 PWDMASSERASE[y] Field Descriptions
BitFieldTypeResetDescription
31-0PASSWORDR/WFFFFFFFFhSHA2-256 Bit digest of Mass Erase Password

1.4.5.8 PWDFACTORYRESET[y] (Offset = 41C00034h + formula) [Reset = FFFFFFFFh]

PWDFACTORYRESET[y] is shown in Figure 1-9 and described in Table 1-16.

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SWD factory reset command password (must be provided via DSSM to authenticate a factory reset command)

Offset = 41C00034h + (y * 4h); where y = 0h to 3h

Figure 1-9 PWDFACTORYRESET[y]
313029282726252423222120191817161514131211109876543210
PASSWORD
R/W-FFFFFFFFh
Table 1-16 PWDFACTORYRESET[y] Field Descriptions
BitFieldTypeResetDescription
31-0PASSWORDR/WFFFFFFFFhSHA2-256 Bit digest of Factory Reset Password

1.4.5.9 FLASHSWP0 (Offset = 41C00044h) [Reset = FFFFFFFFh]

FLASHSWP0 is shown in Figure 1-10 and described in Table 1-17.

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Static write protection policy for the first 32kB of flash memory. When protected, sectors will not be available for program or erase by either the bootloader or application code

Figure 1-10 FLASHSWP0
313029282726252423222120191817161514131211109876543210
DATA
R/W-FFFFFFFFh
Table 1-17 FLASHSWP0 Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/WFFFFFFFFh1 bit per sector
  • 0h = A value of 0 indicates the write protection is applied to the corresponding sector
  • 1h = A value of 1 indicates the sector is un-protected

1.4.5.10 FLASHSWP1 (Offset = 41C00048h) [Reset = FFFFFFFFh]

FLASHSWP1 is shown in Figure 1-11 and described in Table 1-18.

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Static write protection policy for additional sectors of flash memory. When protected, sectors will not be available for program or erase by either the bootloader or application code.

Figure 1-11 FLASHSWP1
313029282726252423222120191817161514131211109876543210
DATA
R/W-FFFFFFFFh
Table 1-18 FLASHSWP1 Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/WFFFFFFFFh1 bit per 8 sectors. This is used to protect Flash memory from (32 to 256 kb)
  • 0h = A value of 0 indicates the write protection is applied to the corresponding sectors
  • 1h = A value of 1 indicates the sector is un-protected

1.4.5.11 BOOTCFG4 (Offset = 41C0004Ch) [Reset = FFFFFFFFh]

BOOTCFG4 is shown in Figure 1-12 and described in Table 1-19.

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Nonmain protection and Application CRC check policies

Figure 1-12 BOOTCFG4
313029282726252423222120191817161514131211109876543210
APPCRCMODENONMAINSWP
R/W-FFFFhR/W-FFFFh
Table 1-19 BOOTCFG4 Field Descriptions
BitFieldTypeResetDescription
31-16APPCRCMODER/WFFFFhAPPCRCMODE enables or disables the boot time CRC check of a segment of MAIN flash memory.
  • AABBh = The boot time MAIN flash CRC check is enabled. If the boot time CRC check passes, the application code in MAIN flash is started unless the reset vector or stack pointer are blank (unprogrammed). In the event of a failing CRC check, the application code in MAIN flash will not be started and the boot process fails.
  • FFFFh = The boot time MAIN flash CRC check is disabled. The application code in MAIN flash is always started unless the reset vector or stack pointer are blank (unprogrammed).
15-0NONMAINSWPR/WFFFFhStatic write protection policy for entire NONMAIN device configuration memory. Only Bit 0 is used.
  • 0h = Protected, does not allow program/erase of the NONMAIN by all means other than a SWD-initiated factory reset
  • 1h = Unprotected, allows program/erase of the NONMAIN by normal means.

1.4.5.12 APPCRCSTART (Offset = 41C00050h) [Reset = FFFFFFFFh]

APPCRCSTART is shown in Figure 1-13 and described in Table 1-20.

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Start address of the application CRC check (must be an address in a MAIN flash region).

Figure 1-13 APPCRCSTART
313029282726252423222120191817161514131211109876543210
ADDRESS
R/W-FFFFFFFFh
Table 1-20 APPCRCSTART Field Descriptions
BitFieldTypeResetDescription
31-0ADDRESSR/WFFFFFFFFhApplication CRC check start address

1.4.5.13 APPCRCLENGTH (Offset = 41C00054h) [Reset = FFFFFFFFh]

APPCRCLENGTH is shown in Figure 1-14 and described in Table 1-21.

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Length of the application area to include in the application CRC check (in bytes), starting from APPCRCSTART.

Figure 1-14 APPCRCLENGTH
313029282726252423222120191817161514131211109876543210
LENGTH
R/W-FFFFFFFFh
Table 1-21 APPCRCLENGTH Field Descriptions
BitFieldTypeResetDescription
31-0LENGTHR/WFFFFFFFFhApplication CRC check source data length

1.4.5.14 APPCRC (Offset = 41C00058h) [Reset = FFFFFFFFh]

APPCRC is shown in Figure 1-15 and described in Table 1-22.

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Expected application CRC check digest (CRC-32) to test against during boot.

Figure 1-15 APPCRC
313029282726252423222120191817161514131211109876543210
DIGEST
R/W-FFFFFFFFh
Table 1-22 APPCRC Field Descriptions
BitFieldTypeResetDescription
31-0DIGESTR/WFFFFFFFFhApplication CRC check digest

1.4.5.15 BOOTCRC (Offset = 41C0005Ch) [Reset = 00000000h]

BOOTCRC is shown in Figure 1-16 and described in Table 1-23.

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CRC digest of the BCR configuration portion of the NONMAIN memory.

Figure 1-16 BOOTCRC
313029282726252423222120191817161514131211109876543210
DIGEST
R/W-0h
Table 1-23 BOOTCRC Field Descriptions
BitFieldTypeResetDescription
31-0DIGESTR/W0hBCR configuration data CRC digest. 32 bit CRC Digest, if the device supports CRC32-ISO3309. Otherwise 16 bit CRC digest, using polynomial CRC16-CCITT. Configuration to be used for CRC calulation: 1. Polynomial should be as per the chosen standard, 2. Input reflected, 3. Output reflected, 4. Initial value should be 0xFFFFFFFF, 5. Final XOR value should be 0x0.

1.4.5.16 BSLCONFIGID (Offset = 41C00100h) [Reset = 00000000h]

BSLCONFIGID is shown in Figure 1-17 and described in Table 1-24.

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Configuration ID of BSL Structure

Figure 1-17 BSLCONFIGID
313029282726252423222120191817161514131211109876543210
CONFIG
R/W-0h
Table 1-24 BSLCONFIGID Field Descriptions
BitFieldTypeResetDescription
31-0CONFIGR/W0hConfiguration ID of BSL Structure

1.4.5.17 BSLPINCFG0 (Offset = 41C00104h) [Reset = 00000000h]

BSLPINCFG0 is shown in Figure 1-18 and described in Table 1-25.

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BSL UART PIN Configuration. The reset value of these fields differ for each device, based on the pins used.

Figure 1-18 BSLPINCFG0
31302928272625242322212019181716
UARTTX_MUX_SELUARTTX_PAD_NUM
R/W-0hR/W-0h
1514131211109876543210
UARTRX_MUX_SELUARTRX_PAD_NUM
R/W-0hR/W-0h
Table 1-25 BSLPINCFG0 Field Descriptions
BitFieldTypeResetDescription
31-24UARTTX_MUX_SELR/W0hUART TX IOMUX PINCM mux selection.
23-16UARTTX_PAD_NUMR/W0hUART TX IOMUX PINCM register
15-8UARTRX_MUX_SELR/W0hUART RX IOMUX PINCM mux selection
7-0UARTRX_PAD_NUMR/W0hUART RX IOMUX PINCM register

1.4.5.18 BSLPINCFG1 (Offset = 41C00108h) [Reset = 00000000h]

BSLPINCFG1 is shown in Figure 1-19 and described in Table 1-26.

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BSL I2C PIN Configuration. The reset value of these fields differ for each device, based on the pins used.

Figure 1-19 BSLPINCFG1
31302928272625242322212019181716
I2CSCL_MUX_SELI2CSCL_PAD_NUM
R/W-0hR/W-0h
1514131211109876543210
I2CSDA_MUX_SELI2CSDA_PAD_NUM
R/W-0hR/W-0h
Table 1-26 BSLPINCFG1 Field Descriptions
BitFieldTypeResetDescription
31-24I2CSCL_MUX_SELR/W0hI2C SCL IOMUX PINCM mux selection
23-16I2CSCL_PAD_NUMR/W0hI2C SCL IOMUX PINCM register
15-8I2CSDA_MUX_SELR/W0hI2C SDA IOMUX PINCM mux selection
7-0I2CSDA_PAD_NUMR/W0hI2C SDA IOMUX PINCM register

1.4.5.19 BSLCONFIG0 (Offset = 41C0010Ch) [Reset = 0000XX00h]

BSLCONFIG0 is shown in Figure 1-20 and described in Table 1-27.

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BSL invoke pin configuration and memory read-out policy.

Figure 1-20 BSLCONFIG0
3130292827262524
READOUTEN
R/W-0h
2322212019181716
READOUTEN
R/W-0h
15141312111098
RESERVEDBSLIVK_GPIOPORTBSLIVK_GPIOPIN
R-0hR/W-XhR/W-Xh
76543210
BSLIVK_LVLRESERVEDBSLIVK_PAD_NUM
R/W-0hR-0hR/W-0h
Table 1-27 BSLCONFIG0 Field Descriptions
BitFieldTypeResetDescription
31-16READOUTENR/WFFFFhSets the memory read-out policy for the BSL interface
  • AABBh = Memory contents can be read via the BSL interface
  • FFFFh = Memory read-out is not possible via the BSL interface (Any value other than 0xAABB)
15-14RESERVEDR0h
13BSLIVK_GPIOPORTR/WxThe BSL_invoke GPIO port index corresponding to the pad used for BSL_invoke
  • 0h = The BSL_invoke pin is on GPIO port A
  • 1h = The BSL_invoke pin is on GPIO port B
12-8BSLIVK_GPIOPINR/WxThe BSL_invoke GPIO pin index corresponding to the pad used for BSL_invoke. Valid values are 0 to 31.
7BSLIVK_LVLR/W1hThe BSL_invoke input logic level which shall invoke the BSL
  • 0h = Pin state LOW will invoke BSL
  • 1h = Pin state HIGH will invoke BSL
6RESERVEDR0h
5-0BSLIVK_PAD_NUMR/W0hThe IOMUX PINCM register corresponding to the pad to be used for BSL_invoke

1.4.5.20 PWDBSL[y] (Offset = 41C00110h + formula) [Reset = FFFFFFFFh]

PWDBSL[y] is shown in Figure 1-21 and described in Table 1-28.

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BSL access password

Offset = 41C00110h + (y * 4h); where y = 0h to 7h

Figure 1-21 PWDBSL[y]
313029282726252423222120191817161514131211109876543210
PASSWORD
R/W-FFFFFFFFh
Table 1-28 PWDBSL[y] Field Descriptions
BitFieldTypeResetDescription
31-0PASSWORDR/WFFFFFFFFhBSL access Password of size 256 bit

1.4.5.21 BSLPLUGINCFG (Offset = 41C00130h) [Reset = FFFFFFFFh]

BSLPLUGINCFG is shown in Figure 1-22 and described in Table 1-29.

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Defines the presence and type of a BSL plug-in in MAIN flash memory.

Figure 1-22 BSLPLUGINCFG
31302928272625242322212019181716
SRAMUSEDFLASHPLUGINEXISTS
R/W-FFhR/W-FFh
1514131211109876543210
PLUGINTYPE
R/W-FFFFh
Table 1-29 BSLPLUGINCFG Field Descriptions
BitFieldTypeResetDescription
31-24SRAMUSEDR/WFFhSRAM consumed by Flash plugin, from 0x00 to 0xFF.
23-16FLASHPLUGINEXISTSR/WFFhThe field tells if Flash Plugin exists are not
  • BBh = Flash Plugin exists
  • FFh = Only ROM plugin will be used
15-0PLUGINTYPER/WFFFFhThe Plugin type specifies which interface plugin is added in Flash. When the same interface is supported by ROM Bootloader, then ROM interface will be overridden with the Flash interface. If the same interface as in ROM BSL should be added as an additional interface without overriding ROM interface, a new value that is not part of this list should be chosen.
  • 1000h = Plug-in is for UART interface. ROM UART interface will be overriden with this Flash plug-in.
  • 2000h = Plug-in is for I2C interface. ROM I2C interface will be overriden with this Flash plug-in.
  • 3000h = Plug-is for a new interface. This interface should be added on top of interfaces supported by ROM BSL. It can be any value other than 0x1000, 0x2000 and 0xFFFF.
  • FFFFh = For all other values. Any other interfaces with valid hooks will be added to Plugin list.

1.4.5.22 BSLPLUGINHOOK[y] (Offset = 41C00134h + formula) [Reset = FFFFFFFFh]

BSLPLUGINHOOK[y] is shown in Figure 1-23 and described in Table 1-30.

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Function pointers for plug-in init, receive, transmit, and de-init functions.

Offset = 41C00134h + (y * 4h); where y = 0h to 3h

Figure 1-23 BSLPLUGINHOOK[y]
313029282726252423222120191817161514131211109876543210
BSLPLUGININIT
R/W-FFFFFFFFh
Table 1-30 BSLPLUGINHOOK[y] Field Descriptions
BitFieldTypeResetDescription
127-96BSLPLUGINDEINITR/WFFFFFFFFhFunction pointer for the Deinit API
95-64BSLPLUGINSENDR/WFFFFFFFFhFunction pointer for the Send API
63-32BSLPLUGINRECEIVER/WFFFFFFFFhFunction pointer for the Receive API
31-0BSLPLUGININITR/WFFFFFFFFhFunction pointer for the Init API

1.4.5.23 BSLCONFIG1 (Offset = 41C00144h) [Reset = FFFFFFFFh]

BSLCONFIG1 is shown in Figure 1-24 and described in Table 1-31.

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Figure 1-24 BSLCONFIG1
313029282726252423222120191817161514131211109876543210
RESERVEDALTBSLCONFIG
R-0hR/W-FFFFh
Table 1-31 BSLCONFIG1 Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDRFFFFh
15-0ALTBSLCONFIGR/WFFFFhControls the invocation of alternate BSL in main flash region.
  • AABBh = Uses the alternate BSL
  • FFFFh = Does not use alternate BSL. Uses ROM BSL.

1.4.5.24 SBLADDRESS (Offset = 41C00148h) [Reset = FFFFFFFFh]

SBLADDRESS is shown in Figure 1-25 and described in Table 1-32.

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Address of an alternate BSL.

Figure 1-25 SBLADDRESS
313029282726252423222120191817161514131211109876543210
ADDRESS
R/W-FFFFFFFFh
Table 1-32 SBLADDRESS Field Descriptions
BitFieldTypeResetDescription
31-0ADDRESSR/WFFFFFFFFhAddress of the alternate BSL, if present.

1.4.5.25 BSLAPPVER (Offset = 41C0014Ch) [Reset = FFFFFFFFh]

BSLAPPVER is shown in Figure 1-26 and described in Table 1-33.

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Address of the application version word.

Figure 1-26 BSLAPPVER
313029282726252423222120191817161514131211109876543210
ADDRESS
R/W-FFFFFFFFh
Table 1-33 BSLAPPVER Field Descriptions
BitFieldTypeResetDescription
31-0ADDRESSR/WFFFFFFFFhAddress of the application version word (must be a valid flash address to be returned). If the given flash address is not programmed, then 0h will be returned.

1.4.5.26 BSLCONFIG2 (Offset = 41C00150h) [Reset = 0048FFFFh]

BSLCONFIG2 is shown in Figure 1-27 and described in Table 1-34.

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Configures the BSL Alert Configuration and I2C Slave address of BSL.

Figure 1-27 BSLCONFIG2
313029282726252423222120191817161514131211109876543210
I2CTARGETADDRALERTACTION
R/W-48hR/W-FFFFh
Table 1-34 BSLCONFIG2 Field Descriptions
BitFieldTypeResetDescription
31-16I2CTARGETADDRR/W0048hI2C target address to be used for the ROM BSL I2C communication.
15-0ALERTACTIONR/WFFFFhAction to take upon a security alert condition.
  • AABBh = Trigger a factory reset. Note that if sectors in MAIN or NONMAIN flash are write protected they will not be affected by the BSL factory reset
  • CCDDh = Re-configure the NONMAIN region to disable the BSL. This is not supported if the NONMAIN region is configured to be write protected
  • 000FFFFFh = Ignore the security alert condition (Any value other than 0xAABB)

1.4.5.27 BSLCRC (Offset = 41C00154h) [Reset = XXXXXXXXh]

BSLCRC is shown in Figure 1-28 and described in Table 1-35.

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CRC digest of the BSL_CONFIG portion of the NONMAIN memory.

Figure 1-28 BSLCRC
313029282726252423222120191817161514131211109876543210
DIGEST
R/W-X
Table 1-35 BSLCRC Field Descriptions
BitFieldTypeResetDescription
31-0DIGESTR/WXBSL configuration data CRC digest. 32 bit CRC Digest, if the device supports CRC32-ISO3309. Otherwise 16 bit CRC digest, using polynomial CRC16-CCITT. Configuration to be used for CRC calulation: 1. Polynomial should be as per the chosen standard, 2. Input reflected, 3. Output reflected, 4. Initial value should be 0xFFFFFFFF, 5. Final XOR value should be 0x0.

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