SLAU847F October   2022  â€“ March 2026 MSPM0L1105 , MSPM0L1106 , MSPM0L1116 , MSPM0L1117 , MSPM0L1227 , MSPM0L1227-Q1 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346 , MSPM0L2116 , MSPM0L2117 , MSPM0L2227 , MSPM0L2227-Q1 , MSPM0L2228 , MSPM0L2228-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation
    5.     Support Resources
    6.     Trademarks
  3. 1 Architecture
    1. 1.1 Architecture Overview
    2. 1.2 Bus Organization
    3. 1.3 Platform Memory Map
      1. 1.3.1 Code Region
      2. 1.3.2 SRAM Region
      3. 1.3.3 Peripheral Region
      4. 1.3.4 Subsystem Region
      5. 1.3.5 System PPB Region
    4. 1.4 Boot Configuration
      1. 1.4.1 Configuration Memory (NONMAIN)
        1. 1.4.1.1 CRC-Backed Configuration Data
        2. 1.4.1.2 16-bit Pattern Match for Critical Fields
      2. 1.4.2 Boot Configuration Routine (BCR)
        1. 1.4.2.1 Serial Wire Debug Related Policies
          1. 1.4.2.1.1 SWD Security Level 0
          2. 1.4.2.1.2 SWD Security Level 1
          3. 1.4.2.1.3 SWD Security Level 2
        2. 1.4.2.2 SWD Mass Erase and Factory Reset Commands
        3. 1.4.2.3 Flash Memory Protection and Integrity Related Policies
          1. 1.4.2.3.1 Locking the Application (MAIN) Flash Memory
          2. 1.4.2.3.2 Locking the Configuration (NONMAIN) Flash Memory
          3. 1.4.2.3.3 Static Write Protection NONMAIN Fields
        4. 1.4.2.4 Application CRC Verification
        5. 1.4.2.5 Fast Boot
        6. 1.4.2.6 Bootstrap Loader (BSL) Enable/Disable Policy
          1. 1.4.2.6.1 BSL Enable
      3. 1.4.3 Bootstrap Loader (BSL)
        1. 1.4.3.1 GPIO Invoke
        2. 1.4.3.2 Bootstrap Loader (BSL) Security Policies
          1. 1.4.3.2.1 BSL Access Password
          2. 1.4.3.2.2 BSL Read-out Policy
          3. 1.4.3.2.3 BSL Security Alert Policy
        3. 1.4.3.3 Application Version
        4. 1.4.3.4 BSL Triggered Mass Erase and Factory Reset
      4. 1.4.4 NONMAIN Layout Types
      5. 1.4.5 NONMAIN_TYPEA Registers
      6. 1.4.6 NONMAIN_TYPEC Registers
      7. 1.4.7 NONMAIN_TYPEE Registers
    5. 1.5 Factory Constants
      1. 1.5.1 FACTORYREGION Layout Types
      2. 1.5.2 FACTORYREGION_TYPEA Registers
      3. 1.5.3 FACTORYREGION_TYPEC Registers
      4. 1.5.4 FACTORYREGION_TYPED Registers
      5. 1.5.5 FACTORYREGION_TYPEE Registers
  4. 2 PMCU
    1. 2.1 PMCU Overview
      1. 2.1.1 Power Domains
      2. 2.1.2 Operating Modes
        1. 2.1.2.1 RUN Mode
        2. 2.1.2.2 SLEEP Mode
        3. 2.1.2.3 STOP Mode
        4. 2.1.2.4 STANDBY Mode
        5. 2.1.2.5 SHUTDOWN Mode
        6. 2.1.2.6 Supported Functionality by Operating Mode
        7. 2.1.2.7 Suspended Low-Power Mode Operation
    2. 2.2 Power Management (PMU)
      1. 2.2.1 Power Supply
      2. 2.2.2 Core Regulator
      3. 2.2.3 Supply Supervisors
        1. 2.2.3.1 Power-on Reset (POR)
        2. 2.2.3.2 Brownout Reset (BOR)
        3. 2.2.3.3 POR and BOR Behavior During Supply Changes
      4. 2.2.4 Bandgap Reference
      5. 2.2.5 VBOOST for Analog Muxes
      6. 2.2.6 Peripheral Enable
        1. 2.2.6.1 Automatic Peripheral Disable in Low Power Modes
    3. 2.3 Clock Module (CKM)
      1. 2.3.1 Oscillators
        1. 2.3.1.1 Internal Low-Frequency Oscillator (LFOSC)
        2. 2.3.1.2 Internal System Oscillator (SYSOSC)
          1. 2.3.1.2.1 SYSOSC Gear Shift
          2. 2.3.1.2.2 SYSOSC Frequency
          3. 2.3.1.2.3 SYSOSC Frequency Correction Loop
            1. 2.3.1.2.3.1 SYSOSC FCL in External Resistor Mode (ROSC)
            2. 2.3.1.2.3.2 SYSOSC FCL in Internal Resistor Mode
          4. 2.3.1.2.4 SYSOSC User Trim Procedure
          5. 2.3.1.2.5 Disabling SYSOSC
        3. 2.3.1.3 Low Frequency Crystal Oscillator (LFXT)
        4. 2.3.1.4 LFCLK_IN (Digital Clock)
        5. 2.3.1.5 High Frequency Crystal Oscillator (HFXT)
        6. 2.3.1.6 HFCLK_IN (Digital clock)
      2. 2.3.2 Clocks
        1. 2.3.2.1  MCLK (Main Clock) Tree
        2. 2.3.2.2  CPUCLK (Processor Clock)
        3. 2.3.2.3  ULPCLK (Low-Power Clock)
        4. 2.3.2.4  MFCLK (Middle Frequency Clock)
        5. 2.3.2.5  MFPCLK (Middle Frequency Precision Clock)
        6. 2.3.2.6  LFCLK (Low-Frequency Clock)
        7. 2.3.2.7  HFCLK (High-Frequency External Clock)
        8. 2.3.2.8  HSCLK (High Speed Clock)
        9. 2.3.2.9  ADCCLK (ADC Sample Period Clock)
        10. 2.3.2.10 CANCLK (CAN-FD Functional Clock)
        11. 2.3.2.11 RTCCLK (RTC Clock)
        12. 2.3.2.12 External Clock Output (CLK_OUT)
        13. 2.3.2.13 Direct Clock Connections for Infrastructure
      3. 2.3.3 Clock Tree
        1. 2.3.3.1 Peripheral Clock Source Selection
      4. 2.3.4 Clock Monitors
        1. 2.3.4.1 LFCLK Monitor
        2. 2.3.4.2 MCLK Monitor
        3. 2.3.4.3 Startup Monitors
          1. 2.3.4.3.1 LFOSC Startup Monitor
          2. 2.3.4.3.2 LFXT Startup Monitor
          3. 2.3.4.3.3 HFCLK Startup Monitor
          4. 2.3.4.3.4 HSCLK Status
      5. 2.3.5 Frequency Clock Counter (FCC)
        1. 2.3.5.1 Using the FCC
        2. 2.3.5.2 FCC Frequency Computation and Accuracy
    4. 2.4 System Controller (SYSCTL)
      1. 2.4.1  Resets and Device Initialization
        1. 2.4.1.1 Reset Levels
          1. 2.4.1.1.1 Power-on Reset (POR) Reset Level
          2. 2.4.1.1.2 Brownout Reset (BOR) Reset Level
          3. 2.4.1.1.3 Boot Reset (BOOTRST) Reset Level
          4. 2.4.1.1.4 System Reset (SYSRST) Reset Level
          5. 2.4.1.1.5 CPU-only Reset (CPURST) Reset Level
        2. 2.4.1.2 Initial Conditions After Power-Up
        3. 2.4.1.3 NRST Pin
        4. 2.4.1.4 SWD Pins
        5. 2.4.1.5 Generating Resets in Software
        6. 2.4.1.6 Reset Cause
        7. 2.4.1.7 Peripheral Reset Control
        8. 2.4.1.8 Boot Fail Handling
      2. 2.4.2  Operating Mode Selection
      3. 2.4.3  Asynchronous Fast Clock Requests
      4. 2.4.4  SRAM Write Protection
      5. 2.4.5  Flash Wait States
      6. 2.4.6  Flash Bank Address Swap
      7. 2.4.7  Shutdown Mode Handling (if present)
      8. 2.4.8  Configuration Lockout
      9. 2.4.9  System Status
      10. 2.4.10 Error Handling
      11. 2.4.11 SYSCTL Events
        1. 2.4.11.1 CPU Interrupt Event (CPU_INT)
        2. 2.4.11.2 Nonmaskable Interrupt Event (NMI)
    5. 2.5 SYSCTL Layout Types
    6. 2.6 SYSCTL_TYPEA Registers
    7. 2.7 SYSCTL_TYPEB Registers
    8. 2.8 SYSCTL_TYPEC Registers
    9. 2.9 Quick Start Reference
      1. 2.9.1 Default Device Configuration
      2. 2.9.2 Leveraging MFCLK
      3. 2.9.3 Optimizing Power Consumption in STOP Mode
      4. 2.9.4 Optimizing Power Consumption in STANDBY Mode
      5. 2.9.5 Increasing MCLK Precision
      6. 2.9.6 High Speed Clock (SYSPLL, HFCLK) Handling in Low-Power Modes
      7. 2.9.7 Optimizing for Lowest Wakeup Latency
      8. 2.9.8 Optimizing for Lowest Peak Current in RUN/SLEEP Mode
  5. 3 CPU
    1. 3.1 Overview
    2. 3.2 Arm Cortex-M0+ CPU
      1. 3.2.1 CPU Register File
      2. 3.2.2 Stack Behavior
      3. 3.2.3 Execution Modes and Privilege Levels
      4. 3.2.4 Address Space and Supported Data Sizes
    3. 3.3 Interrupts and Exceptions
      1. 3.3.1 Peripheral Interrupts (IRQs)
        1. 3.3.1.1 Nested Vectored Interrupt Controller (NVIC)
        2. 3.3.1.2 Interrupt Groups
        3. 3.3.1.3 Wake Up Controller (WUC)
      2. 3.3.2 Interrupt and Exception Table
      3. 3.3.3 Processor Lockup Scenario
    4. 3.4 CPU Peripherals
      1. 3.4.1 System Control Block (SCB)
      2. 3.4.2 System Tick Timer (SysTick)
    5. 3.5 Read-Only Memory (ROM)
    6. 3.6 CPUSS Registers
    7. 3.7 WUC Registers
  6. 4 SECURITY
    1. 4.1 Overview
      1. 4.1.1 Secure Boot
      2. 4.1.2 Customer Secure Code (CSC)
    2. 4.2 Boot and Startup Sequence
      1. 4.2.1 CSC Programming Overview
    3. 4.3 Secure Key Storage
    4. 4.4 Flash Memory Protection
      1. 4.4.1 Bank Swapping
      2. 4.4.2 Write Protection
      3. 4.4.3 Read-Execute Protection
      4. 4.4.4 IP Protection
      5. 4.4.5 Data Bank Protection
      6. 4.4.6 Hardware Monotonic Counter
    5. 4.5 SRAM Protection
    6. 4.6 SECURITY Registers
  7. 5 Direct Memory Access (DMA)
    1. 5.1 DMA Overview
    2. 5.2 DMA Operation
      1. 5.2.1  Addressing Modes
      2. 5.2.2  Channel Types
      3. 5.2.3  Transfer Modes
        1. 5.2.3.1 Single Transfer
        2. 5.2.3.2 Block Transfer
        3. 5.2.3.3 Repeated Single Transfer
        4. 5.2.3.4 Repeated Block Transfer
        5. 5.2.3.5 Stride Mode
      4. 5.2.4  Extended Modes
        1. 5.2.4.1 Fill Mode
        2. 5.2.4.2 Table Mode
      5. 5.2.5  Initiating DMA Transfers
      6. 5.2.6  Stopping DMA Transfers
      7. 5.2.7  Channel Priorities
      8. 5.2.8  Burst Block Mode
      9. 5.2.9  Using DMA with System Interrupts
      10. 5.2.10 DMA Controller Interrupts
      11. 5.2.11 DMA Trigger Event Status
      12. 5.2.12 DMA Operating Mode Support
        1. 5.2.12.1 Transfer in RUN Mode
        2. 5.2.12.2 Transfer in SLEEP Mode
        3. 5.2.12.3 Transfer in STOP Mode
        4. 5.2.12.4 Transfers in STANDBY Mode
      13. 5.2.13 DMA Address and Data Errors
      14. 5.2.14 Interrupt and Event Support
    3. 5.3 DMA Registers
  8. 6 NVM (Flash)
    1. 6.1 NVM Overview
      1. 6.1.1 Key Features
      2. 6.1.2 System Components
      3. 6.1.3 Terminology
    2. 6.2 Flash Memory Bank Organization
      1. 6.2.1 Banks
      2. 6.2.2 Flash Memory Regions
      3. 6.2.3 Addressing
        1. 6.2.3.1 Flash Memory Map
      4. 6.2.4 Memory Organization Examples
    3. 6.3 Flash Controller
      1. 6.3.1 Overview of Flash Controller Commands
      2. 6.3.2 NOOP Command
      3. 6.3.3 PROGRAM Command
        1. 6.3.3.1 Program Bit Masking Behavior
        2. 6.3.3.2 Programming Less Than One Flash Word
        3. 6.3.3.3 Target Data Alignment (Devices with Single Flash Word Programming Only)
        4. 6.3.3.4 Target Data Alignment (Devices With Multiword Programming)
        5. 6.3.3.5 Executing a PROGRAM Operation
      4. 6.3.4 ERASE Command
        1. 6.3.4.1 Erase Sector Masking Behavior
        2. 6.3.4.2 Executing an ERASE Operation
      5. 6.3.5 READVERIFY Command
        1. 6.3.5.1 Executing a READVERIFY Operation
      6. 6.3.6 BLANKVERIFY Command
        1. 6.3.6.1 Executing a BLANKVERIFY Operation
      7. 6.3.7 Command Diagnostics
        1. 6.3.7.1 Command Status
        2. 6.3.7.2 Address Translation
        3. 6.3.7.3 Pulse Counts
      8. 6.3.8 Overriding the System Address With a Bank ID, Region ID, and Bank Address
      9. 6.3.9 FLASHCTL Events
        1. 6.3.9.1 CPU Interrupt Event Publisher
    4. 6.4 Write Protection
      1. 6.4.1 Write Protection Resolution
      2. 6.4.2 Static Write Protection
      3. 6.4.3 Dynamic Write Protection
        1. 6.4.3.1 Configuring Protection for the MAIN Region
        2. 6.4.3.2 Configuring Protection for the NONMAIN Region
    5. 6.5 Read Interface
      1. 6.5.1 Bank Address Swapping
    6. 6.6 FLASHCTL Registers
  9. 7 Events
    1. 7.1 Events Overview
      1. 7.1.1 Event Publisher
      2. 7.1.2 Event Subscriber
      3. 7.1.3 Event Fabric Routing
        1. 7.1.3.1 CPU Interrupt Event Route (CPU_INT)
        2. 7.1.3.2 DMA Trigger Event Route (DMA_TRIGx)
        3. 7.1.3.3 Generic Event Route (GEN_EVENTx)
      4. 7.1.4 Event Routing Map
      5. 7.1.5 Event Propagation Latency
    2. 7.2 Events Operation
      1. 7.2.1 CPU Interrupt
      2. 7.2.2 DMA Trigger
      3. 7.2.3 Peripheral to Peripheral Event
      4. 7.2.4 Extended Module Description Register
      5. 7.2.5 Using Event Registers
        1. 7.2.5.1 Event Registers
        2. 7.2.5.2 Configuring Events
        3. 7.2.5.3 Responding to CPU Interrupts in Application Software
        4. 7.2.5.4 Hardware Event Handling
  10. 8 IOMUX
    1. 8.1 IOMUX Overview
      1. 8.1.1 IO Types and Analog Sharing
    2. 8.2 IOMUX Operation
      1. 8.2.1 Peripheral Function (PF) Assignment
      2. 8.2.2 Logic High to Hi-Z Conversion
      3. 8.2.3 Logic Inversion
      4. 8.2.4 SHUTDOWN Mode Wakeup Logic
      5. 8.2.5 Pullup/Pulldown Resistors
      6. 8.2.6 Drive Strength Control
      7. 8.2.7 Hysteresis and Logic Level Control
    3. 8.3 IOMUX Registers
  11. 9 General-Purpose Input/Output (GPIO)
    1. 9.1 GPIO Overview
    2. 9.2 GPIO Operation
      1. 9.2.1 GPIO Ports
      2. 9.2.2 GPIO Read/Write Interface
      3. 9.2.3 GPIO Input Glitch Filtering and Synchronization
      4. 9.2.4 GPIO Fast Wake
      5. 9.2.5 GPIO DMA Interface
      6. 9.2.6 Event Publishers and Subscribers
    3. 9.3 GPIO Registers
  12. 10AES
    1. 10.1 AES Overview
      1. 10.1.1 AESADV Performance
    2. 10.2 AESADV Operation
      1. 10.2.1 Loading the Key
      2. 10.2.2 Writing Input Data
      3. 10.2.3 Reading Output Data
      4. 10.2.4 Operation Descriptions
        1. 10.2.4.1 Single Block Operation
        2. 10.2.4.2 Electronic Codebook (ECB) Mode
          1. 10.2.4.2.1 ECB Encryption
          2. 10.2.4.2.2 ECB Decryption
        3. 10.2.4.3 Cipher Block Chaining (CBC) Mode
          1. 10.2.4.3.1 CBC Encryption
          2. 10.2.4.3.2 CBC Decryption
        4. 10.2.4.4 Output Feedback (OFB) Mode
          1. 10.2.4.4.1 OFB Encryption
          2. 10.2.4.4.2 OFB Decryption
        5. 10.2.4.5 Cipher Feedback (CFB) Mode
          1. 10.2.4.5.1 CFB Encryption
          2. 10.2.4.5.2 CFB Decryption
        6. 10.2.4.6 Counter (CTR) Mode
          1. 10.2.4.6.1 CTR Encryption
          2. 10.2.4.6.2 CTR Decryption
        7. 10.2.4.7 Galois Counter (GCM) Mode
          1. 10.2.4.7.1 GHASH Operation
          2. 10.2.4.7.2 GCM Operating Modes
            1. 10.2.4.7.2.1 Autonomous GCM Operation
              1. 10.2.4.7.2.1.1 GMAC
            2. 10.2.4.7.2.2 GCM With Pre-Calculations
            3. 10.2.4.7.2.3 GCM Operation With Precalculated H- and Y0-Encrypted Forced to Zero
        8. 10.2.4.8 Counter With Cipher Block Chaining Message Authentication Code (CCM)
          1. 10.2.4.8.1 CCM Operation
      5. 10.2.5 AES Events
        1. 10.2.5.1 CPU Interrupt Event Publisher (CPU_EVENT)
        2. 10.2.5.2 DMA Trigger Event Publisher (DMA_TRIG_DATAIN)
        3. 10.2.5.3 DMA Trigger Event Publisher (DMA_TRIG_DATAOUT)
    3. 10.3 AESADV Registers
  13. 11CRC
    1. 11.1 CRC Overview
      1. 11.1.1 CRC16-CCITT
      2. 11.1.2 CRC32-ISO3309
    2. 11.2 CRC Operation
      1. 11.2.1 CRC Generator Implementation
      2. 11.2.2 Configuration
        1. 11.2.2.1 Polynomial Selection
        2. 11.2.2.2 Bit Order
        3. 11.2.2.3 Byte Swap
        4. 11.2.2.4 Byte Order
        5. 11.2.2.5 CRC C Library Compatibility
    3. 11.3 CRCP0 Registers
  14. 12Keystore
    1. 12.1 Overview
    2. 12.2 Detailed Description
    3. 12.3 KEYSTORECTL Registers
  15. 13TRNG
    1. 13.1 TRNG Overview
    2. 13.2 TRNG Operation
      1. 13.2.1 TRNG Generation Data Path
      2. 13.2.2 Clock Configuration and Output Rate
      3. 13.2.3 Behavior in Low Power Modes
      4. 13.2.4 Health Tests
        1. 13.2.4.1 Digital Block Startup Self-Test
        2. 13.2.4.2 Analog Block Startup Self-Test
        3. 13.2.4.3 Runtime Health Test
          1. 13.2.4.3.1 Repetition Count Test
          2. 13.2.4.3.2 Adaptive Proportion Test
          3. 13.2.4.3.3 Handling Runtime Health Test Failures
      5. 13.2.5 Configuration
        1. 13.2.5.1 TRNG State Machine
          1. 13.2.5.1.1 Changing TRNG States
        2. 13.2.5.2 Using the TRNG
        3. 13.2.5.3 TRNG Events
          1. 13.2.5.3.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 13.3 TRNG Registers
  16. 14Temperature Sensor
  17. 15ADC
    1. 15.1 ADC Overview
    2. 15.2 ADC Operation
      1. 15.2.1  ADC Core
      2. 15.2.2  Voltage Reference Options
      3. 15.2.3  Generic Resolution Modes
      4. 15.2.4  Hardware Averaging
      5. 15.2.5  ADC Clocking
      6. 15.2.6  Common ADC Use Cases
      7. 15.2.7  Power Down Behavior
      8. 15.2.8  Sampling Trigger Sources and Sampling Modes
        1. 15.2.8.1 AUTO Sampling Mode
        2. 15.2.8.2 MANUAL Sampling Mode
      9. 15.2.9  Sampling Period
      10. 15.2.10 Conversion Modes
      11. 15.2.11 Data Format
      12. 15.2.12 Advanced Features
        1. 15.2.12.1 Window Comparator
        2. 15.2.12.2 DMA and FIFO Operation
        3. 15.2.12.3 Analog Peripheral Interconnection
      13. 15.2.13 Status Register
      14. 15.2.14 ADC Events
        1. 15.2.14.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 15.2.14.2 Generic Event Publisher (GEN_EVENT)
        3. 15.2.14.3 DMA Trigger Event Publisher (DMA_TRIG)
        4. 15.2.14.4 Generic Event Subscriber (FSUB_0)
    3. 15.3 ADC12 Registers
  18. 16COMP
    1. 16.1 Comparator Overview
    2. 16.2 Comparator Operation
      1. 16.2.1  Comparator Configuration
      2. 16.2.2  Comparator Channels Selection
      3. 16.2.3  Comparator Output
      4. 16.2.4  Output Filter
      5. 16.2.5  Sampled Output Mode
      6. 16.2.6  Blanking Mode
      7. 16.2.7  Reference Voltage Generator
      8. 16.2.8  Comparator Hysteresis
      9. 16.2.9  Input SHORT Switch
      10. 16.2.10 Interrupt and Events Support
        1. 16.2.10.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 16.2.10.2 Generic Event Publisher (GEN_EVENT)
        3. 16.2.10.3 Generic Event Subscribers
    3. 16.3 COMP0 Registers
  19. 17OPA
    1. 17.1 OPA Overview
    2. 17.2 OPA Operation
      1. 17.2.1 Analog Core
      2. 17.2.2 Power Up Behavior
      3. 17.2.3 Inputs
      4. 17.2.4 Output
      5. 17.2.5 Clock Requirements
      6. 17.2.6 Chopping
      7. 17.2.7 OPA Amplifier Modes
        1. 17.2.7.1 General-Purpose Mode
        2. 17.2.7.2 Buffer Mode
        3. 17.2.7.3 OPA PGA Mode
          1. 17.2.7.3.1 Inverting PGA Mode
          2. 17.2.7.3.2 Non-inverting PGA Mode
        4. 17.2.7.4 Difference Amplifier Mode
        5. 17.2.7.5 Cascade Amplifier Mode
      8. 17.2.8 OPA Configuration Selection
      9. 17.2.9 Burnout Current Source
    3. 17.3 OA Registers
  20. 18GPAMP
    1. 18.1 GPAMP Overview
    2. 18.2 GPAMP Operation
      1. 18.2.1 Analog Core
      2. 18.2.2 Power Up Behavior
      3. 18.2.3 Inputs
      4. 18.2.4 Output
      5. 18.2.5 GPAMP Amplifier Modes
        1. 18.2.5.1 General-Purpose Mode
        2. 18.2.5.2 ADC Buffer Mode
        3. 18.2.5.3 Unity Gain Mode
      6. 18.2.6 Chopping
    3. 18.3 GPAMP Registers
  21. 19VREF
    1. 19.1 VREF Overview
    2. 19.2 VREF Operation
      1. 19.2.1 Internal Reference Generation
      2. 19.2.2 External Reference Input
      3. 19.2.3 Analog Peripheral Interface
    3. 19.3 VREF Registers
  22. 20LCD
    1. 20.1 LCD Introduction
      1. 20.1.1 LCD Operating Principle
      2. 20.1.2 Static Mode
      3. 20.1.3 2-Mux Mode
      4. 20.1.4 3-Mux Mode
      5. 20.1.5 4-Mux Mode
      6. 20.1.6 6-Mux Mode
      7. 20.1.7 8-Mux Mode
      8. 20.1.8 Introduction
      9. 20.1.9 LCD Waveforms
    2. 20.2 LCD Clocking
    3. 20.3 Voltage Generation
      1. 20.3.1  Mode 0 - Voltage Generation from external reference and external resistor divider
      2. 20.3.2  Mode 1 - Voltage Generation from AVDD and external resistor divider
      3. 20.3.3  Mode 2 - Voltage Generation from external reference and internal resistor divider
      4. 20.3.4  Mode 3 - Voltage Generation From AVDD and Internal Resistor Ladder
      5. 20.3.5  Mode 4 - Voltage Generation from charge pump with external supply
      6. 20.3.6  Mode 5 - Voltage Generation From Charge Pump With AVDD
      7. 20.3.7  Mode 6 - Voltage Generation From Charge Pump With External Reference on R13
      8. 20.3.8  Mode 7 - Voltage Generation From Charge Pump With Internal Reference on R13
      9. 20.3.9  Charge pump
      10. 20.3.10 Internal Reference Generation
    4. 20.4 Analog Mux
      1. 20.4.1 Static Mode
      2. 20.4.2 Non-Static 1/3 bias mode
      3. 20.4.3 Non-Static 1/4 bias mode
      4. 20.4.4 Low power mode switch controls
    5. 20.5 LCD Memory and output drive
      1. 20.5.1 LCD Memory organization
        1. 20.5.1.1 Memory Organization in Mux-1 to Mux-4 Modes
        2. 20.5.1.2 Memory Organization in Mux-5 to Mux-8 Modes
        3. 20.5.1.3 Configuring memory
        4. 20.5.1.4 Accessing memory and output drive
        5. 20.5.1.5 Blinking Override
    6. 20.6 IO Muxing
    7. 20.7 Interrupt Generation
    8. 20.8 Power Domains and Power Modes
    9. 20.9 LCD Registers
  23. 21UART
    1. 21.1 UART Overview
      1. 21.1.1 Purpose of the Peripheral
      2. 21.1.2 Features
      3. 21.1.3 Functional Block Diagram
    2. 21.2 UART Operation
      1. 21.2.1 Clock Control
      2. 21.2.2 Signal Descriptions
      3. 21.2.3 General Architecture and Protocol
        1. 21.2.3.1  Transmit Receive Logic
        2. 21.2.3.2  Bit Sampling
        3. 21.2.3.3  Majority Voting Feature
        4. 21.2.3.4  Baud Rate Generation
        5. 21.2.3.5  Data Transmission
        6. 21.2.3.6  Error and Status
        7. 21.2.3.7  Local Interconnect Network (LIN) Support
          1. 21.2.3.7.1 LIN Responder Transmission Delay
        8. 21.2.3.8  Flow Control
        9. 21.2.3.9  Idle-Line Multiprocessor
        10. 21.2.3.10 9-Bit UART Mode
        11. 21.2.3.11 RS-485 Support
        12. 21.2.3.12 DALI Protocol
        13. 21.2.3.13 Manchester Encoding and Decoding
        14. 21.2.3.14 IrDA Encoding and Decoding
        15. 21.2.3.15 ISO7816 Smart Card Support
        16. 21.2.3.16 Address Detection
        17. 21.2.3.17 FIFO Operation
        18. 21.2.3.18 Loopback Operation
        19. 21.2.3.19 Glitch Suppression
      4. 21.2.4 Low Power Operation
      5. 21.2.5 Reset Considerations
      6. 21.2.6 Initialization
      7. 21.2.7 Interrupt and Events Support
        1. 21.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 21.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 21.2.8 Emulation Modes
    3. 21.3 UART Registers
  24. 22I2C
    1. 22.1 I2C Overview
      1. 22.1.1 Purpose of the Peripheral
      2. 22.1.2 Features
      3. 22.1.3 Functional Block Diagram
      4. 22.1.4 Environment and External Connections
    2. 22.2 I2C Operation
      1. 22.2.1 Clock Control
        1. 22.2.1.1 Clock Select and I2C Speed
        2. 22.2.1.2 Clock Startup
      2. 22.2.2 Signal Descriptions
      3. 22.2.3 General Architecture
        1. 22.2.3.1  I2C Bus Functional Overview
        2. 22.2.3.2  START and STOP Conditions
        3. 22.2.3.3  Data Format with 7-Bit Address
        4. 22.2.3.4  Acknowledge
        5. 22.2.3.5  Repeated Start
        6. 22.2.3.6  SCL Clock Low Timeout
        7. 22.2.3.7  Clock Stretching
        8. 22.2.3.8  Dual Address
        9. 22.2.3.9  Arbitration
        10. 22.2.3.10 Multiple Controller Mode
        11. 22.2.3.11 Glitch Suppression
        12. 22.2.3.12 FIFO operation
          1. 22.2.3.12.1 Flushing Stale Tx Data in Target Mode
        13. 22.2.3.13 Loopback mode
        14. 22.2.3.14 Burst Mode
        15. 22.2.3.15 DMA Operation
        16. 22.2.3.16 Low-Power Operation
      4. 22.2.4 Protocol Descriptions
        1. 22.2.4.1 I2C Controller Mode
          1. 22.2.4.1.1 Controller Configuration
          2. 22.2.4.1.2 Controller Mode Operation
          3. 22.2.4.1.3 Read On TX Empty
        2. 22.2.4.2 I2C Target Mode
          1. 22.2.4.2.1 Target Mode Operation
      5. 22.2.5 Reset Considerations
      6. 22.2.6 Initialization
      7. 22.2.7 Interrupt and Events Support
        1. 22.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 22.2.7.2 DMA Trigger Publisher (DMA_TRIG1, DMA_TRIG0)
      8. 22.2.8 Emulation Modes
    3. 22.3 I2C Registers
  25. 23SPI
    1. 23.1 SPI Overview
      1. 23.1.1 Purpose of the Peripheral
      2. 23.1.2 Features
      3. 23.1.3 Functional Block Diagram
      4. 23.1.4 External Connections and Signal Descriptions
    2. 23.2 SPI Operation
      1. 23.2.1 Clock Control
      2. 23.2.2 General Architecture
        1. 23.2.2.1 Chip Select and Command Handling
          1. 23.2.2.1.1 Chip Select Control
          2. 23.2.2.1.2 Command Data Control
        2. 23.2.2.2 Data Format
        3. 23.2.2.3 Delayed data sampling
        4. 23.2.2.4 Clock Generation
        5. 23.2.2.5 FIFO Operation
        6. 23.2.2.6 Loopback mode
        7. 23.2.2.7 DMA Operation
        8. 23.2.2.8 Repeat Transfer mode
        9. 23.2.2.9 Low Power Mode
      3. 23.2.3 Protocol Descriptions
        1. 23.2.3.1 Motorola SPI Frame Format
        2. 23.2.3.2 Texas Instruments Synchronous Serial Frame Format
      4. 23.2.4 Reset Considerations
      5. 23.2.5 Initialization
      6. 23.2.6 Interrupt and Events Support
        1. 23.2.6.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 23.2.6.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      7. 23.2.7 Emulation Modes
    3. 23.3 SPI Registers
  26. 24UNICOMM
    1. 24.1 Overview
      1. 24.1.1 Block Diagram
    2. 24.2 Unicomm Architecture
      1. 24.2.1 Serial Peripheral Group (SPG) Configurations
        1. 24.2.1.1 I2C Pairings
      2. 24.2.2 Enables & Resets
    3. 24.3 High-Level Initialization
    4. 24.4 UNICOMM/SPGSS Registers
      1. 24.4.1 UNICOMM Registers
        1. 24.4.1.1 UNICOMM Registers
      2. 24.4.2 SPG Registers
        1. 24.4.2.1 SPGSS Registers
  27. 25UNICOMM UART
    1. 25.1 UART Overview
      1. 25.1.1 Purpose of the Peripheral
      2. 25.1.2 Features
      3. 25.1.3 Functional Block Diagram
    2. 25.2 UART Operation
      1. 25.2.1 Clock Control
      2. 25.2.2 General Architecture and Protocol
        1. 25.2.2.1 Signal Descriptions
        2. 25.2.2.2 Transmit and Receive Logic
        3. 25.2.2.3 Bit Sampling
        4. 25.2.2.4 Baud Rate Generation
        5. 25.2.2.5 Data Transmission
        6. 25.2.2.6 Error and Status
        7. 25.2.2.7 DMA Operation
        8. 25.2.2.8 Internal Loopback Operation
      3. 25.2.3 Additional Protocol and Feature Support
        1. 25.2.3.1  Local Interconnect Network (LIN) Support
          1. 25.2.3.1.1 LIN Commander Transmit
          2. 25.2.3.1.2 LIN Responder Receive
          3. 25.2.3.1.3 LIN Responder Transmission Delay
        2. 25.2.3.2  Flow Control
        3. 25.2.3.3  RS485 Support
        4. 25.2.3.4  FIFO Operation
        5. 25.2.3.5  Idle-Line Multiprocessor
        6. 25.2.3.6  9-Bit UART Mode
        7. 25.2.3.7  DALI Protocol
        8. 25.2.3.8  Manchester Encoding and Decoding
        9. 25.2.3.9  IrDA Encoding and Decoding
        10. 25.2.3.10 ISO7816 Smart Card Support
        11. 25.2.3.11 Address Detection
        12. 25.2.3.12 Glitch Suppression
      4. 25.2.4 Low Power Operation
      5. 25.2.5 Reset Considerations
      6. 25.2.6 UART Initialization
      7. 25.2.7 Interrupt and Events Support
        1. 25.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 25.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 25.2.8 Emulation Modes
    3. 25.3 UNICOMMUART Registers
  28. 26UNICOMM-I2C
    1. 26.1 UNICOMM-I2C Overview
      1. 26.1.1 Purpose of the Peripheral
      2. 26.1.2 Features
      3. 26.1.3 Functional Block Diagram
      4. 26.1.4 Environment and External Connections
    2. 26.2 UNICOMM Common Infrastructure
    3. 26.3 Peripheral Functional Description
      1. 26.3.1 Clock Control
        1. 26.3.1.1 Clock Select and I2C Speed
        2. 26.3.1.2 Clock Startup
      2. 26.3.2 Signal Descriptions
      3. 26.3.3 General Architecture
        1. 26.3.3.1  I2C Bus Functional Overview
        2. 26.3.3.2  START and STOP Conditions
        3. 26.3.3.3  Dual Address
        4. 26.3.3.4  Address Format
          1. 26.3.3.4.1 Data Format with 7-Bit Address
          2. 26.3.3.4.2 Data Format with 10-Bit Address
        5. 26.3.3.5  Acknowledge
        6. 26.3.3.6  Repeated Start
        7. 26.3.3.7  Clock Stretching
        8. 26.3.3.8  Clock Low Timeout
        9. 26.3.3.9  Burst Mode
        10. 26.3.3.10 Arbitration
        11. 26.3.3.11 Multiple Controller Mode
        12. 26.3.3.12 Glitch Suppression
        13. 26.3.3.13 DMA Operation
        14. 26.3.3.14 FIFO Operation
          1. 26.3.3.14.1 FIFO Status Flags
          2. 26.3.3.14.2 FIFO Levels
          3. 26.3.3.14.3 Clearing FIFO Contents
        15. 26.3.3.15 Suspend Communication
        16. 26.3.3.16 Low Power Operation
        17. 26.3.3.17 SMBUS 3.0 Support
          1. 26.3.3.17.1 Quick Command
          2. 26.3.3.17.2 SMBUS Enhanced Acknowledge Control
          3. 26.3.3.17.3 Clock Low Timeout Detection
          4. 26.3.3.17.4 Clock High Timeout Detection
          5. 26.3.3.17.5 Cumulative Clock Low Extended Timeout
          6. 26.3.3.17.6 Packet Error Checking (PEC)
          7. 26.3.3.17.7 Host Notify Protocol
          8. 26.3.3.17.8 Alert Response Protocol
          9. 26.3.3.17.9 Address Resolution Protocol
      4. 26.3.4 Protocol Descriptions & Initialization
        1. 26.3.4.1 I2C Controller Mode
          1. 26.3.4.1.1 I2C Controller Initialization
          2. 26.3.4.1.2 I2C Controller Status
          3. 26.3.4.1.3 I2C Controller Receive Mode
          4. 26.3.4.1.4 I2C Controller Transmitter Mode
          5. 26.3.4.1.5 Controller Transaction Configurations
        2. 26.3.4.2 I2C Target Mode
          1. 26.3.4.2.1 I2C Target Initialization
          2. 26.3.4.2.2 I2C Target Status
          3. 26.3.4.2.3 I2C Target Receiver Mode
          4. 26.3.4.2.4 I2C Target Transmitter Mode
      5. 26.3.5 Reset Considerations
      6. 26.3.6 Initialization
      7. 26.3.7 Interrupt and Events Support
        1. 26.3.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 26.3.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 26.3.8 Emulation Modes
    4. 26.4 UNICOMM I2C Registers
      1. 26.4.1 UNICOMMI2CC Registers
      2. 26.4.2 UNICOMMI2CT Registers
  29. 27UNICOMM-SPI
    1. 27.1 UNICOMM-SPI Overview
      1. 27.1.1 Purpose of the Peripheral
      2. 27.1.2 Features
      3. 27.1.3 Functional Block Diagram
      4. 27.1.4 External Connections and Signal Descriptions
    2. 27.2 SPI Operation
      1. 27.2.1  Clock Frequency Support
        1. 27.2.1.1 SPI Clock Generation
      2. 27.2.2  General Architecture
        1. 27.2.2.1 Chip Select and Command Handling
          1. 27.2.2.1.1 Chip Select Control
        2. 27.2.2.2 Command Data Control
        3. 27.2.2.3 Data Format
        4. 27.2.2.4 Delayed data sampling
        5. 27.2.2.5 DMA Operation
      3. 27.2.3  FIFO Operation
        1. 27.2.3.1 FIFO Size
        2. 27.2.3.2 FIFO Status bits
          1. 27.2.3.2.1 RIS.RX based on FIFO threshold settings
          2. 27.2.3.2.2 RIS.TX based on FIFO threshold settings
        3. 27.2.3.3 Clearing FIFO contents
        4. 27.2.3.4 Hardware monitors empty, full and overflow conditions
      4. 27.2.4  Suspend communication
        1. 27.2.4.1 SPI IDLE State Requirements
      5. 27.2.5  Internal Loopback Operation
      6. 27.2.6  Repeat Transfer mode
      7. 27.2.7  Receive Timeout
      8. 27.2.8  Line Timeout
      9. 27.2.9  Protocol Descriptions
        1. 27.2.9.1 Motorola SPI Frame Format
        2. 27.2.9.2 Texas Instruments Synchronous Serial Frame Format
      10. 27.2.10 Status Flags
      11. 27.2.11 Module configuration
      12. 27.2.12 Reset Considerations
      13. 27.2.13 Initialization
      14. 27.2.14 Interrupt and Events Support
        1. 27.2.14.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 27.2.14.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      15. 27.2.15 Emulation Modes
        1. 27.2.15.1 Graceful Halt
    3. 27.3 UNICOMMSPI Registers
  30. 28Timers (TIMx)
    1. 28.1 TIMx Overview
      1. 28.1.1 TIMG Overview
        1. 28.1.1.1 TIMG Features
        2. 28.1.1.2 Functional Block Diagram
      2. 28.1.2 TIMA Overview
        1. 28.1.2.1 TIMA Features
        2. 28.1.2.2 Functional Block Diagram
      3. 28.1.3 TIMx Instance Configuration
    2. 28.2 TIMx Operation
      1. 28.2.1  Timer Counter
        1. 28.2.1.1 Clock Source Select and Prescaler
          1. 28.2.1.1.1 Internal Clock and Prescaler
          2. 28.2.1.1.2 External Signal Trigger
        2. 28.2.1.2 Repeat Counter (TIMA only)
      2. 28.2.2  Counting Mode Control
        1. 28.2.2.1 One-shot and Periodic Modes
        2. 28.2.2.2 Down Counting Mode
        3. 28.2.2.3 Up/Down Counting Mode
        4. 28.2.2.4 Up Counting Mode
        5. 28.2.2.5 Phase Load (TIMA only)
      3. 28.2.3  Capture/Compare Module
        1. 28.2.3.1 Capture Mode
          1. 28.2.3.1.1 Input Selection, Counter Conditions, and Inversion
            1. 28.2.3.1.1.1 CCP Input Edge Synchronization
            2. 28.2.3.1.1.2 CCP Input Pulse Conditions
            3. 28.2.3.1.1.3 Counter Control Operation
            4. 28.2.3.1.1.4 CCP Input Filtering
            5. 28.2.3.1.1.5 Input Selection
          2. 28.2.3.1.2 Use Cases
            1. 28.2.3.1.2.1 Edge Time Capture
            2. 28.2.3.1.2.2 Period Capture
            3. 28.2.3.1.2.3 Pulse Width Capture
            4. 28.2.3.1.2.4 Combined Pulse Width and Period Time
          3. 28.2.3.1.3 QEI Mode (TIMG with QEI support only)
            1. 28.2.3.1.3.1 QEI With 2-Signal
            2. 28.2.3.1.3.2 QEI With Index Input
            3. 28.2.3.1.3.3 QEI Error Detection
          4. 28.2.3.1.4 Hall Input Mode (TIMG with QEI support only)
        2. 28.2.3.2 Compare Mode
          1. 28.2.3.2.1 Edge Count
      4. 28.2.4  Shadow Load and Shadow Compare
        1. 28.2.4.1 Shadow Load (TIMG4-7, TIMA only)
        2. 28.2.4.2 Shadow Compare (TIMG4-7, TIMG12-13, TIMA only)
      5. 28.2.5  Output Generator
        1. 28.2.5.1 Configuration
        2. 28.2.5.2 Use Cases
          1. 28.2.5.2.1 Edge-Aligned PWM
          2. 28.2.5.2.2 Center-Aligned PWM
          3. 28.2.5.2.3 Asymmetric PWM (TIMA only)
          4. 28.2.5.2.4 Complementary PWM With Deadband Insertion (TIMA only)
        3. 28.2.5.3 Forced Output
      6. 28.2.6  Fault Handler (TIMA only)
        1. 28.2.6.1 Fault Input Conditioning
        2. 28.2.6.2 Fault Input Sources
        3. 28.2.6.3 Counter Behavior With Fault Conditions
        4. 28.2.6.4 Output Behavior With Fault Conditions
      7. 28.2.7  Synchronization With Cross Trigger
        1. 28.2.7.1 Main Timer Cross Trigger Configuration
        2. 28.2.7.2 Secondary Timer Cross Trigger Configuration
      8. 28.2.8  Low Power Operation
      9. 28.2.9  Interrupt and Event Support
        1. 28.2.9.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 28.2.9.2 Generic Event Publisher and Subscriber (GEN_EVENT0 and GEN_EVENT1)
        3. 28.2.9.3 Generic Subscriber Event Example (COMP to TIMx)
      10. 28.2.10 Debug Handler (TIMA Only)
    3. 28.3 TIMx Registers
  31. 29TIMB
    1. 29.1 TIMB Overview
      1. 29.1.1 Features
      2. 29.1.2 TIMB Block Diagram
    2. 29.2 TIMB Operation
      1. 29.2.1 Counter Block Operation
        1. 29.2.1.1 Clock Source Selection
        2. 29.2.1.2 Counter Reset Generation
        3. 29.2.1.3 Event Based Enable and Disable
        4. 29.2.1.4 Event Generation
        5. 29.2.1.5 Interrupt Generation
        6. 29.2.1.6 Counter Behavior on a Debug Halt
        7. 29.2.1.7 Hardware Locking of Configuration Registers
    3. 29.3 TIMB Example Applications
      1. 29.3.1 Periodic Interrupt Generation
      2. 29.3.2 Counter Chaining
      3. 29.3.3 Event Counting
      4. 29.3.4 Event Duration Measurement
      5. 29.3.5 Event Sequence Checking
      6. 29.3.6 PWM Generation
    4. 29.4 TIMB Registers
  32. 30Low Frequency Subsystem (LFSS)
    1. 30.1  Overview
    2. 30.2  Clock System
    3. 30.3  LFSS Reset Using VBAT
    4. 30.4  Power Domains and Supply Detection
      1. 30.4.1 Startup When VBAT Powers on First
      2. 30.4.2 Startup when VDD powers on first
      3. 30.4.3 Behavior When VDD is Lost
      4. 30.4.4 Behavior when VBAT is lost
      5. 30.4.5 Behavior when the device goes into SHUTDOWN mode
      6. 30.4.6 Supercapacitor Charging Circuit
    5. 30.5  Real Time Counter (RTC_x)
    6. 30.6  Independent Watchdog Timer (IWDT)
    7. 30.7  Tamper Input and Output
      1. 30.7.1 IOMUX Mode
      2. 30.7.2 Tamper Mode
        1. 30.7.2.1 Tamper Event Detection
        2. 30.7.2.2 Timestamp Event Output
        3. 30.7.2.3 Heartbeat Generator
        4. 30.7.2.4 RTC Clock Output
    8. 30.8  Scratchpad Memory
    9. 30.9  Lock Function of RTC, TIO, and IWDT
    10. 30.10 LFSS Registers
  33. 31Low Frequency Subsystem (LFSS_B)
    1. 31.1 Overview
    2. 31.2 Clock System
    3. 31.3 LFSS Reset
    4. 31.4 Real Time Counter (RTC_x)
    5. 31.5 Independent Watchdog Timer (IWDT)
    6. 31.6 Lock Function of RTC and IWDT
    7. 31.7 LFSS Registers
  34. 32RTC
    1. 32.1 Overview
      1. 32.1.1 RTC Instances
    2. 32.2 Basic Operation
    3. 32.3 Configuration
      1. 32.3.1  Clocking
      2. 32.3.2  Reading and Writing to RTC Peripheral Registers
      3. 32.3.3  Binary vs. BCD
      4. 32.3.4  Leap Year Handling
      5. 32.3.5  Calendar Alarm Configuration
      6. 32.3.6  Interval Alarm Configuration
      7. 32.3.7  Periodic Alarm Configuration
      8. 32.3.8  Calibration
        1. 32.3.8.1 Crystal Offset Error
          1. 32.3.8.1.1 Offset Error Correction Mechanism
        2. 32.3.8.2 Crystal Temperature Error
          1. 32.3.8.2.1 Temperature Drift Correction Mechanism
      9. 32.3.9  RTC Prescaler Extension
      10. 32.3.10 RTC Timestamp Capture
      11. 32.3.11 RTC Events
        1. 32.3.11.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 32.3.11.2 Generic Event Publisher (GEN_EVENT)
    4. 32.4 RTC Registers
  35. 33IWDT
    1. 33.1 920
    2. 33.2 IWDT Clock Configuration
    3. 33.3 IWDT Period Selection
    4. 33.4 Debug Behavior of the IWDT
    5. 33.5 IWDT Registers
  36. 34Window Watchdog Timer (WWDT)
    1. 34.1 WWDT Overview
      1. 34.1.1 Watchdog Mode
      2. 34.1.2 Interval Timer Mode
    2. 34.2 WWDT Operation
      1. 34.2.1 Mode Selection
      2. 34.2.2 Clock Configuration
      3. 34.2.3 Low-Power Mode Behavior
      4. 34.2.4 Debug Behavior
      5. 34.2.5 WWDT Events
        1. 34.2.5.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 34.3 WWDT Registers
  37. 35Debug
    1. 35.1 DEBUGSS Overview
      1. 35.1.1 Debug Interconnect
      2. 35.1.2 Physical Interface
      3. 35.1.3 Debug Access Ports
    2. 35.2 DEBUGSS Operation
      1. 35.2.1 Debug Features
        1. 35.2.1.1 Processor Debug
          1. 35.2.1.1.1 Breakpoint Unit (BPU)
          2. 35.2.1.1.2 Data Watchpoint and Trace Unit (DWT)
        2. 35.2.1.2 Peripheral Debug
        3. 35.2.1.3 EnergyTrace Technology
      2. 35.2.2 Behavior in Low Power Modes
      3. 35.2.3 Restricting Debug Access
      4. 35.2.4 Mailbox (DSSM)
        1. 35.2.4.1 DSSM Events
          1. 35.2.4.1.1 CPU Interrupt Event (CPU_INT)
        2. 35.2.4.2 Reference
    3. 35.3 DEBUGSS Registers
  38. 36Revision History

27.3 UNICOMMSPI Registers

Table 27-7 lists the memory-mapped registers for the UNICOMMSPI registers. All register offset addresses not listed in Table 27-7 should be considered as reserved locations and the register contents should not be modified.

Table 27-7 UNICOMMSPI Registers
OffsetAcronymRegister NameGroupSection
1000hCLKDIVClock DividerGo
1008hCLKSELClock Select for Ultra Low Power peripheralsGo
1020hIIDXInterrupt Index RegisterCPU_INTGo
1028hIMASKInterrupt maskCPU_INTGo
1030hRISRaw interrupt statusCPU_INTGo
1038hMISMasked interrupt statusCPU_INTGo
1040hISETInterrupt setCPU_INTGo
1048hICLRInterrupt clearCPU_INTGo
1058hIMASKInterrupt maskDMA_TRIG_RXGo
1060hRISRaw interrupt statusDMA_TRIG_RXGo
1068hMISMasked interrupt statusDMA_TRIG_RXGo
1070hISETInterrupt setDMA_TRIG_RXGo
1088hIMASKInterrupt maskDMA_TRIG_TXGo
1090hRISRaw interrupt statusDMA_TRIG_TXGo
1098hMISMasked interrupt statusDMA_TRIG_TXGo
10A0hISETInterrupt setDMA_TRIG_TXGo
10E4hINTCTLInterrupt control registerGo
1100hCTL0SPI control register 0Go
1108hSTATStatus RegisterGo
110ChIFLSInterrupt FIFO Level Select RegisterGo
1110hCLKCTLClock prescaler and divider register.Go
1120hTXDATATXDATA RegisterGo
1124hRXDATARXDATA RegisterGo
114ChCTL1SPI control register 1Go

Complex bit access types are encoded to fit into small table cells. Table 27-8 shows the codes that are used for access types in this section.

Table 27-8 UNICOMMSPI Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
Reset or Default Value
-nValue after reset or the default value

27.3.1 CLKDIV (Offset = 1000h) [Reset = 00000000h]

CLKDIV is shown in Figure 27-8 and described in Table 27-9.

Return to the Summary Table.

SPI Clock Divider. This register is used to specify module-specific divide ratio of the functional clock

Figure 27-8 CLKDIV
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDRATIO
R-0hR/W-0h
Table 27-9 CLKDIV Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0h
2-0RATIOR/W0hSelects divide ratio of module clock
  • 0h = Do not divide clock source
  • 1h = Divide clock source by 2
  • 2h = Divide clock source by 3
  • 3h = Divide clock source by 4
  • 4h = Divide clock source by 5
  • 5h = Divide clock source by 6
  • 6h = Divide clock source by 7
  • 7h = Divide clock source by 8

27.3.2 CLKSEL (Offset = 1008h) [Reset = 00000000h]

CLKSEL is shown in Figure 27-9 and described in Table 27-10.

Return to the Summary Table.

SPI Source Clock Selection.

Figure 27-9 CLKSEL
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDASYNC_PLL_SELASYNC_HFCLK_SELASYNC_SYSCLK_SELASYNC_LFCLK_SEL
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
RESERVEDBUSCLK_SELMFCLK_SELLFCLK_SELRESERVED
R-0hR/W-0hR/W-0hR/W-0hR-0h
Table 27-10 CLKSEL Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0h
11ASYNC_PLL_SELR/W0hAsynchronous PLL selected as source
  • 0h = Does not select this clock as a source
  • 1h = Select this clock as a source
10ASYNC_HFCLK_SELR/W0hAsynchronous HFCLK selected as source
  • 0h = Does not select this clock as a source
  • 1h = Select this clock as a source
9ASYNC_SYSCLK_SELR/W0hAsynchronous sys clock selected as source
  • 0h = Does not select this clock as a source
  • 1h = Select this clock as a source
8ASYNC_LFCLK_SELR/W0hAsynchronous lfclk selected as source
  • 0h = Does not select this clock as a source
  • 1h = Select this clock as a source
7-4RESERVEDR0h
3BUSCLK_SELR/W0hSelects buscclk as clock source if enabled
  • 0h = Does not select this clock as a source
  • 1h = Select this clock as a source
2MFCLK_SELR/W0hSelects MFCLK as clock source if enabled
  • 0h = Does not select this clock as a source
  • 1h = Select this clock as a source
1LFCLK_SELR/W0hSelects LFCLK as clock source if enabled
  • 0h = Does not select this clock as a source
  • 1h = Select this clock as a source
0RESERVEDR0h

27.3.3 IIDX (Offset = 1020h) [Reset = 00000000h]

IIDX is shown in Figure 27-10 and described in Table 27-11.

Return to the Summary Table.

This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, … IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred. On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in [RIS] and [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.

Figure 27-10 IIDX
313029282726252423222120191817161514131211109876543210
RESERVEDSTAT
R-0hR-0h
Table 27-11 IIDX Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7-0STATR0hInterrupt index status
  • 00h = No interrupt pending
  • 1h = Transmit Parity Event/interrupt pending
  • 2h = RX FIFO Overflow Event/interrupt pending
  • 3h = Receive interrupt
  • 4h = RX FIFO Full Interrupt
  • 5h = TX FIFO underflow interrupt
  • 6h = Transmit Event
  • 7h = Transmit Buffer Empty Event/interrupt pending
  • 9h = End of Transmit Event/interrupt pending
  • Ah = SPI receive time-out interrupt
  • 10h = DMA DONE on RX
  • 11h = DMA DONE on TX
  • 13h = DMA PRE IRQ RX INTERRUPT
  • 14h = DMA PRE IRQ TX INTERRUPT
  • 15h = SPI line time-out interrupt

27.3.4 IMASK (Offset = 1028h) [Reset = 00000000h]

IMASK is shown in Figure 27-11 and described in Table 27-12.

Return to the Summary Table.

Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Figure 27-11 IMASK
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDLTOUTRESERVEDRESERVEDRESERVEDDMA_DONE_TX
R-0hR/W-0hR-0hR-0hR-0hR/W-0h
15141312111098
DMA_DONE_RXRESERVEDRTOUTIDLE
R/W-0hR-0hR/W-0hR/W-0h
76543210
RESERVEDTXEMPTYTXTXFIFO_UNFRXFULLRXRXFIFO_OVFPER
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 27-12 IMASK Field Descriptions
BitFieldTypeResetDescription
31-21RESERVEDR0h
20LTOUTR/W0hSPI Line Time-Out Interrupt Mask. This interrupt is raised when the UNICOMM-SPI is in peripheral mode, and no new transaction has been detected for the timeout period programmed by the CTL1.RXTIMEOUT field.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrupt Mask
19RESERVEDR0hReserved
18RESERVEDR0hReserved
17RESERVEDR0h
16DMA_DONE_TXR/W0hSPI DMA Done on TX Event Channel Interrupt Mask. This interrupt is raised when the DONE signal is sent to the SPI from a DMA indicating all the transactions have completed.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrupt Mask
15DMA_DONE_RXR/W0hSPI DMA Done on RX Event Channel Interrupt Mask. This interrupt is raised when the DONE signal is sent to the SPI from a DMA indicating all the transactions have completed.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrupt Mask
14-10RESERVEDR0h
9RTOUTR/W0hSPI Receive Time-Out Interrupt Mask. This interrupt is raised when the UNICOMM-SPI is in peripheral mode receiving data, the SCLK line is inactive while the RX FIFO contains at least one element for the timeout period programmed by the CTL1.RXTIMEOUT field, regardless of if the RX FIFO level configured in the IFLS register has been reached.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrupt Mask
8IDLER/W0hSPI Idle Interrupt Mask. This interrupt is raised when the SPI has finished transfers and gone into an idle state.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrupt Mask
7RESERVEDR0h
6TXEMPTYR/W0hSPI TX FIFO Empty Interrupt Mask. This interrupt is raised when all data has been shifted out of the TX FIFO and the SPI transmitter goes idle.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrupt Mask
5TXR/W0hSPI Transmit Interrupt Mask. This interrupt is raised when the TX FIFO level has met the condition configured in the IFLS register. For variants with only a Buffer, indicates that the buffer is empty.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrupt Mask
4TXFIFO_UNFR/W0hSPI TX FIFO Underflow Interrupt Mask. This interrupt is raised when the UNICOMM-SPI (in peripheral mode) gets clock edges on the SCLK line from the SPI controller, but the TX FIFO is empty.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrupt Mask
3RXFULLR/W0hSPI RX FIFO Full Interrupt Mask. This interrupt is raised when the RX FIFO is full.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrupt Mask
2RXR/W0hSPI Receive Interrupt Mask. This interrupt is raised when the RX FIFO level has met the condition configured in the IFLS register. For variants with only a Buffer, indicates that the buffer has received a character.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrupt Mask
1RXFIFO_OVFR/W0hSPI RX FIFO Overflow Interrupt Mask. This interrupt is raised when the SPI receiver tries to receive data, but the SPI RX FIFO is full. In this case, new data will be discarded/lost by the SPI receiver.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrupt Mask
0PERR/W0hSPI Parity Error Interrupt Mask. This interrupt is raised when a character is received with a mismatch between the calculated parity and the received parity.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrupt Mask

27.3.5 RIS (Offset = 1030h) [Reset = 00000000h]

RIS is shown in Figure 27-12 and described in Table 27-13.

Return to the Summary Table.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 27-12 RIS
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDLTOUTRESERVEDRESERVEDRESERVEDDMA_DONE_TX
R-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
DMA_DONE_RXRESERVEDRTOUTIDLE
R-0hR-0hR-0hR-0h
76543210
RESERVEDTXEMPTYTXTXFIFO_UNFRXFULLRXRXFIFO_OVFPER
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 27-13 RIS Field Descriptions
BitFieldTypeResetDescription
31-21RESERVEDR0h
20LTOUTR0hSPI Line Time-Out Interrupt Raw Status. This interrupt is raised when the UNICOMM-SPI is in peripheral mode, and no new transaction has been detected for the timeout period programmed by the CTL1.RXTIMEOUT field.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
19RESERVEDR0hReserved
18RESERVEDR0hReserved
17RESERVEDR0h
16DMA_DONE_TXR0hSPI DMA Done on TX Event Channel Interrupt Raw Status. This interrupt is raised when the DONE signal is sent to the SPI from a DMA indicating all the transactions have completed.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
15DMA_DONE_RXR0hSPI DMA Done on RX Event Channel Interrupt Raw Status. This interrupt is raised when the DONE signal is sent to the SPI from a DMA indicating all the transactions have completed.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
14-10RESERVEDR0h
9RTOUTR0hSPI Receive Time-Out Interrupt Raw Status. This interrupt is raised when the UNICOMM-SPI is in peripheral mode receiving data, the SCLK line is inactive while the RX FIFO contains at least one element for the timeout period programmed by the CTL1.RXTIMEOUT field, regardless of if the RX FIFO level configured in the IFLS register has been reached.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
8IDLER0hSPI Idle Interrupt Raw Status. This interrupt is raised when the SPI has finished transfers and gone into an idle state.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
7RESERVEDR0h
6TXEMPTYR0hSPI TX FIFO Empty Interrupt Raw Status. This interrupt is raised when all data has been shifted out of the TX FIFO and the SPI transmitter goes idle.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
5TXR0hSPI Transmit Interrupt Raw Status. This interrupt is raised when the TX FIFO level has met the condition configured in the IFLS register. For variants with only a Buffer, indicates that the buffer is empty.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
4TXFIFO_UNFR0hSPI TX FIFO Underflow Interrupt Raw Status. This interrupt is raised when the UNICOMM-SPI (in peripheral mode) gets clock edges on the SCLK line from the SPI controller, but the TX FIFO is empty.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
3RXFULLR0hSPI RX FIFO Full Interrupt Raw Status. This interrupt is raised when the RX FIFO is full.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
2RXR0hSPI Receive Interrupt Raw Status. This interrupt is raised when the RX FIFO level has met the condition configured in the IFLS register. For variants with only a Buffer, indicates that the buffer has received a character.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
1RXFIFO_OVFR0hSPI RX FIFO Overflow Interrupt Raw Status. This interrupt is raised when the SPI receiver tries to receive data, but the SPI RX FIFO is full. In this case, new data will be discarded/lost by the SPI receiver.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
0PERR0hSPI Parity Error Interrupt Raw Status. This interrupt is raised when a character is received with a mismatch between the calculated parity and the received parity.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred

27.3.6 MIS (Offset = 1038h) [Reset = 00000000h]

MIS is shown in Figure 27-13 and described in Table 27-14.

Return to the Summary Table.

Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 27-13 MIS
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDLTOUTRESERVEDRESERVEDRESERVEDDMA_DONE_TX
R-0hR-0hR-0hR-0hR-0hR-0h
15141312111098
DMA_DONE_RXRESERVEDRTOUTIDLE
R-0hR-0hR-0hR-0h
76543210
RESERVEDTXEMPTYTXTXFIFO_UNFRXFULLRXRXFIFO_OVFPER
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 27-14 MIS Field Descriptions
BitFieldTypeResetDescription
31-21RESERVEDR0h
20LTOUTR0hSPI Line Time-Out Interrupt Masked Status. This interrupt is raised when the UNICOMM-SPI is in peripheral mode, and no new transaction has been detected for the timeout period programmed by the CTL1.RXTIMEOUT field.
  • 0h = Interrupt did not occur or mask was not enabled
  • 1h = Interrupt occured
19RESERVEDR0hReserved
18RESERVEDR0hReserved
17RESERVEDR0h
16DMA_DONE_TXR0hSPI DMA Done on TX Event Channel Interrupt Masked Status. This interrupt is raised when the DONE signal is sent to the SPI from a DMA indicating all the transactions have completed.
  • 0h = Interrupt did not occur or mask was not enabled
  • 1h = Interrupt occurred
15DMA_DONE_RXR0hSPI DMA Done on RX Event Channel Interrupt Masked Status. This interrupt is raised when the DONE signal is sent to the SPI from a DMA indicating all the transactions have completed.
  • 0h = Interrupt did not occur or mask was not enabled
  • 1h = Interrupt occurred
14-10RESERVEDR0h
9RTOUTR0hSPI Receive Time-Out Interrupt Masked Status. This interrupt is raised when the UNICOMM-SPI is in peripheral mode receiving data, the SCLK line is inactive while the RX FIFO contains at least one element for the timeout period programmed by the CTL1.RXTIMEOUT field, regardless of if the RX FIFO level configured in the IFLS register has been reached.
  • 0h = Interrupt did not occur or mask was not enabled
  • 1h = Interrupt occured
8IDLER0hSPI Idle Interrupt Masked Status. This interrupt is raised when the SPI has finished transfers and gone into an idle state.
  • 0h = Interrupt did not occur or mask was not enabled
  • 1h = Interrupt occurred
7RESERVEDR0h
6TXEMPTYR0hSPI TX FIFO Empty Interrupt Masked Status. This interrupt is raised when all data has been shifted out of the TX FIFO and the SPI transmitter goes idle.
  • 0h = Interrupt did not occur or mask was not enabled
  • 1h = Interrupt occurred
5TXR0hSPI Transmit Interrupt Masked Status. This interrupt is raised when the TX FIFO level has met the condition configured in the IFLS register. For variants with only a Buffer, indicates that the buffer is empty.
  • 0h = Interrupt did not occur or mask was not enabled
  • 1h = Interrupt occurred
4TXFIFO_UNFR0hSPI TX FIFO Underflow Interrupt Masked Status. This interrupt is raised when the UNICOMM-SPI (in peripheral mode) gets clock edges on the SCLK line from the SPI controller, but the TX FIFO is empty.
  • 0h = Interrupt did not occur or mask was not enabled
  • 1h = Interrupt occurred
3RXFULLR0hSPI RX FIFO Full Interrupt Masked Status. This interrupt is raised when the RX FIFO is full.
  • 0h = Interrupt did not occur or mask was not enabled
  • 1h = Interrupt occurred
2RXR0hSPI Receive Interrupt Masked Status. This interrupt is raised when the RX FIFO level has met the condition configured in the IFLS register. For variants with only a Buffer, indicates that the buffer has received a character.
  • 0h = Interrupt did not occur or mask was not enabled
  • 1h = Interrupt occurred
1RXFIFO_OVFR0hSPI RX FIFO Overflow Interrupt Masked Status. This interrupt is raised when the SPI receiver tries to receive data, but the SPI RX FIFO is full. In this case, new data will be discarded/lost by the SPI receiver.
  • 0h = Interrupt did not occur or mask was not enabled
  • 1h = Interrupt occurred
0PERR0hSPI Parity Error Interrupt Masked Status. This interrupt is raised when a character is received with a mismatch between the calculated parity and the received parity.
  • 0h = Interrupt did not occur or mask was not enabled
  • 1h = Interrupt occurred

27.3.7 ISET (Offset = 1040h) [Reset = 00000000h]

ISET is shown in Figure 27-14 and described in Table 27-15.

Return to the Summary Table.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 27-14 ISET
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDLTOUTRESERVEDRESERVEDRESERVEDDMA_DONE_TX
R-0hW-0hR-0hR-0hR-0hW-0h
15141312111098
DMA_DONE_RXRESERVEDRTOUTIDLE
W-0hR-0hW-0hW-0h
76543210
RESERVEDTXEMPTYTXTXFIFO_UNFRXFULLRXRXFIFO_OVFPER
R-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 27-15 ISET Field Descriptions
BitFieldTypeResetDescription
31-21RESERVEDR0h
20LTOUTW0hSet SPI Line Time-Out Interrupt. This interrupt is raised when the UNICOMM-SPI is in peripheral mode, and no new transaction has been detected for the timeout period programmed by the CTL1.RXTIMEOUT field.
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
19RESERVEDR0hReserved
18RESERVEDR0hReserved
17RESERVEDR0h
16DMA_DONE_TXW0hSet SPI DMA Done on TX Event Channel Interrupt. This interrupt is raised when the DONE signal is sent to the SPI from a DMA indicating all the transactions have completed.
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
15DMA_DONE_RXW0hSet SPI DMA Done on RX Event Channel Interrupt. This interrupt is raised when the DONE signal is sent to the SPI from a DMA indicating all the transactions have completed.
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
14-10RESERVEDR0h
9RTOUTW0hSet SPI Receive Time-Out Interrupt. This interrupt is raised when the UNICOMM-SPI is in peripheral mode receiving data, the SCLK line is inactive while the RX FIFO contains at least one element for the timeout period programmed by the CTL1.RXTIMEOUT field, regardless of if the RX FIFO level configured in the IFLS register has been reached.
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
8IDLEW0hSet SPI Idle Interrupt. This interrupt is raised when the SPI has finished transfers and gone into an idle state.
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
7RESERVEDR0h
6TXEMPTYW0hSet SPI TX FIFO Empty Interrupt. This interrupt is raised when all data has been shifted out of the TX FIFO and the SPI transmitter goes idle.
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
5TXW0hSet SPI Transmit Interrupt. This interrupt is raised when the TX FIFO level has met the condition configured in the IFLS register. For variants with only a Buffer, indicates that the buffer is empty.
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
4TXFIFO_UNFW0hSet SPI TX FIFO Underflow Interrupt. This interrupt is raised when the UNICOMM-SPI (in peripheral mode) gets clock edges on the SCLK line from the SPI controller, but the TX FIFO is empty.
  • 0h = Writing has no effect
  • 1h = Set interrupt
3RXFULLW0hSet SPI RX FIFO Full Interrupt. This interrupt is raised when the RX FIFO is full.
  • 0h = Writing has no effect
  • 1h = Set Interrupt
2RXW0hSet SPI Receive Interrupt. This interrupt is raised when the RX FIFO level has met the condition configured in the IFLS register. For variants with only a Buffer, indicates that the buffer has received a character.
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
1RXFIFO_OVFW0hSet SPI RX FIFO Overflow Interrupt. This interrupt is raised when the SPI receiver tries to receive data, but the SPI RX FIFO is full. In this case, new data will be discarded/lost by the SPI receiver.
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
0PERW0hSet SPI Parity Error Interrupt. This interrupt is raised when a character is received with a mismatch between the calculated parity and the received parity.
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt

27.3.8 ICLR (Offset = 1048h) [Reset = 00000000h]

ICLR is shown in Figure 27-15 and described in Table 27-16.

Return to the Summary Table.

Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 27-15 ICLR
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDLTOUTRESERVEDRESERVEDRESERVEDDMA_DONE_TX
R-0hW-0hR-0hR-0hR-0hW-0h
15141312111098
DMA_DONE_RXRESERVEDRTOUTIDLE
W-0hR-0hW-0hW-0h
76543210
RESERVEDTXEMPTYTXTXFIFO_UNFRXFULLRXRXFIFO_OVFPER
R-0hW-0hW-0hW-0hW-0hW-0hW-0hW-0h
Table 27-16 ICLR Field Descriptions
BitFieldTypeResetDescription
31-21RESERVEDR0h
20LTOUTW0hClear SPI Line Time-Out Interrupt. This interrupt is raised when the UNICOMM-SPI is in peripheral mode, and no new transaction has been detected for the timeout period programmed by the CTL1.RXTIMEOUT field.
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
19RESERVEDR0hReserved
18RESERVEDR0hReserved
17RESERVEDR0h
16DMA_DONE_TXW0hClear SPI DMA Done on TX Event Channel Interrupt. This interrupt is raised when the DONE signal is sent to the SPI from a DMA indicating all the transactions have completed.
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
15DMA_DONE_RXW0hClear SPI DMA Done on RX Event Channel Interrupt. This interrupt is raised when the DONE signal is sent to the SPI from a DMA indicating all the transactions have completed.
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
14-10RESERVEDR0h
9RTOUTW0hClear SPI Receive Time-Out Interrupt. This interrupt is raised when the UNICOMM-SPI is in peripheral mode receiving data, the SCLK line is inactive while the RX FIFO contains at least one element for the timeout period programmed by the CTL1.RXTIMEOUT field, regardless of if the RX FIFO level configured in the IFLS register has been reached.
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
8IDLEW0hClear SPI Idle Interrupt. This interrupt is raised when the SPI has finished transfers and gone into an idle state.
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
7RESERVEDR0h
6TXEMPTYW0hClear SPI TX FIFO Empty Interrupt. This interrupt is raised when all data has been shifted out of the TX FIFO and the SPI transmitter goes idle.
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
5TXW0hClear SPI Transmit Interrupt. This interrupt is raised when the TX FIFO level has met the condition configured in the IFLS register. For variants with only a Buffer, indicates that the buffer is empty.
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
4TXFIFO_UNFW0hClear SPI TX FIFO Underflow Interrupt. This interrupt is raised when the UNICOMM-SPI (in peripheral mode) gets clock edges on the SCLK line from the SPI controller, but the TX FIFO is empty.
  • 0h = Writing has no effect
  • 1h = Clear interrupt
3RXFULLW0hClear SPI RX FIFO Full Interrupt. This interrupt is raised when the RX FIFO is full.
  • 0h = Writing has no effect
  • 1h = Clear interrupt
2RXW0hClear SPI Receive Interrupt. This interrupt is raised when the RX FIFO level has met the condition configured in the IFLS register. For variants with only a Buffer, indicates that the buffer has received a character.
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
1RXFIFO_OVFW0hClear SPI RX FIFO Overflow Interrupt. This interrupt is raised when the SPI receiver tries to receive data, but the SPI RX FIFO is full. In this case, new data will be discarded/lost by the SPI receiver.
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
0PERW0hClear SPI Parity Error Interrupt. This interrupt is raised when a character is received with a mismatch between the calculated parity and the received parity.
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt

27.3.9 IMASK (Offset = 1058h) [Reset = 00000000h]

IMASK is shown in Figure 27-16 and described in Table 27-17.

Return to the Summary Table.

Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Figure 27-16 IMASK
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRTOUTRESERVED
R-0hR/W-0hR-0h
76543210
RESERVEDRXRESERVED
R-0hR/W-0hR-0h
Table 27-17 IMASK Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0h
9RTOUTR/W0hSPI Receive Timeout DMA Trigger Mask. The DMA is triggered when the UNICOMM-SPI is in peripheral mode receiving data, the SCLK line is inactive while the RX FIFO contains at least one element for the timeout period programmed by the CTL1.RXTIMEOUT field, regardless of if the RX FIFO level configured in the IFLS register has been reached.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrupt Mask
8-3RESERVEDR0h
2RXR/W0hSPI Receive DMA Trigger Mask. The DMA is triggered when the RX FIFO condition programmed by the IFLS register is met. When FIFO is not present, this indicates that the buffer is full.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrupt Mask
1-0RESERVEDR0h

27.3.10 RIS (Offset = 1060h) [Reset = 00000000h]

RIS is shown in Figure 27-17 and described in Table 27-18.

Return to the Summary Table.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 27-17 RIS
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRTOUTRESERVED
R-0hR-0hR-0h
76543210
RESERVEDRXRESERVED
R-0hR-0hR-0h
Table 27-18 RIS Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0h
9RTOUTR0hSPI Receive Timeout DMA Trigger Raw Status. The DMA is triggered when the UNICOMM-SPI is in peripheral mode receiving data, the SCLK line is inactive while the RX FIFO contains at least one element for the timeout period programmed by the CTL1.RXTIMEOUT field, regardless of if the RX FIFO level configured in the IFLS register has been reached.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrupt Mask
8-3RESERVEDR0h
2RXR0hSPI Receive DMA Trigger Raw Status. The DMA is triggered when the RX FIFO condition programmed by the IFLS register is met. When FIFO is not present, this indicates that the buffer is full.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
1-0RESERVEDR0h

27.3.11 MIS (Offset = 1068h) [Reset = 00000000h]

MIS is shown in Figure 27-18 and described in Table 27-19.

Return to the Summary Table.

Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 27-18 MIS
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRTOUTRESERVED
R-0hR-0hR-0h
76543210
RESERVEDRXRESERVED
R-0hR-0hR-0h
Table 27-19 MIS Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0h
9RTOUTR0hSPI Receive Timeout DMA Trigger Masked Status. The DMA is triggered when the UNICOMM-SPI is in peripheral mode receiving data, the SCLK line is inactive while the RX FIFO contains at least one element for the timeout period programmed by the CTL1.RXTIMEOUT field, regardless of if the RX FIFO level configured in the IFLS register has been reached.
  • 0h = Interrupt did not occur or mask was not enabled.
  • 1h = Interrupt Occurred
8-3RESERVEDR0h
2RXR0hSPI Receive DMA Trigger Masked Status. The DMA is triggered when the RX FIFO condition programmed by the IFLS register is met. When FIFO is not present, this indicates that the buffer is full.
  • 0h = Interrupt did not occur or mask was not enabled
  • 1h = Interrupt occurred
1-0RESERVEDR0h

27.3.12 ISET (Offset = 1070h) [Reset = 00000000h]

ISET is shown in Figure 27-19 and described in Table 27-20.

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Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 27-19 ISET
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRTOUTRESERVED
R-0hW-0hR-0h
76543210
RESERVEDRXRESERVED
R-0hW-0hR-0h
Table 27-20 ISET Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR0h
9RTOUTW0hSet SPI Receive Timeout DMA Trigger. The DMA is triggered when the UNICOMM-SPI is in peripheral mode receiving data, the SCLK line is inactive while the RX FIFO contains at least one element for the timeout period programmed by the CTL1.RXTIMEOUT field, regardless of if the RX FIFO level configured in the IFLS register has been reached.
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt Mask
8-3RESERVEDR0h
2RXW0hSet SPI Receive DMA Trigger. The DMA is triggered when the RX FIFO condition programmed by the IFLS register is met. When FIFO is not present, this indicates that the buffer is full.
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
1-0RESERVEDR0h

27.3.13 IMASK (Offset = 1088h) [Reset = 00000000h]

IMASK is shown in Figure 27-20 and described in Table 27-21.

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Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Figure 27-20 IMASK
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDTXRESERVED
R-0hR/W-0hR-0h
Table 27-21 IMASK Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0h
5TXR/W0hSPI Transmit DMA Trigger Mask. The DMA is triggered when the TX FIFO condition programmed by the IFLS register is met. When FIFO is not present, this indicates that the buffer is empty.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrupt Mask
4-0RESERVEDR0h

27.3.14 RIS (Offset = 1090h) [Reset = 00000000h]

RIS is shown in Figure 27-21 and described in Table 27-22.

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Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 27-21 RIS
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDTXRESERVED
R-0hR-0hR-0h
Table 27-22 RIS Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0h
5TXR0hSPI Transmit DMA Trigger Raw Status. The DMA is triggered when the TX FIFO condition programmed by the IFLS register is met. When FIFO is not present, this indicates that the buffer is empty.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
4-0RESERVEDR0h

27.3.15 MIS (Offset = 1098h) [Reset = 00000000h]

MIS is shown in Figure 27-22 and described in Table 27-23.

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Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 27-22 MIS
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDTXRESERVED
R-0hR-0hR-0h
Table 27-23 MIS Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0h
5TXR0hSPI Transmit DMA Trigger Masked Status. The DMA is triggered when the TX FIFO condition programmed by the IFLS register is met. When FIFO is not present, this indicates that the buffer is empty.
  • 0h = Interrupt did not occur or mask was not enabled.
  • 1h = Interrupt occurred
4-0RESERVEDR0h

27.3.16 ISET (Offset = 10A0h) [Reset = 00000000h]

ISET is shown in Figure 27-23 and described in Table 27-24.

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Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 27-23 ISET
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDTXRESERVED
R-0hW-0hR-0h
Table 27-24 ISET Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0h
5TXW0hSet SPI Transmit DMA Trigger. The DMA is triggered when the TX FIFO condition programmed by the IFLS register is met. When FIFO is not present, this indicates that the buffer is empty.
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
4-0RESERVEDR0h

27.3.17 INTCTL (Offset = 10E4h) [Reset = 00000000h]

INTCTL is shown in Figure 27-24 and described in Table 27-25.

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Interrupt Control Register.

Figure 27-24 INTCTL
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDINTEVAL
R-0hW-0h
Table 27-25 INTCTL Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h
0INTEVALW0hWriting a 1 to this field re-evaluates the interrupt sources.
  • 0h = Writing 0 has no effect
  • 1h = Interrupt Eval

27.3.18 CTL0 (Offset = 1100h) [Reset = 00000000h]

CTL0 is shown in Figure 27-25 and described in Table 27-26.

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SPI Control Register 0.

Figure 27-25 CTL0
3130292827262524
RESERVEDCS_MASK_ROTATE_ENCS3_ROTATE_MASKCS2_ROTATE_MASKCS1_ROTATE_MASKCS0_ROTATE_MASK
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDCSCLRCSSELRESERVEDSPHSPO
R-0hR/W-0hR/W-0hR-0hR/W-0hR/W-0h
76543210
PACKENFRFDSS
R/W-0hR/W-0hR/W-0h
Table 27-26 CTL0 Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDR0h
28CS_MASK_ROTATE_ENR/W0hChip select rotate mask enable
  • 0h = No additional delay
  • 1h = Enable
27CS3_ROTATE_MASKR/W0hChip select rotate mask
  • 0h = Disable
  • 1h = Enable
26CS2_ROTATE_MASKR/W0hChip select rotate mask
  • 0h = Disable
  • 1h = Enable
25CS1_ROTATE_MASKR/W0hChip select rotate mask
  • 0h = Disable
  • 1h = Enable
24CS0_ROTATE_MASKR/W0hChip select rotate mask
  • 0h = Disable
  • 1h = Enable
23-15RESERVEDR0h
14CSCLRR/W0hClear shift register counter on CS inactive This bit is relevant only in the peripheral, CTL1.CP=0.
  • 0h = Disable automatic clear of shift register when CS goes to disable.
  • 1h = Enable automatic clear of shift register when CS goes to disable.
13-12CSSELR/W0hSelect the CS line to control on data transfer This bit is applicable for both controller/target mode
  • 0h (R/W) = CS line select: 0
  • 1h (R/W) = CS line select: 1
  • 2h (R/W) = CS line select: 2
  • 3h (R/W) = CS line select: 3
11-10RESERVEDR0h
9SPHR/W0hCLKOUT phase (Motorola SPI frame format only) This bit selects the clock edge that captures data and enables it to change state. It has the most impact on the first bit transmitted by either permitting or not permitting a clock transition before the first data capture edge.
  • 0h = Data is captured on the first clock edge transition.
  • 1h = Data is captured on the second clock edge transition.
8SPOR/W0hCLKOUT polarity (Motorola SPI frame format only)
  • 0h = SPI produces a steady state LOW value on the CLKOUT
  • 1h = SPI produces a steady state HIGH value on the CLKOUT
7PACKENR/W0hPacking Enable. When 1, packing feature is enabled inside the IP When 0, packing feature is disabled inside the IP
  • 0h = Packing feature disabled
  • 1h = Packing feature enabled
6-5FRFR/W0hFrame format Select
  • 0h = Motorola SPI frame format (3 wire mode)
  • 1h = Motorola SPI frame format (4 wire mode)
  • 2h = TI synchronous serial frame format
  • 3h = Reserved - not to be selected
4-0DSSR/W0hData Size Select. Values 0 - 2 are reserved and shall not be used. 3h = 4_BIT : 4-bit data SPI allows only values up to 16 Bit
  • 3h (R/W) = Data Size Select bits: 4
  • 4h (R/W) = Data Size Select bits: 5
  • 5h (R/W) = Data Size Select bits: 6
  • 6h (R/W) = Data Size Select bits: 7
  • 7h (R/W) = Data Size Select bits: 8
  • 8h (R/W) = Data Size Select bits: 9
  • 9h (R/W) = Data Size Select bits: 10
  • Ah (R/W) = Data Size Select bits: 11
  • Bh (R/W) = Data Size Select bits: 12
  • Ch (R/W) = Data Size Select bits: 13
  • Dh (R/W) = Data Size Select bits: 14
  • Eh (R/W) = Data Size Select bits: 15
  • Fh (R/W) = Data Size Select bits: 16

27.3.19 STAT (Offset = 1108h) [Reset = 00000000h]

STAT is shown in Figure 27-26 and described in Table 27-27.

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SPI Status Register.

Figure 27-26 STAT
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
CDMODERESERVEDBUSY
R-0hR-0hR-0h
76543210
TXCLRTXFFTXFERXCLRRXFFRXFERESERVED
R-0hR-0hR-0hR-0hR-0hR-0hR-0h
Table 27-27 STAT Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0h
15-12CDMODER0hCurrent CDMODE Status. This reflects the current counter value.
  • 0h = Smallest value
  • 0h = Manual mode: Data
  • Fh = Manual mode: Command
11-9RESERVEDR0h
8BUSYR0hSPI Busy Status.
  • 0h = SPI is in idle mode.
  • 1h = SPI is currently transmitting and/or receiving data
7TXCLRR0hSPI TX FIFO Clear Status.
  • 0h = TX FIFO is not cleared
  • 1h = TX FIFO clear is complete
6TXFFR0hSPI TX FIFO Full Status.
  • 0h = TX FIFO is not full
  • 1h = TX FIFO is full
5TXFER1hTX FIFO Empty Status.
  • 0h = TX FIFO is not empty
  • 1h = TX FIFO is empty
4RXCLRR0hSPI RX FIFO Clear Status.
  • 0h = FIFO is not cleared
  • 1h = FIFO clear is complete
3RXFFR0hSPI RX FIFO Full Status.
  • 0h = RX FIFO is not full
  • 1h = RX FIFO is full
2RXFER1hRX FIFO Empty Status.
  • 0h = RX FIFO is not empty
  • 1h = RX FIFO is empty
1-0RESERVEDR0h

27.3.20 IFLS (Offset = 110Ch) [Reset = 00000022h]

IFLS is shown in Figure 27-27 and described in Table 27-28.

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Interrupt FIFO Level Select. The IFLS register is the interrupt FIFO level select register. You can use this register to define the levels at which the TX, RX and timeout interrupt flags are triggered. The interrupts are generated based on a transition through a level rather than being based on the level. That is, the interrupts are generated when the fill level progresses through the trigger level. For example, if the receive trigger level is set to the half-way mark, the interrupt is triggered when the RX FIFO is filled with two or more characters. Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt at the half-way mark.

Figure 27-27 IFLS
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RXCLRRXIFLSELTXCLRTXIFLSEL
R/W-0hR/W-2hR/W-0hR/W-2h
Table 27-28 IFLS Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7RXCLRR/W0hRX FIFO Clear. Setting this bit will clear the RX FIFO contents.
  • 0h = Disable FIFO clear
  • 1h = Enable FIFO Clear
6-4RXIFLSELR/W2hRX FIFO Level Select for generating events (interrupt/DMA). Note: for undefined settings the default configuration is used.
  • 1h = RX FIFO >= 1/4 full
  • 2h = RX FIFO >= 1/2 full (default)
  • 3h = RX FIFO >= 3/4 full
  • 4h = Opposite of empty
  • 5h = RX FIFO is full
  • 6h = RX_FIFO >= (MAX_FIFO_LEN -1)
  • 7h = RX_FIFO <= 1
3TXCLRR/W0hTX FIFO Clear. Setting this bit will clear the TX FIFO contents.
  • 0h = Disable FIFO clear
  • 1h = Enable FIFO Clear
2-0TXIFLSELR/W2hTX FIFO Level Select for generating events (interrupt/DMA). Note: for undefined settings the default configuration is used.
  • 1h = TX FIFO <= 3/4 empty
  • 2h = TX FIFO <= 1/2 empty (default)
  • 3h = TX FIFO <= 1/4 empty
  • 4h = Opposite of full
  • 5h = TX FIFO is empty
  • 6h = TX FIFO <= 1
  • 7h = TX_FIFO >= (MAX_FIFO_LEN -1)

27.3.21 CLKCTL (Offset = 1110h) [Reset = 00000000h]

CLKCTL is shown in Figure 27-28 and described in Table 27-29.

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Clock prescaler and divider register. This register contains the settings for the Clock prescaler and divider settings.

Figure 27-28 CLKCTL
31302928272625242322212019181716
DSAMPLERESERVED
R/W-0hR-0h
1514131211109876543210
RESERVEDSCR
R-0hR/W-0h
Table 27-29 CLKCTL Field Descriptions
BitFieldTypeResetDescription
31-28DSAMPLER/W0hDelayed Sampling Value. In controller mode, data on input pin will be delayed sampled by the defined clock cycles of internal functional clock (SPIclk) hence relaxing the setup time of input data. This setting is useful in systems where the board delays and external peripheral delays are more than the input setup time of the controller. Please refer to the datasheet for values of controller input setup time and assess what DSAMPLE value meets the requirement of the system. Note: High values of DSAMPLE can cause HOLD time violations and must be factored in the calculations.
  • 0h = Delayed sampling is not used
  • Fh = Highest possible value
27-10RESERVEDR0h
9-0SCRR/W0hSerial Clock Divider. This is used to generate the transmit and receive bit rate of the SPI. The SPI bit rate is (SPIclk)/((SCR+1)*2). SCR is a value from 0-1023.
  • 0h = Smallest value
  • 3FFh = Highest possible value

27.3.22 TXDATA (Offset = 1120h) [Reset = 00000000h]

TXDATA is shown in Figure 27-29 and described in Table 27-30.

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TXDATA Register. Writing puts the data into the TX FIFO. Reading this register returns the last written value. When PACKEN=0, only the lower 16-bits of data written into the register is transferred to one 16-bits wide TX FIFO entry When PACKEN=1, upper and lower 16-bits of 32-bit write data are transferred to two16-bits wide TX FIFO entry

Figure 27-29 TXDATA
313029282726252423222120191817161514131211109876543210
DATA
W-0h
Table 27-30 TXDATA Field Descriptions
BitFieldTypeResetDescription
31-0DATAW0hTransmit Data When read, last written value will be returned. If the last write to this field was a 32-bit write (with PACKEN=1), 32-bits will be returned and if the last write was a 16-bit write (PACKEN=0), those 16-bits will be returned. When written, one or two FIFO entries will be written depending on PACKEN value. Data values are removed from the TX FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the TXD output pin at the programmed bit rate. When a data size of less than 16 bits is selected, the user must right-justify data written to the TX FIFO. The transmit logic ignores the unused bits.
  • 0h = Smallest value
  • FFFFh = Highest possible value

27.3.23 RXDATA (Offset = 1124h) [Reset = 00000000h]

RXDATA is shown in Figure 27-30 and described in Table 27-31.

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RXDATA Register. Reading this register returns value(s) from the RX FIFO. If the FIFO is empty the last read value is returned. Writing has not effect and is ignored. When PACKEN=1,two entries of the FIFO are returned as a 32-bit value. When PACKEN=0, 1 entry of FIFO is returned as 16-bit value.

Figure 27-30 RXDATA
313029282726252423222120191817161514131211109876543210
DATA
R-0h
Table 27-31 RXDATA Field Descriptions
BitFieldTypeResetDescription
31-0DATAR0hReceived Data. When PACKEN=1,two entries of the FIFO are returned as a 32-bit value. When PACKEN=0, 1 entry of FIFO is returned as 16-bit value. As data values are removed by the receive logic from the incoming data frame, they are placed into the entry in the RX FIFO, pointed to by the current FIFO write pointer. Received data less than 16 bits is automatically right justified in the receive buffer.
  • 0h = Smallest value
  • FFFFh = Highest possible value

27.3.24 CTL1 (Offset = 114Ch) [Reset = 00000004h]

CTL1 is shown in Figure 27-31 and described in Table 27-32.

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SPI Control Register 1.

Figure 27-31 CTL1
3130292827262524
RESERVEDRXTIMEOUT
R-0hR/W-0h
2322212019181716
REPEATTX
R/W-0h
15141312111098
CDMODECDENABLERESERVEDSUSPENDPTEN
R/W-0hR/W-0hR-0hR/W-0hR/W-0h
76543210
RESERVEDPESPRENMSBPODCPLBMENABLE
R-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-1hR/W-0hR/W-0h
Table 27-32 CTL1 Field Descriptions
BitFieldTypeResetDescription
31-30RESERVEDR0h
29-24RXTIMEOUTR/W0hSPI Receive Interrupt Timeout Select (peripheral mode only). Configures the number of bits (at the programmed baud rate), used by the SPI peripheral when there is no SCLK pulse received, to flag/trigger a timeout condition (RTOUT or LTOUT). A value of 0 disables the timeout functions.
  • 0h = Smallest value
  • 3Fh = Highest possible value
23-16REPEATTXR/W0hCounter to repeat last transfer. 0: repeat last transfer is disabled. x: repeat the last transfer with the given number. The transfer will be started with writing a data into the TX Buffer. Sending the data will be repeated with the given value, so the data will be transferred X+1 times in total. The behavior is identical as if the data would be written into the TX Buffer that many times as defined by the value here. It can be used to clean a transfer or to pull a certain amount of data by a peripheral.
  • 0h = Smallest value
  • FFh = Highest possible value
15-12CDMODER/W0hCommand/Data Mode Value. When CTL1.CDENABLE is 1, CS3 line is used as C/D signal to distinguish between Command (C/D low) and Data (C/D high) information. When a value is written into the CTL1.CDMODE bits, the C/D (CS3) line will go low for the given numbers of byte which are sent by the SPI, starting with the next value to be transmitted after which, C/D line will go high automatically 0: Manual mode with C/D signal as High 1-14: C/D is low while this number of bytes are being sent after which, this field sets to 0 and C/D goes high. Reading this field at any time returns the remaining number of command bytes. 15: Manual mode with C/D signal as Low.
  • 0h = Manual mode: Data
  • 0h = Smallest value
  • Fh = Manual mode: Command
11CDENABLER/W0hCommand/Data Mode Enable.
  • 0h = CS3 is used for Chip Select
  • 1h = CS3 is used as CD signal
10RESERVEDR0h
9SUSPENDR/W0hSuspend External Communication. When this bit is set, SPI communication on the external bus is suspended after the CS has returned to the idle state in controller mode, and after the CS is read as an idle state in peripheral mode.
  • 0h = Functional mode resumed
  • 1h = External communication suspended
8PTENR/W0hParity Transmit Enable. If enabled, parity transmission will be done for both controller and peripheral modes.
  • 0h = Parity transmission is disabled
  • 1h = Parity transmission is enabled
7RESERVEDR0h
6PESR/W0hEven Parity Select.
  • 0h = Odd Parity mode
  • 1h = Even Parity mode
5PRENR/W0hParity Receive Enable. If enabled, parity reception check will be done for both controller and peripheral modes In case of a parity miss-match the parity error flag RIS.PER will be set.
  • 0h = Disable Parity receive function
  • 1h = Enable Parity receive function
4MSBR/W0hMSB First Select. Controls the direction of the receive and transmit shift register.
  • 0h = LSB first
  • 1h = MSB first
3PODR/W0hPeripheral-mode: Data output disabled. This bit is relevant only in Peripheral mode. In multiple-peripheral system topologies, SPI controller can broadcast a message to all peripherals, while only one peripheral drives the line. POD can be used by the SPI peripheral to disable driving data on the line.
  • 0h = SPI can drive the POCI output in peripheral mode.
  • 1h = SPI cannot drive the POCI output in peripheral mode.
2CPR/W1hController or Peripheral Mode Select. This bit can be modified only when SPI is disabled, CTL1.ENABLE=0.
  • 0h = Select Peripheral mode
  • 1h = Select Controller Mode
1LBMR/W0hLoopback Mode Enable.
  • 0h = Disable loopback mode
  • 1h = Enable loopback mode
0ENABLER/W0hSPI Enable.
  • 0h = Disable module function
  • 1h = Enable module function