SLAU847F October   2022  â€“ March 2026 MSPM0L1105 , MSPM0L1106 , MSPM0L1116 , MSPM0L1117 , MSPM0L1227 , MSPM0L1227-Q1 , MSPM0L1228 , MSPM0L1228-Q1 , MSPM0L1303 , MSPM0L1304 , MSPM0L1304-Q1 , MSPM0L1305 , MSPM0L1305-Q1 , MSPM0L1306 , MSPM0L1306-Q1 , MSPM0L1343 , MSPM0L1344 , MSPM0L1345 , MSPM0L1346 , MSPM0L2116 , MSPM0L2117 , MSPM0L2227 , MSPM0L2227-Q1 , MSPM0L2228 , MSPM0L2228-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation
    5.     Support Resources
    6.     Trademarks
  3. 1 Architecture
    1. 1.1 Architecture Overview
    2. 1.2 Bus Organization
    3. 1.3 Platform Memory Map
      1. 1.3.1 Code Region
      2. 1.3.2 SRAM Region
      3. 1.3.3 Peripheral Region
      4. 1.3.4 Subsystem Region
      5. 1.3.5 System PPB Region
    4. 1.4 Boot Configuration
      1. 1.4.1 Configuration Memory (NONMAIN)
        1. 1.4.1.1 CRC-Backed Configuration Data
        2. 1.4.1.2 16-bit Pattern Match for Critical Fields
      2. 1.4.2 Boot Configuration Routine (BCR)
        1. 1.4.2.1 Serial Wire Debug Related Policies
          1. 1.4.2.1.1 SWD Security Level 0
          2. 1.4.2.1.2 SWD Security Level 1
          3. 1.4.2.1.3 SWD Security Level 2
        2. 1.4.2.2 SWD Mass Erase and Factory Reset Commands
        3. 1.4.2.3 Flash Memory Protection and Integrity Related Policies
          1. 1.4.2.3.1 Locking the Application (MAIN) Flash Memory
          2. 1.4.2.3.2 Locking the Configuration (NONMAIN) Flash Memory
          3. 1.4.2.3.3 Static Write Protection NONMAIN Fields
        4. 1.4.2.4 Application CRC Verification
        5. 1.4.2.5 Fast Boot
        6. 1.4.2.6 Bootstrap Loader (BSL) Enable/Disable Policy
          1. 1.4.2.6.1 BSL Enable
      3. 1.4.3 Bootstrap Loader (BSL)
        1. 1.4.3.1 GPIO Invoke
        2. 1.4.3.2 Bootstrap Loader (BSL) Security Policies
          1. 1.4.3.2.1 BSL Access Password
          2. 1.4.3.2.2 BSL Read-out Policy
          3. 1.4.3.2.3 BSL Security Alert Policy
        3. 1.4.3.3 Application Version
        4. 1.4.3.4 BSL Triggered Mass Erase and Factory Reset
      4. 1.4.4 NONMAIN Layout Types
      5. 1.4.5 NONMAIN_TYPEA Registers
      6. 1.4.6 NONMAIN_TYPEC Registers
      7. 1.4.7 NONMAIN_TYPEE Registers
    5. 1.5 Factory Constants
      1. 1.5.1 FACTORYREGION Layout Types
      2. 1.5.2 FACTORYREGION_TYPEA Registers
      3. 1.5.3 FACTORYREGION_TYPEC Registers
      4. 1.5.4 FACTORYREGION_TYPED Registers
      5. 1.5.5 FACTORYREGION_TYPEE Registers
  4. 2 PMCU
    1. 2.1 PMCU Overview
      1. 2.1.1 Power Domains
      2. 2.1.2 Operating Modes
        1. 2.1.2.1 RUN Mode
        2. 2.1.2.2 SLEEP Mode
        3. 2.1.2.3 STOP Mode
        4. 2.1.2.4 STANDBY Mode
        5. 2.1.2.5 SHUTDOWN Mode
        6. 2.1.2.6 Supported Functionality by Operating Mode
        7. 2.1.2.7 Suspended Low-Power Mode Operation
    2. 2.2 Power Management (PMU)
      1. 2.2.1 Power Supply
      2. 2.2.2 Core Regulator
      3. 2.2.3 Supply Supervisors
        1. 2.2.3.1 Power-on Reset (POR)
        2. 2.2.3.2 Brownout Reset (BOR)
        3. 2.2.3.3 POR and BOR Behavior During Supply Changes
      4. 2.2.4 Bandgap Reference
      5. 2.2.5 VBOOST for Analog Muxes
      6. 2.2.6 Peripheral Enable
        1. 2.2.6.1 Automatic Peripheral Disable in Low Power Modes
    3. 2.3 Clock Module (CKM)
      1. 2.3.1 Oscillators
        1. 2.3.1.1 Internal Low-Frequency Oscillator (LFOSC)
        2. 2.3.1.2 Internal System Oscillator (SYSOSC)
          1. 2.3.1.2.1 SYSOSC Gear Shift
          2. 2.3.1.2.2 SYSOSC Frequency
          3. 2.3.1.2.3 SYSOSC Frequency Correction Loop
            1. 2.3.1.2.3.1 SYSOSC FCL in External Resistor Mode (ROSC)
            2. 2.3.1.2.3.2 SYSOSC FCL in Internal Resistor Mode
          4. 2.3.1.2.4 SYSOSC User Trim Procedure
          5. 2.3.1.2.5 Disabling SYSOSC
        3. 2.3.1.3 Low Frequency Crystal Oscillator (LFXT)
        4. 2.3.1.4 LFCLK_IN (Digital Clock)
        5. 2.3.1.5 High Frequency Crystal Oscillator (HFXT)
        6. 2.3.1.6 HFCLK_IN (Digital clock)
      2. 2.3.2 Clocks
        1. 2.3.2.1  MCLK (Main Clock) Tree
        2. 2.3.2.2  CPUCLK (Processor Clock)
        3. 2.3.2.3  ULPCLK (Low-Power Clock)
        4. 2.3.2.4  MFCLK (Middle Frequency Clock)
        5. 2.3.2.5  MFPCLK (Middle Frequency Precision Clock)
        6. 2.3.2.6  LFCLK (Low-Frequency Clock)
        7. 2.3.2.7  HFCLK (High-Frequency External Clock)
        8. 2.3.2.8  HSCLK (High Speed Clock)
        9. 2.3.2.9  ADCCLK (ADC Sample Period Clock)
        10. 2.3.2.10 CANCLK (CAN-FD Functional Clock)
        11. 2.3.2.11 RTCCLK (RTC Clock)
        12. 2.3.2.12 External Clock Output (CLK_OUT)
        13. 2.3.2.13 Direct Clock Connections for Infrastructure
      3. 2.3.3 Clock Tree
        1. 2.3.3.1 Peripheral Clock Source Selection
      4. 2.3.4 Clock Monitors
        1. 2.3.4.1 LFCLK Monitor
        2. 2.3.4.2 MCLK Monitor
        3. 2.3.4.3 Startup Monitors
          1. 2.3.4.3.1 LFOSC Startup Monitor
          2. 2.3.4.3.2 LFXT Startup Monitor
          3. 2.3.4.3.3 HFCLK Startup Monitor
          4. 2.3.4.3.4 HSCLK Status
      5. 2.3.5 Frequency Clock Counter (FCC)
        1. 2.3.5.1 Using the FCC
        2. 2.3.5.2 FCC Frequency Computation and Accuracy
    4. 2.4 System Controller (SYSCTL)
      1. 2.4.1  Resets and Device Initialization
        1. 2.4.1.1 Reset Levels
          1. 2.4.1.1.1 Power-on Reset (POR) Reset Level
          2. 2.4.1.1.2 Brownout Reset (BOR) Reset Level
          3. 2.4.1.1.3 Boot Reset (BOOTRST) Reset Level
          4. 2.4.1.1.4 System Reset (SYSRST) Reset Level
          5. 2.4.1.1.5 CPU-only Reset (CPURST) Reset Level
        2. 2.4.1.2 Initial Conditions After Power-Up
        3. 2.4.1.3 NRST Pin
        4. 2.4.1.4 SWD Pins
        5. 2.4.1.5 Generating Resets in Software
        6. 2.4.1.6 Reset Cause
        7. 2.4.1.7 Peripheral Reset Control
        8. 2.4.1.8 Boot Fail Handling
      2. 2.4.2  Operating Mode Selection
      3. 2.4.3  Asynchronous Fast Clock Requests
      4. 2.4.4  SRAM Write Protection
      5. 2.4.5  Flash Wait States
      6. 2.4.6  Flash Bank Address Swap
      7. 2.4.7  Shutdown Mode Handling (if present)
      8. 2.4.8  Configuration Lockout
      9. 2.4.9  System Status
      10. 2.4.10 Error Handling
      11. 2.4.11 SYSCTL Events
        1. 2.4.11.1 CPU Interrupt Event (CPU_INT)
        2. 2.4.11.2 Nonmaskable Interrupt Event (NMI)
    5. 2.5 SYSCTL Layout Types
    6. 2.6 SYSCTL_TYPEA Registers
    7. 2.7 SYSCTL_TYPEB Registers
    8. 2.8 SYSCTL_TYPEC Registers
    9. 2.9 Quick Start Reference
      1. 2.9.1 Default Device Configuration
      2. 2.9.2 Leveraging MFCLK
      3. 2.9.3 Optimizing Power Consumption in STOP Mode
      4. 2.9.4 Optimizing Power Consumption in STANDBY Mode
      5. 2.9.5 Increasing MCLK Precision
      6. 2.9.6 High Speed Clock (SYSPLL, HFCLK) Handling in Low-Power Modes
      7. 2.9.7 Optimizing for Lowest Wakeup Latency
      8. 2.9.8 Optimizing for Lowest Peak Current in RUN/SLEEP Mode
  5. 3 CPU
    1. 3.1 Overview
    2. 3.2 Arm Cortex-M0+ CPU
      1. 3.2.1 CPU Register File
      2. 3.2.2 Stack Behavior
      3. 3.2.3 Execution Modes and Privilege Levels
      4. 3.2.4 Address Space and Supported Data Sizes
    3. 3.3 Interrupts and Exceptions
      1. 3.3.1 Peripheral Interrupts (IRQs)
        1. 3.3.1.1 Nested Vectored Interrupt Controller (NVIC)
        2. 3.3.1.2 Interrupt Groups
        3. 3.3.1.3 Wake Up Controller (WUC)
      2. 3.3.2 Interrupt and Exception Table
      3. 3.3.3 Processor Lockup Scenario
    4. 3.4 CPU Peripherals
      1. 3.4.1 System Control Block (SCB)
      2. 3.4.2 System Tick Timer (SysTick)
    5. 3.5 Read-Only Memory (ROM)
    6. 3.6 CPUSS Registers
    7. 3.7 WUC Registers
  6. 4 SECURITY
    1. 4.1 Overview
      1. 4.1.1 Secure Boot
      2. 4.1.2 Customer Secure Code (CSC)
    2. 4.2 Boot and Startup Sequence
      1. 4.2.1 CSC Programming Overview
    3. 4.3 Secure Key Storage
    4. 4.4 Flash Memory Protection
      1. 4.4.1 Bank Swapping
      2. 4.4.2 Write Protection
      3. 4.4.3 Read-Execute Protection
      4. 4.4.4 IP Protection
      5. 4.4.5 Data Bank Protection
      6. 4.4.6 Hardware Monotonic Counter
    5. 4.5 SRAM Protection
    6. 4.6 SECURITY Registers
  7. 5 Direct Memory Access (DMA)
    1. 5.1 DMA Overview
    2. 5.2 DMA Operation
      1. 5.2.1  Addressing Modes
      2. 5.2.2  Channel Types
      3. 5.2.3  Transfer Modes
        1. 5.2.3.1 Single Transfer
        2. 5.2.3.2 Block Transfer
        3. 5.2.3.3 Repeated Single Transfer
        4. 5.2.3.4 Repeated Block Transfer
        5. 5.2.3.5 Stride Mode
      4. 5.2.4  Extended Modes
        1. 5.2.4.1 Fill Mode
        2. 5.2.4.2 Table Mode
      5. 5.2.5  Initiating DMA Transfers
      6. 5.2.6  Stopping DMA Transfers
      7. 5.2.7  Channel Priorities
      8. 5.2.8  Burst Block Mode
      9. 5.2.9  Using DMA with System Interrupts
      10. 5.2.10 DMA Controller Interrupts
      11. 5.2.11 DMA Trigger Event Status
      12. 5.2.12 DMA Operating Mode Support
        1. 5.2.12.1 Transfer in RUN Mode
        2. 5.2.12.2 Transfer in SLEEP Mode
        3. 5.2.12.3 Transfer in STOP Mode
        4. 5.2.12.4 Transfers in STANDBY Mode
      13. 5.2.13 DMA Address and Data Errors
      14. 5.2.14 Interrupt and Event Support
    3. 5.3 DMA Registers
  8. 6 NVM (Flash)
    1. 6.1 NVM Overview
      1. 6.1.1 Key Features
      2. 6.1.2 System Components
      3. 6.1.3 Terminology
    2. 6.2 Flash Memory Bank Organization
      1. 6.2.1 Banks
      2. 6.2.2 Flash Memory Regions
      3. 6.2.3 Addressing
        1. 6.2.3.1 Flash Memory Map
      4. 6.2.4 Memory Organization Examples
    3. 6.3 Flash Controller
      1. 6.3.1 Overview of Flash Controller Commands
      2. 6.3.2 NOOP Command
      3. 6.3.3 PROGRAM Command
        1. 6.3.3.1 Program Bit Masking Behavior
        2. 6.3.3.2 Programming Less Than One Flash Word
        3. 6.3.3.3 Target Data Alignment (Devices with Single Flash Word Programming Only)
        4. 6.3.3.4 Target Data Alignment (Devices With Multiword Programming)
        5. 6.3.3.5 Executing a PROGRAM Operation
      4. 6.3.4 ERASE Command
        1. 6.3.4.1 Erase Sector Masking Behavior
        2. 6.3.4.2 Executing an ERASE Operation
      5. 6.3.5 READVERIFY Command
        1. 6.3.5.1 Executing a READVERIFY Operation
      6. 6.3.6 BLANKVERIFY Command
        1. 6.3.6.1 Executing a BLANKVERIFY Operation
      7. 6.3.7 Command Diagnostics
        1. 6.3.7.1 Command Status
        2. 6.3.7.2 Address Translation
        3. 6.3.7.3 Pulse Counts
      8. 6.3.8 Overriding the System Address With a Bank ID, Region ID, and Bank Address
      9. 6.3.9 FLASHCTL Events
        1. 6.3.9.1 CPU Interrupt Event Publisher
    4. 6.4 Write Protection
      1. 6.4.1 Write Protection Resolution
      2. 6.4.2 Static Write Protection
      3. 6.4.3 Dynamic Write Protection
        1. 6.4.3.1 Configuring Protection for the MAIN Region
        2. 6.4.3.2 Configuring Protection for the NONMAIN Region
    5. 6.5 Read Interface
      1. 6.5.1 Bank Address Swapping
    6. 6.6 FLASHCTL Registers
  9. 7 Events
    1. 7.1 Events Overview
      1. 7.1.1 Event Publisher
      2. 7.1.2 Event Subscriber
      3. 7.1.3 Event Fabric Routing
        1. 7.1.3.1 CPU Interrupt Event Route (CPU_INT)
        2. 7.1.3.2 DMA Trigger Event Route (DMA_TRIGx)
        3. 7.1.3.3 Generic Event Route (GEN_EVENTx)
      4. 7.1.4 Event Routing Map
      5. 7.1.5 Event Propagation Latency
    2. 7.2 Events Operation
      1. 7.2.1 CPU Interrupt
      2. 7.2.2 DMA Trigger
      3. 7.2.3 Peripheral to Peripheral Event
      4. 7.2.4 Extended Module Description Register
      5. 7.2.5 Using Event Registers
        1. 7.2.5.1 Event Registers
        2. 7.2.5.2 Configuring Events
        3. 7.2.5.3 Responding to CPU Interrupts in Application Software
        4. 7.2.5.4 Hardware Event Handling
  10. 8 IOMUX
    1. 8.1 IOMUX Overview
      1. 8.1.1 IO Types and Analog Sharing
    2. 8.2 IOMUX Operation
      1. 8.2.1 Peripheral Function (PF) Assignment
      2. 8.2.2 Logic High to Hi-Z Conversion
      3. 8.2.3 Logic Inversion
      4. 8.2.4 SHUTDOWN Mode Wakeup Logic
      5. 8.2.5 Pullup/Pulldown Resistors
      6. 8.2.6 Drive Strength Control
      7. 8.2.7 Hysteresis and Logic Level Control
    3. 8.3 IOMUX Registers
  11. 9 General-Purpose Input/Output (GPIO)
    1. 9.1 GPIO Overview
    2. 9.2 GPIO Operation
      1. 9.2.1 GPIO Ports
      2. 9.2.2 GPIO Read/Write Interface
      3. 9.2.3 GPIO Input Glitch Filtering and Synchronization
      4. 9.2.4 GPIO Fast Wake
      5. 9.2.5 GPIO DMA Interface
      6. 9.2.6 Event Publishers and Subscribers
    3. 9.3 GPIO Registers
  12. 10AES
    1. 10.1 AES Overview
      1. 10.1.1 AESADV Performance
    2. 10.2 AESADV Operation
      1. 10.2.1 Loading the Key
      2. 10.2.2 Writing Input Data
      3. 10.2.3 Reading Output Data
      4. 10.2.4 Operation Descriptions
        1. 10.2.4.1 Single Block Operation
        2. 10.2.4.2 Electronic Codebook (ECB) Mode
          1. 10.2.4.2.1 ECB Encryption
          2. 10.2.4.2.2 ECB Decryption
        3. 10.2.4.3 Cipher Block Chaining (CBC) Mode
          1. 10.2.4.3.1 CBC Encryption
          2. 10.2.4.3.2 CBC Decryption
        4. 10.2.4.4 Output Feedback (OFB) Mode
          1. 10.2.4.4.1 OFB Encryption
          2. 10.2.4.4.2 OFB Decryption
        5. 10.2.4.5 Cipher Feedback (CFB) Mode
          1. 10.2.4.5.1 CFB Encryption
          2. 10.2.4.5.2 CFB Decryption
        6. 10.2.4.6 Counter (CTR) Mode
          1. 10.2.4.6.1 CTR Encryption
          2. 10.2.4.6.2 CTR Decryption
        7. 10.2.4.7 Galois Counter (GCM) Mode
          1. 10.2.4.7.1 GHASH Operation
          2. 10.2.4.7.2 GCM Operating Modes
            1. 10.2.4.7.2.1 Autonomous GCM Operation
              1. 10.2.4.7.2.1.1 GMAC
            2. 10.2.4.7.2.2 GCM With Pre-Calculations
            3. 10.2.4.7.2.3 GCM Operation With Precalculated H- and Y0-Encrypted Forced to Zero
        8. 10.2.4.8 Counter With Cipher Block Chaining Message Authentication Code (CCM)
          1. 10.2.4.8.1 CCM Operation
      5. 10.2.5 AES Events
        1. 10.2.5.1 CPU Interrupt Event Publisher (CPU_EVENT)
        2. 10.2.5.2 DMA Trigger Event Publisher (DMA_TRIG_DATAIN)
        3. 10.2.5.3 DMA Trigger Event Publisher (DMA_TRIG_DATAOUT)
    3. 10.3 AESADV Registers
  13. 11CRC
    1. 11.1 CRC Overview
      1. 11.1.1 CRC16-CCITT
      2. 11.1.2 CRC32-ISO3309
    2. 11.2 CRC Operation
      1. 11.2.1 CRC Generator Implementation
      2. 11.2.2 Configuration
        1. 11.2.2.1 Polynomial Selection
        2. 11.2.2.2 Bit Order
        3. 11.2.2.3 Byte Swap
        4. 11.2.2.4 Byte Order
        5. 11.2.2.5 CRC C Library Compatibility
    3. 11.3 CRCP0 Registers
  14. 12Keystore
    1. 12.1 Overview
    2. 12.2 Detailed Description
    3. 12.3 KEYSTORECTL Registers
  15. 13TRNG
    1. 13.1 TRNG Overview
    2. 13.2 TRNG Operation
      1. 13.2.1 TRNG Generation Data Path
      2. 13.2.2 Clock Configuration and Output Rate
      3. 13.2.3 Behavior in Low Power Modes
      4. 13.2.4 Health Tests
        1. 13.2.4.1 Digital Block Startup Self-Test
        2. 13.2.4.2 Analog Block Startup Self-Test
        3. 13.2.4.3 Runtime Health Test
          1. 13.2.4.3.1 Repetition Count Test
          2. 13.2.4.3.2 Adaptive Proportion Test
          3. 13.2.4.3.3 Handling Runtime Health Test Failures
      5. 13.2.5 Configuration
        1. 13.2.5.1 TRNG State Machine
          1. 13.2.5.1.1 Changing TRNG States
        2. 13.2.5.2 Using the TRNG
        3. 13.2.5.3 TRNG Events
          1. 13.2.5.3.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 13.3 TRNG Registers
  16. 14Temperature Sensor
  17. 15ADC
    1. 15.1 ADC Overview
    2. 15.2 ADC Operation
      1. 15.2.1  ADC Core
      2. 15.2.2  Voltage Reference Options
      3. 15.2.3  Generic Resolution Modes
      4. 15.2.4  Hardware Averaging
      5. 15.2.5  ADC Clocking
      6. 15.2.6  Common ADC Use Cases
      7. 15.2.7  Power Down Behavior
      8. 15.2.8  Sampling Trigger Sources and Sampling Modes
        1. 15.2.8.1 AUTO Sampling Mode
        2. 15.2.8.2 MANUAL Sampling Mode
      9. 15.2.9  Sampling Period
      10. 15.2.10 Conversion Modes
      11. 15.2.11 Data Format
      12. 15.2.12 Advanced Features
        1. 15.2.12.1 Window Comparator
        2. 15.2.12.2 DMA and FIFO Operation
        3. 15.2.12.3 Analog Peripheral Interconnection
      13. 15.2.13 Status Register
      14. 15.2.14 ADC Events
        1. 15.2.14.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 15.2.14.2 Generic Event Publisher (GEN_EVENT)
        3. 15.2.14.3 DMA Trigger Event Publisher (DMA_TRIG)
        4. 15.2.14.4 Generic Event Subscriber (FSUB_0)
    3. 15.3 ADC12 Registers
  18. 16COMP
    1. 16.1 Comparator Overview
    2. 16.2 Comparator Operation
      1. 16.2.1  Comparator Configuration
      2. 16.2.2  Comparator Channels Selection
      3. 16.2.3  Comparator Output
      4. 16.2.4  Output Filter
      5. 16.2.5  Sampled Output Mode
      6. 16.2.6  Blanking Mode
      7. 16.2.7  Reference Voltage Generator
      8. 16.2.8  Comparator Hysteresis
      9. 16.2.9  Input SHORT Switch
      10. 16.2.10 Interrupt and Events Support
        1. 16.2.10.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 16.2.10.2 Generic Event Publisher (GEN_EVENT)
        3. 16.2.10.3 Generic Event Subscribers
    3. 16.3 COMP0 Registers
  19. 17OPA
    1. 17.1 OPA Overview
    2. 17.2 OPA Operation
      1. 17.2.1 Analog Core
      2. 17.2.2 Power Up Behavior
      3. 17.2.3 Inputs
      4. 17.2.4 Output
      5. 17.2.5 Clock Requirements
      6. 17.2.6 Chopping
      7. 17.2.7 OPA Amplifier Modes
        1. 17.2.7.1 General-Purpose Mode
        2. 17.2.7.2 Buffer Mode
        3. 17.2.7.3 OPA PGA Mode
          1. 17.2.7.3.1 Inverting PGA Mode
          2. 17.2.7.3.2 Non-inverting PGA Mode
        4. 17.2.7.4 Difference Amplifier Mode
        5. 17.2.7.5 Cascade Amplifier Mode
      8. 17.2.8 OPA Configuration Selection
      9. 17.2.9 Burnout Current Source
    3. 17.3 OA Registers
  20. 18GPAMP
    1. 18.1 GPAMP Overview
    2. 18.2 GPAMP Operation
      1. 18.2.1 Analog Core
      2. 18.2.2 Power Up Behavior
      3. 18.2.3 Inputs
      4. 18.2.4 Output
      5. 18.2.5 GPAMP Amplifier Modes
        1. 18.2.5.1 General-Purpose Mode
        2. 18.2.5.2 ADC Buffer Mode
        3. 18.2.5.3 Unity Gain Mode
      6. 18.2.6 Chopping
    3. 18.3 GPAMP Registers
  21. 19VREF
    1. 19.1 VREF Overview
    2. 19.2 VREF Operation
      1. 19.2.1 Internal Reference Generation
      2. 19.2.2 External Reference Input
      3. 19.2.3 Analog Peripheral Interface
    3. 19.3 VREF Registers
  22. 20LCD
    1. 20.1 LCD Introduction
      1. 20.1.1 LCD Operating Principle
      2. 20.1.2 Static Mode
      3. 20.1.3 2-Mux Mode
      4. 20.1.4 3-Mux Mode
      5. 20.1.5 4-Mux Mode
      6. 20.1.6 6-Mux Mode
      7. 20.1.7 8-Mux Mode
      8. 20.1.8 Introduction
      9. 20.1.9 LCD Waveforms
    2. 20.2 LCD Clocking
    3. 20.3 Voltage Generation
      1. 20.3.1  Mode 0 - Voltage Generation from external reference and external resistor divider
      2. 20.3.2  Mode 1 - Voltage Generation from AVDD and external resistor divider
      3. 20.3.3  Mode 2 - Voltage Generation from external reference and internal resistor divider
      4. 20.3.4  Mode 3 - Voltage Generation From AVDD and Internal Resistor Ladder
      5. 20.3.5  Mode 4 - Voltage Generation from charge pump with external supply
      6. 20.3.6  Mode 5 - Voltage Generation From Charge Pump With AVDD
      7. 20.3.7  Mode 6 - Voltage Generation From Charge Pump With External Reference on R13
      8. 20.3.8  Mode 7 - Voltage Generation From Charge Pump With Internal Reference on R13
      9. 20.3.9  Charge pump
      10. 20.3.10 Internal Reference Generation
    4. 20.4 Analog Mux
      1. 20.4.1 Static Mode
      2. 20.4.2 Non-Static 1/3 bias mode
      3. 20.4.3 Non-Static 1/4 bias mode
      4. 20.4.4 Low power mode switch controls
    5. 20.5 LCD Memory and output drive
      1. 20.5.1 LCD Memory organization
        1. 20.5.1.1 Memory Organization in Mux-1 to Mux-4 Modes
        2. 20.5.1.2 Memory Organization in Mux-5 to Mux-8 Modes
        3. 20.5.1.3 Configuring memory
        4. 20.5.1.4 Accessing memory and output drive
        5. 20.5.1.5 Blinking Override
    6. 20.6 IO Muxing
    7. 20.7 Interrupt Generation
    8. 20.8 Power Domains and Power Modes
    9. 20.9 LCD Registers
  23. 21UART
    1. 21.1 UART Overview
      1. 21.1.1 Purpose of the Peripheral
      2. 21.1.2 Features
      3. 21.1.3 Functional Block Diagram
    2. 21.2 UART Operation
      1. 21.2.1 Clock Control
      2. 21.2.2 Signal Descriptions
      3. 21.2.3 General Architecture and Protocol
        1. 21.2.3.1  Transmit Receive Logic
        2. 21.2.3.2  Bit Sampling
        3. 21.2.3.3  Majority Voting Feature
        4. 21.2.3.4  Baud Rate Generation
        5. 21.2.3.5  Data Transmission
        6. 21.2.3.6  Error and Status
        7. 21.2.3.7  Local Interconnect Network (LIN) Support
          1. 21.2.3.7.1 LIN Responder Transmission Delay
        8. 21.2.3.8  Flow Control
        9. 21.2.3.9  Idle-Line Multiprocessor
        10. 21.2.3.10 9-Bit UART Mode
        11. 21.2.3.11 RS-485 Support
        12. 21.2.3.12 DALI Protocol
        13. 21.2.3.13 Manchester Encoding and Decoding
        14. 21.2.3.14 IrDA Encoding and Decoding
        15. 21.2.3.15 ISO7816 Smart Card Support
        16. 21.2.3.16 Address Detection
        17. 21.2.3.17 FIFO Operation
        18. 21.2.3.18 Loopback Operation
        19. 21.2.3.19 Glitch Suppression
      4. 21.2.4 Low Power Operation
      5. 21.2.5 Reset Considerations
      6. 21.2.6 Initialization
      7. 21.2.7 Interrupt and Events Support
        1. 21.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 21.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 21.2.8 Emulation Modes
    3. 21.3 UART Registers
  24. 22I2C
    1. 22.1 I2C Overview
      1. 22.1.1 Purpose of the Peripheral
      2. 22.1.2 Features
      3. 22.1.3 Functional Block Diagram
      4. 22.1.4 Environment and External Connections
    2. 22.2 I2C Operation
      1. 22.2.1 Clock Control
        1. 22.2.1.1 Clock Select and I2C Speed
        2. 22.2.1.2 Clock Startup
      2. 22.2.2 Signal Descriptions
      3. 22.2.3 General Architecture
        1. 22.2.3.1  I2C Bus Functional Overview
        2. 22.2.3.2  START and STOP Conditions
        3. 22.2.3.3  Data Format with 7-Bit Address
        4. 22.2.3.4  Acknowledge
        5. 22.2.3.5  Repeated Start
        6. 22.2.3.6  SCL Clock Low Timeout
        7. 22.2.3.7  Clock Stretching
        8. 22.2.3.8  Dual Address
        9. 22.2.3.9  Arbitration
        10. 22.2.3.10 Multiple Controller Mode
        11. 22.2.3.11 Glitch Suppression
        12. 22.2.3.12 FIFO operation
          1. 22.2.3.12.1 Flushing Stale Tx Data in Target Mode
        13. 22.2.3.13 Loopback mode
        14. 22.2.3.14 Burst Mode
        15. 22.2.3.15 DMA Operation
        16. 22.2.3.16 Low-Power Operation
      4. 22.2.4 Protocol Descriptions
        1. 22.2.4.1 I2C Controller Mode
          1. 22.2.4.1.1 Controller Configuration
          2. 22.2.4.1.2 Controller Mode Operation
          3. 22.2.4.1.3 Read On TX Empty
        2. 22.2.4.2 I2C Target Mode
          1. 22.2.4.2.1 Target Mode Operation
      5. 22.2.5 Reset Considerations
      6. 22.2.6 Initialization
      7. 22.2.7 Interrupt and Events Support
        1. 22.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 22.2.7.2 DMA Trigger Publisher (DMA_TRIG1, DMA_TRIG0)
      8. 22.2.8 Emulation Modes
    3. 22.3 I2C Registers
  25. 23SPI
    1. 23.1 SPI Overview
      1. 23.1.1 Purpose of the Peripheral
      2. 23.1.2 Features
      3. 23.1.3 Functional Block Diagram
      4. 23.1.4 External Connections and Signal Descriptions
    2. 23.2 SPI Operation
      1. 23.2.1 Clock Control
      2. 23.2.2 General Architecture
        1. 23.2.2.1 Chip Select and Command Handling
          1. 23.2.2.1.1 Chip Select Control
          2. 23.2.2.1.2 Command Data Control
        2. 23.2.2.2 Data Format
        3. 23.2.2.3 Delayed data sampling
        4. 23.2.2.4 Clock Generation
        5. 23.2.2.5 FIFO Operation
        6. 23.2.2.6 Loopback mode
        7. 23.2.2.7 DMA Operation
        8. 23.2.2.8 Repeat Transfer mode
        9. 23.2.2.9 Low Power Mode
      3. 23.2.3 Protocol Descriptions
        1. 23.2.3.1 Motorola SPI Frame Format
        2. 23.2.3.2 Texas Instruments Synchronous Serial Frame Format
      4. 23.2.4 Reset Considerations
      5. 23.2.5 Initialization
      6. 23.2.6 Interrupt and Events Support
        1. 23.2.6.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 23.2.6.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      7. 23.2.7 Emulation Modes
    3. 23.3 SPI Registers
  26. 24UNICOMM
    1. 24.1 Overview
      1. 24.1.1 Block Diagram
    2. 24.2 Unicomm Architecture
      1. 24.2.1 Serial Peripheral Group (SPG) Configurations
        1. 24.2.1.1 I2C Pairings
      2. 24.2.2 Enables & Resets
    3. 24.3 High-Level Initialization
    4. 24.4 UNICOMM/SPGSS Registers
      1. 24.4.1 UNICOMM Registers
        1. 24.4.1.1 UNICOMM Registers
      2. 24.4.2 SPG Registers
        1. 24.4.2.1 SPGSS Registers
  27. 25UNICOMM UART
    1. 25.1 UART Overview
      1. 25.1.1 Purpose of the Peripheral
      2. 25.1.2 Features
      3. 25.1.3 Functional Block Diagram
    2. 25.2 UART Operation
      1. 25.2.1 Clock Control
      2. 25.2.2 General Architecture and Protocol
        1. 25.2.2.1 Signal Descriptions
        2. 25.2.2.2 Transmit and Receive Logic
        3. 25.2.2.3 Bit Sampling
        4. 25.2.2.4 Baud Rate Generation
        5. 25.2.2.5 Data Transmission
        6. 25.2.2.6 Error and Status
        7. 25.2.2.7 DMA Operation
        8. 25.2.2.8 Internal Loopback Operation
      3. 25.2.3 Additional Protocol and Feature Support
        1. 25.2.3.1  Local Interconnect Network (LIN) Support
          1. 25.2.3.1.1 LIN Commander Transmit
          2. 25.2.3.1.2 LIN Responder Receive
          3. 25.2.3.1.3 LIN Responder Transmission Delay
        2. 25.2.3.2  Flow Control
        3. 25.2.3.3  RS485 Support
        4. 25.2.3.4  FIFO Operation
        5. 25.2.3.5  Idle-Line Multiprocessor
        6. 25.2.3.6  9-Bit UART Mode
        7. 25.2.3.7  DALI Protocol
        8. 25.2.3.8  Manchester Encoding and Decoding
        9. 25.2.3.9  IrDA Encoding and Decoding
        10. 25.2.3.10 ISO7816 Smart Card Support
        11. 25.2.3.11 Address Detection
        12. 25.2.3.12 Glitch Suppression
      4. 25.2.4 Low Power Operation
      5. 25.2.5 Reset Considerations
      6. 25.2.6 UART Initialization
      7. 25.2.7 Interrupt and Events Support
        1. 25.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 25.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 25.2.8 Emulation Modes
    3. 25.3 UNICOMMUART Registers
  28. 26UNICOMM-I2C
    1. 26.1 UNICOMM-I2C Overview
      1. 26.1.1 Purpose of the Peripheral
      2. 26.1.2 Features
      3. 26.1.3 Functional Block Diagram
      4. 26.1.4 Environment and External Connections
    2. 26.2 UNICOMM Common Infrastructure
    3. 26.3 Peripheral Functional Description
      1. 26.3.1 Clock Control
        1. 26.3.1.1 Clock Select and I2C Speed
        2. 26.3.1.2 Clock Startup
      2. 26.3.2 Signal Descriptions
      3. 26.3.3 General Architecture
        1. 26.3.3.1  I2C Bus Functional Overview
        2. 26.3.3.2  START and STOP Conditions
        3. 26.3.3.3  Dual Address
        4. 26.3.3.4  Address Format
          1. 26.3.3.4.1 Data Format with 7-Bit Address
          2. 26.3.3.4.2 Data Format with 10-Bit Address
        5. 26.3.3.5  Acknowledge
        6. 26.3.3.6  Repeated Start
        7. 26.3.3.7  Clock Stretching
        8. 26.3.3.8  Clock Low Timeout
        9. 26.3.3.9  Burst Mode
        10. 26.3.3.10 Arbitration
        11. 26.3.3.11 Multiple Controller Mode
        12. 26.3.3.12 Glitch Suppression
        13. 26.3.3.13 DMA Operation
        14. 26.3.3.14 FIFO Operation
          1. 26.3.3.14.1 FIFO Status Flags
          2. 26.3.3.14.2 FIFO Levels
          3. 26.3.3.14.3 Clearing FIFO Contents
        15. 26.3.3.15 Suspend Communication
        16. 26.3.3.16 Low Power Operation
        17. 26.3.3.17 SMBUS 3.0 Support
          1. 26.3.3.17.1 Quick Command
          2. 26.3.3.17.2 SMBUS Enhanced Acknowledge Control
          3. 26.3.3.17.3 Clock Low Timeout Detection
          4. 26.3.3.17.4 Clock High Timeout Detection
          5. 26.3.3.17.5 Cumulative Clock Low Extended Timeout
          6. 26.3.3.17.6 Packet Error Checking (PEC)
          7. 26.3.3.17.7 Host Notify Protocol
          8. 26.3.3.17.8 Alert Response Protocol
          9. 26.3.3.17.9 Address Resolution Protocol
      4. 26.3.4 Protocol Descriptions & Initialization
        1. 26.3.4.1 I2C Controller Mode
          1. 26.3.4.1.1 I2C Controller Initialization
          2. 26.3.4.1.2 I2C Controller Status
          3. 26.3.4.1.3 I2C Controller Receive Mode
          4. 26.3.4.1.4 I2C Controller Transmitter Mode
          5. 26.3.4.1.5 Controller Transaction Configurations
        2. 26.3.4.2 I2C Target Mode
          1. 26.3.4.2.1 I2C Target Initialization
          2. 26.3.4.2.2 I2C Target Status
          3. 26.3.4.2.3 I2C Target Receiver Mode
          4. 26.3.4.2.4 I2C Target Transmitter Mode
      5. 26.3.5 Reset Considerations
      6. 26.3.6 Initialization
      7. 26.3.7 Interrupt and Events Support
        1. 26.3.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 26.3.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 26.3.8 Emulation Modes
    4. 26.4 UNICOMM I2C Registers
      1. 26.4.1 UNICOMMI2CC Registers
      2. 26.4.2 UNICOMMI2CT Registers
  29. 27UNICOMM-SPI
    1. 27.1 UNICOMM-SPI Overview
      1. 27.1.1 Purpose of the Peripheral
      2. 27.1.2 Features
      3. 27.1.3 Functional Block Diagram
      4. 27.1.4 External Connections and Signal Descriptions
    2. 27.2 SPI Operation
      1. 27.2.1  Clock Frequency Support
        1. 27.2.1.1 SPI Clock Generation
      2. 27.2.2  General Architecture
        1. 27.2.2.1 Chip Select and Command Handling
          1. 27.2.2.1.1 Chip Select Control
        2. 27.2.2.2 Command Data Control
        3. 27.2.2.3 Data Format
        4. 27.2.2.4 Delayed data sampling
        5. 27.2.2.5 DMA Operation
      3. 27.2.3  FIFO Operation
        1. 27.2.3.1 FIFO Size
        2. 27.2.3.2 FIFO Status bits
          1. 27.2.3.2.1 RIS.RX based on FIFO threshold settings
          2. 27.2.3.2.2 RIS.TX based on FIFO threshold settings
        3. 27.2.3.3 Clearing FIFO contents
        4. 27.2.3.4 Hardware monitors empty, full and overflow conditions
      4. 27.2.4  Suspend communication
        1. 27.2.4.1 SPI IDLE State Requirements
      5. 27.2.5  Internal Loopback Operation
      6. 27.2.6  Repeat Transfer mode
      7. 27.2.7  Receive Timeout
      8. 27.2.8  Line Timeout
      9. 27.2.9  Protocol Descriptions
        1. 27.2.9.1 Motorola SPI Frame Format
        2. 27.2.9.2 Texas Instruments Synchronous Serial Frame Format
      10. 27.2.10 Status Flags
      11. 27.2.11 Module configuration
      12. 27.2.12 Reset Considerations
      13. 27.2.13 Initialization
      14. 27.2.14 Interrupt and Events Support
        1. 27.2.14.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 27.2.14.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      15. 27.2.15 Emulation Modes
        1. 27.2.15.1 Graceful Halt
    3. 27.3 UNICOMMSPI Registers
  30. 28Timers (TIMx)
    1. 28.1 TIMx Overview
      1. 28.1.1 TIMG Overview
        1. 28.1.1.1 TIMG Features
        2. 28.1.1.2 Functional Block Diagram
      2. 28.1.2 TIMA Overview
        1. 28.1.2.1 TIMA Features
        2. 28.1.2.2 Functional Block Diagram
      3. 28.1.3 TIMx Instance Configuration
    2. 28.2 TIMx Operation
      1. 28.2.1  Timer Counter
        1. 28.2.1.1 Clock Source Select and Prescaler
          1. 28.2.1.1.1 Internal Clock and Prescaler
          2. 28.2.1.1.2 External Signal Trigger
        2. 28.2.1.2 Repeat Counter (TIMA only)
      2. 28.2.2  Counting Mode Control
        1. 28.2.2.1 One-shot and Periodic Modes
        2. 28.2.2.2 Down Counting Mode
        3. 28.2.2.3 Up/Down Counting Mode
        4. 28.2.2.4 Up Counting Mode
        5. 28.2.2.5 Phase Load (TIMA only)
      3. 28.2.3  Capture/Compare Module
        1. 28.2.3.1 Capture Mode
          1. 28.2.3.1.1 Input Selection, Counter Conditions, and Inversion
            1. 28.2.3.1.1.1 CCP Input Edge Synchronization
            2. 28.2.3.1.1.2 CCP Input Pulse Conditions
            3. 28.2.3.1.1.3 Counter Control Operation
            4. 28.2.3.1.1.4 CCP Input Filtering
            5. 28.2.3.1.1.5 Input Selection
          2. 28.2.3.1.2 Use Cases
            1. 28.2.3.1.2.1 Edge Time Capture
            2. 28.2.3.1.2.2 Period Capture
            3. 28.2.3.1.2.3 Pulse Width Capture
            4. 28.2.3.1.2.4 Combined Pulse Width and Period Time
          3. 28.2.3.1.3 QEI Mode (TIMG with QEI support only)
            1. 28.2.3.1.3.1 QEI With 2-Signal
            2. 28.2.3.1.3.2 QEI With Index Input
            3. 28.2.3.1.3.3 QEI Error Detection
          4. 28.2.3.1.4 Hall Input Mode (TIMG with QEI support only)
        2. 28.2.3.2 Compare Mode
          1. 28.2.3.2.1 Edge Count
      4. 28.2.4  Shadow Load and Shadow Compare
        1. 28.2.4.1 Shadow Load (TIMG4-7, TIMA only)
        2. 28.2.4.2 Shadow Compare (TIMG4-7, TIMG12-13, TIMA only)
      5. 28.2.5  Output Generator
        1. 28.2.5.1 Configuration
        2. 28.2.5.2 Use Cases
          1. 28.2.5.2.1 Edge-Aligned PWM
          2. 28.2.5.2.2 Center-Aligned PWM
          3. 28.2.5.2.3 Asymmetric PWM (TIMA only)
          4. 28.2.5.2.4 Complementary PWM With Deadband Insertion (TIMA only)
        3. 28.2.5.3 Forced Output
      6. 28.2.6  Fault Handler (TIMA only)
        1. 28.2.6.1 Fault Input Conditioning
        2. 28.2.6.2 Fault Input Sources
        3. 28.2.6.3 Counter Behavior With Fault Conditions
        4. 28.2.6.4 Output Behavior With Fault Conditions
      7. 28.2.7  Synchronization With Cross Trigger
        1. 28.2.7.1 Main Timer Cross Trigger Configuration
        2. 28.2.7.2 Secondary Timer Cross Trigger Configuration
      8. 28.2.8  Low Power Operation
      9. 28.2.9  Interrupt and Event Support
        1. 28.2.9.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 28.2.9.2 Generic Event Publisher and Subscriber (GEN_EVENT0 and GEN_EVENT1)
        3. 28.2.9.3 Generic Subscriber Event Example (COMP to TIMx)
      10. 28.2.10 Debug Handler (TIMA Only)
    3. 28.3 TIMx Registers
  31. 29TIMB
    1. 29.1 TIMB Overview
      1. 29.1.1 Features
      2. 29.1.2 TIMB Block Diagram
    2. 29.2 TIMB Operation
      1. 29.2.1 Counter Block Operation
        1. 29.2.1.1 Clock Source Selection
        2. 29.2.1.2 Counter Reset Generation
        3. 29.2.1.3 Event Based Enable and Disable
        4. 29.2.1.4 Event Generation
        5. 29.2.1.5 Interrupt Generation
        6. 29.2.1.6 Counter Behavior on a Debug Halt
        7. 29.2.1.7 Hardware Locking of Configuration Registers
    3. 29.3 TIMB Example Applications
      1. 29.3.1 Periodic Interrupt Generation
      2. 29.3.2 Counter Chaining
      3. 29.3.3 Event Counting
      4. 29.3.4 Event Duration Measurement
      5. 29.3.5 Event Sequence Checking
      6. 29.3.6 PWM Generation
    4. 29.4 TIMB Registers
  32. 30Low Frequency Subsystem (LFSS)
    1. 30.1  Overview
    2. 30.2  Clock System
    3. 30.3  LFSS Reset Using VBAT
    4. 30.4  Power Domains and Supply Detection
      1. 30.4.1 Startup When VBAT Powers on First
      2. 30.4.2 Startup when VDD powers on first
      3. 30.4.3 Behavior When VDD is Lost
      4. 30.4.4 Behavior when VBAT is lost
      5. 30.4.5 Behavior when the device goes into SHUTDOWN mode
      6. 30.4.6 Supercapacitor Charging Circuit
    5. 30.5  Real Time Counter (RTC_x)
    6. 30.6  Independent Watchdog Timer (IWDT)
    7. 30.7  Tamper Input and Output
      1. 30.7.1 IOMUX Mode
      2. 30.7.2 Tamper Mode
        1. 30.7.2.1 Tamper Event Detection
        2. 30.7.2.2 Timestamp Event Output
        3. 30.7.2.3 Heartbeat Generator
        4. 30.7.2.4 RTC Clock Output
    8. 30.8  Scratchpad Memory
    9. 30.9  Lock Function of RTC, TIO, and IWDT
    10. 30.10 LFSS Registers
  33. 31Low Frequency Subsystem (LFSS_B)
    1. 31.1 Overview
    2. 31.2 Clock System
    3. 31.3 LFSS Reset
    4. 31.4 Real Time Counter (RTC_x)
    5. 31.5 Independent Watchdog Timer (IWDT)
    6. 31.6 Lock Function of RTC and IWDT
    7. 31.7 LFSS Registers
  34. 32RTC
    1. 32.1 Overview
      1. 32.1.1 RTC Instances
    2. 32.2 Basic Operation
    3. 32.3 Configuration
      1. 32.3.1  Clocking
      2. 32.3.2  Reading and Writing to RTC Peripheral Registers
      3. 32.3.3  Binary vs. BCD
      4. 32.3.4  Leap Year Handling
      5. 32.3.5  Calendar Alarm Configuration
      6. 32.3.6  Interval Alarm Configuration
      7. 32.3.7  Periodic Alarm Configuration
      8. 32.3.8  Calibration
        1. 32.3.8.1 Crystal Offset Error
          1. 32.3.8.1.1 Offset Error Correction Mechanism
        2. 32.3.8.2 Crystal Temperature Error
          1. 32.3.8.2.1 Temperature Drift Correction Mechanism
      9. 32.3.9  RTC Prescaler Extension
      10. 32.3.10 RTC Timestamp Capture
      11. 32.3.11 RTC Events
        1. 32.3.11.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 32.3.11.2 Generic Event Publisher (GEN_EVENT)
    4. 32.4 RTC Registers
  35. 33IWDT
    1. 33.1 920
    2. 33.2 IWDT Clock Configuration
    3. 33.3 IWDT Period Selection
    4. 33.4 Debug Behavior of the IWDT
    5. 33.5 IWDT Registers
  36. 34Window Watchdog Timer (WWDT)
    1. 34.1 WWDT Overview
      1. 34.1.1 Watchdog Mode
      2. 34.1.2 Interval Timer Mode
    2. 34.2 WWDT Operation
      1. 34.2.1 Mode Selection
      2. 34.2.2 Clock Configuration
      3. 34.2.3 Low-Power Mode Behavior
      4. 34.2.4 Debug Behavior
      5. 34.2.5 WWDT Events
        1. 34.2.5.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 34.3 WWDT Registers
  37. 35Debug
    1. 35.1 DEBUGSS Overview
      1. 35.1.1 Debug Interconnect
      2. 35.1.2 Physical Interface
      3. 35.1.3 Debug Access Ports
    2. 35.2 DEBUGSS Operation
      1. 35.2.1 Debug Features
        1. 35.2.1.1 Processor Debug
          1. 35.2.1.1.1 Breakpoint Unit (BPU)
          2. 35.2.1.1.2 Data Watchpoint and Trace Unit (DWT)
        2. 35.2.1.2 Peripheral Debug
        3. 35.2.1.3 EnergyTrace Technology
      2. 35.2.2 Behavior in Low Power Modes
      3. 35.2.3 Restricting Debug Access
      4. 35.2.4 Mailbox (DSSM)
        1. 35.2.4.1 DSSM Events
          1. 35.2.4.1.1 CPU Interrupt Event (CPU_INT)
        2. 35.2.4.2 Reference
    3. 35.3 DEBUGSS Registers
  38. 36Revision History

23.3 SPI Registers

Table 23-7 lists the memory-mapped registers for the SPI registers. All register offset addresses not listed in Table 23-7 should be considered as reserved locations and the register contents should not be modified.

Table 23-7 SPI Registers
Offset Acronym Register Name Group Section
800h PWREN Power enable Go
804h RSTCTL Reset Control Go
808h CLKCFG Peripheral Clock Configuration Register Go
814h STAT Status Register Go
1000h CLKDIV Clock Divider Go
1004h CLKSEL Clock Select for Ultra Low Power peripherals Go
1018h PDBGCTL Peripheral Debug Control Go
1020h IIDX Interrupt Index Register CPU_INT Go
1028h IMASK Interrupt mask CPU_INT Go
1030h RIS Raw interrupt status CPU_INT Go
1038h MIS Masked interrupt status CPU_INT Go
1040h ISET Interrupt set CPU_INT Go
1048h ICLR Interrupt clear CPU_INT Go
1050h IIDX Interrupt Index Register DMA_TRIG_RX Go
1058h IMASK Interrupt mask DMA_TRIG_RX Go
1060h RIS Raw interrupt status DMA_TRIG_RX Go
1068h MIS Masked interrupt status DMA_TRIG_RX Go
1070h ISET Interrupt set DMA_TRIG_RX Go
1078h ICLR Interrupt clear DMA_TRIG_RX Go
1080h IIDX Interrupt Index Register DMA_TRIG_TX Go
1088h IMASK Interrupt mask DMA_TRIG_TX Go
1090h RIS Raw interrupt status DMA_TRIG_TX Go
1098h MIS Masked interrupt status DMA_TRIG_TX Go
10A0h ISET Interrupt set DMA_TRIG_TX Go
10A8h ICLR Interrupt clear DMA_TRIG_TX Go
10E0h EVT_MODE Event Mode Go
10E4h INTCTL Interrupt control register Go
1100h CTL0 SPI control register 0 Go
1104h CTL1 SPI control register 1 Go
1108h CLKCTL Clock prescaler and divider register. Go
110Ch IFLS Interrupt FIFO Level Select Register Go
1110h STAT Status Register Go
1130h RXDATA RXDATA Register Go
1140h TXDATA TXDATA Register Go

Complex bit access types are encoded to fit into small table cells. Table 23-8 shows the codes that are used for access types in this section.

Table 23-8 SPI Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
WK W
K		 Write
Write protected by a key
Reset or Default Value
-n Value after reset or the default value

23.3.1 PWREN (Offset = 800h) [Reset = 00000000h]

PWREN is shown in Figure 23-9 and described in Table 23-9.

Return to the Summary Table.

Register to control the power state

Figure 23-9 PWREN
31 30 29 28 27 26 25 24
KEY
W-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED ENABLE
R-0h R/WK-0h
Table 23-9 PWREN Field Descriptions
Bit Field Type Reset Description
31-24 KEY W 0h KEY to allow Power State Change
  • 26h = KEY to allow write access to this register
23-1 RESERVED R 0h
0 ENABLE R/WK 0h Enable the power

KEY must be set to 26h to write to this bit.

  • 0h = Disable Power
  • 1h = Enable Power

23.3.2 RSTCTL (Offset = 804h) [Reset = 00000000h]

RSTCTL is shown in Figure 23-10 and described in Table 23-10.

Return to the Summary Table.

Register to control reset assertion and de-assertion

Figure 23-10 RSTCTL
31 30 29 28 27 26 25 24
KEY
W-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED RESETSTKYCLR RESETASSERT
R-0h WK-0h WK-0h
Table 23-10 RSTCTL Field Descriptions
Bit Field Type Reset Description
31-24 KEY W 0h Unlock key
  • B1h = KEY to allow write access to this register
23-2 RESERVED R 0h
1 RESETSTKYCLR WK 0h Clear the RESETSTKY bit in the STAT register

KEY must be set to B1h to write to this bit.

  • 0h = Writing 0 has no effect
  • 1h = Clear reset sticky bit
0 RESETASSERT WK 0h Assert reset to the peripheral

KEY must be set to B1h to write to this bit.

  • 0h = Writing 0 has no effect
  • 1h = Assert reset

23.3.3 CLKCFG (Offset = 808h) [Reset = 00000000h]

CLKCFG is shown in Figure 23-11 and described in Table 23-11.

Return to the Summary Table.

Peripheral Clock Configuration Register

Figure 23-11 CLKCFG
31 30 29 28 27 26 25 24
KEY
W-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED BLOCKASYNC
R-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED
R-0h
Table 23-11 CLKCFG Field Descriptions
Bit Field Type Reset Description
31-24 KEY W 0h KEY to Allow State Change -- 0xA9
  • A9h = key value to allow change field of GPRCM
23-9 RESERVED R 0h
8 BLOCKASYNC R/W 0h Async Clock Request is blocked from starting SYSOSC or forcing bus clock to 32MHz
  • 0h = Not block async clock request
  • 1h = Block async clock request
7-0 RESERVED R 0h

23.3.4 STAT (Offset = 814h) [Reset = 00000000h]

STAT is shown in Figure 23-12 and described in Table 23-12.

Return to the Summary Table.

peripheral enable and reset status

Figure 23-12 STAT
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED RESETSTKY
R-0h R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED
R-0h
Table 23-12 STAT Field Descriptions
Bit Field Type Reset Description
31-17 RESERVED R 0h
16 RESETSTKY R 0h This bit indicates, if the peripheral was reset, since this bit was cleared by RESETSTKYCLR in the RSTCTL register
  • 0h = The peripheral has not been reset since this bit was last cleared by RESETSTKYCLR in the RSTCTL register
  • 1h = The peripheral was reset since the last bit clear
15-0 RESERVED R 0h

23.3.5 CLKDIV (Offset = 1000h) [Reset = 00000000h]

CLKDIV is shown in Figure 23-13 and described in Table 23-13.

Return to the Summary Table.

This register is used to specify module-specific divide ratio of the functional clock

Figure 23-13 CLKDIV
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RATIO
R-0h R/W-0h
Table 23-13 CLKDIV Field Descriptions
Bit Field Type Reset Description
31-3 RESERVED R 0h
2-0 RATIO R/W 0h Selects divide ratio of module clock
  • 0h = Do not divide clock source
  • 1h = Divide clock source by 2
  • 2h = Divide clock source by 3
  • 3h = Divide clock source by 4
  • 4h = Divide clock source by 5
  • 5h = Divide clock source by 6
  • 6h = Divide clock source by 7
  • 7h = Divide clock source by 8

23.3.6 CLKSEL (Offset = 1004h) [Reset = 00000000h]

CLKSEL is shown in Figure 23-14 and described in Table 23-14.

Return to the Summary Table.

Clock source selection for peripherals

Figure 23-14 CLKSEL
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED SYSCLK_SEL MFCLK_SEL LFCLK_SEL RESERVED
R-0h R/W-0h R/W-0h R/W-0h R-0h
Table 23-14 CLKSEL Field Descriptions
Bit Field Type Reset Description
31-4 RESERVED R 0h
3 SYSCLK_SEL R/W 0h Selects SYSCLK as clock source if enabled
  • 0h = Does not select this clock as a source
  • 1h = Select this clock as a source
2 MFCLK_SEL R/W 0h Selects MFCLK as clock source if enabled
  • 0h = Does not select this clock as a source
  • 1h = Select this clock as a source
1 LFCLK_SEL R/W 0h Selects LFCLK as clock source if enabled
  • 0h = Does not select this clock as a source
  • 1h = Select this clock as a source
0 RESERVED R 0h

23.3.7 PDBGCTL (Offset = 1018h) [Reset = 00000000h]

PDBGCTL is shown in Figure 23-15 and described in Table 23-15.

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This register can be used by the software developer to control the behavior of the peripheral relative to the 'Core Halted' input

Figure 23-15 PDBGCTL
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED SOFT FREE
R-0h R/W-0h R/W-0h
Table 23-15 PDBGCTL Field Descriptions
Bit Field Type Reset Description
31-2 RESERVED R 0h
1 SOFT R/W 1h Soft halt boundary control. This function is only available, if FREE is set to 'STOP'
  • 0h = The peripheral will halt immediately, even if the resultant state will result in corruption if the system is restarted
  • 1h = The peripheral blocks the debug freeze until it has reached a boundary where it can resume without corruption
0 FREE R/W 1h Free run control
  • 0h = The peripheral freezes functionality while the Core Halted input is asserted and resumes when it is deasserted.
  • 1h = The peripheral ignores the state of the Core Halted input

23.3.8 IIDX (Offset = 1020h) [Reset = 00000000h]

IIDX is shown in Figure 23-16 and described in Table 23-16.

Return to the Summary Table.

This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, … IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred. On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in [RIS] and [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.

Figure 23-16 IIDX
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED STAT
R-0h R-0h
Table 23-16 IIDX Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-0 STAT R 0h Interrupt index status
  • 00h = No interrupt pending
  • 1h = RX FIFO Overflow Event/interrupt pending
  • 2h = Transmit Parity Event/interrupt pending
  • 3h = SPI receive time-out interrupt
  • 4h = Receive Event/interrupt pending
  • 5h = Transmit Event/interrupt pending
  • 6h = Transmit Buffer Empty Event/interrupt pending
  • 7h = End of Transmit Event/interrupt pending
  • 8h = DMA Done for Receive Event/interrupt pending
  • 9h = DMA Done for Transmit Event/interrupt pending
  • Ah = TX FIFO underflow interrupt
  • Bh = RX FIFO Full Interrupt

23.3.9 IMASK (Offset = 1028h) [Reset = 00000000h]

IMASK is shown in Figure 23-17 and described in Table 23-17.

Return to the Summary Table.

Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Figure 23-17 IMASK
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED RXFULL TXFIFO_UNF DMA_DONE_TX
R-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
DMA_DONE_RX IDLE TXEMPTY TX RX RTOUT PER RXFIFO_OVF
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
Table 23-17 IMASK Field Descriptions
Bit Field Type Reset Description
31-11 RESERVED R 0h
10 RXFULL R/W 0h RX FIFO Full Interrupt Mask
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrupt Mask
9 TXFIFO_UNF R/W 0h TX FIFO underflow interrupt mask
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrupt Mask
8 DMA_DONE_TX R/W 0h DMA Done 1 event for TX event mask.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrupt Mask
7 DMA_DONE_RX R/W 0h DMA Done 1 event for RX event mask.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrupt Mask
6 IDLE R/W 0h SPI Idle event mask.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrupt Mask
5 TXEMPTY R/W 0h Transmit FIFO Empty event mask.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrupt Mask
4 TX R/W 0h Transmit FIFO event mask.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrupt Mask
3 RX R/W 0h Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrupt Mask
2 RTOUT R/W 0h Enable SPI Receive Time-Out event mask.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrupt Mask
1 PER R/W 0h Parity error event mask.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrupt Mask
0 RXFIFO_OVF R/W 0h RXFIFO overflow event mask.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrupt Mask

23.3.10 RIS (Offset = 1030h) [Reset = 00000000h]

RIS is shown in Figure 23-18 and described in Table 23-18.

Return to the Summary Table.

Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 23-18 RIS
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED RXFULL TXFIFO_UNF DMA_DONE_TX
R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
DMA_DONE_RX IDLE TXEMPTY TX RX RTOUT PER RXFIFO_OVF
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
Table 23-18 RIS Field Descriptions
Bit Field Type Reset Description
31-11 RESERVED R 0h
10 RXFULL R 0h RX FIFO Full Interrupt
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
9 TXFIFO_UNF R 0h TX FIFO Underflow Interrupt
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
8 DMA_DONE_TX R 0h DMA Done 1 event for TX. This interrupt is set if the TX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
7 DMA_DONE_RX R 0h DMA Done 1 event for RX. This interrupt is set if the RX DMA channel sends the DONE signal. This allows the handling of the DMA event inside the mapped peripheral.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
6 IDLE R 0h SPI has done finished transfers and changed into IDLE mode. This bit is set when BUSY goes low.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
5 TXEMPTY R 0h Transmit FIFO Empty interrupt mask. This interrupt is set if all data in the Transmit FIFO have been move to the shift register.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
4 TX R 0h Transmit FIFO event..This interrupt is set if the selected Transmit FIFO level has been reached.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
3 RX R 0h Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
2 RTOUT R 0h SPI Receive Time-Out event.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
1 PER R 0h Parity error event: this bit is set if a Parity error has been detected
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
0 RXFIFO_OVF R 0h RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred

23.3.11 MIS (Offset = 1038h) [Reset = 00000000h]

MIS is shown in Figure 23-19 and described in Table 23-19.

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Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 23-19 MIS
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED RXFULL TXFIFO_UNF DMA_DONE_TX
R-0h R-0h R-0h R-0h
7 6 5 4 3 2 1 0
DMA_DONE_RX IDLE TXEMPTY TX RX RTOUT PER RXFIFO_OVF
R-0h R-0h R-0h R-0h R-0h R-0h R-0h R-0h
Table 23-19 MIS Field Descriptions
Bit Field Type Reset Description
31-11 RESERVED R 0h
10 RXFULL R 0h RX FIFO Full Interrupt
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
9 TXFIFO_UNF R 0h TX FIFO underflow interrupt
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
8 DMA_DONE_TX R 0h Masked DMA Done 1 event for TX.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
7 DMA_DONE_RX R 0h Masked DMA Done 1 event for RX.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
6 IDLE R 0h Masked SPI IDLE mode event.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
5 TXEMPTY R 0h Masked Transmit FIFO Empty event.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
4 TX R 0h Masked Transmit FIFO event. This interrupt is set if the selected Transmit FIFO level has been reached.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
3 RX R 0h Masked receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
2 RTOUT R 0h Masked SPI Receive Time-Out Interrupt.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrupt Mask
1 PER R 0h Masked Parity error event: this bit if a Parity error has been detected
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
0 RXFIFO_OVF R 0h Masked RXFIFO overflow event. This interrupt is set if an RX FIFO overflow has been detected.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred

23.3.12 ISET (Offset = 1040h) [Reset = 00000000h]

ISET is shown in Figure 23-20 and described in Table 23-20.

Return to the Summary Table.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 23-20 ISET
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED RXFULL TXFIFO_UNF DMA_DONE_TX
R-0h W-0h W-0h W-0h
7 6 5 4 3 2 1 0
DMA_DONE_RX IDLE TXEMPTY TX RX RTOUT PER RXFIFO_OVF
W-0h W-0h W-0h W-0h W-0h W-0h W-0h W-0h
Table 23-20 ISET Field Descriptions
Bit Field Type Reset Description
31-11 RESERVED R 0h
10 RXFULL W 0h Set RX FIFO Full Event
  • 0h = Writing has no effect
  • 1h = Set Interrupt
9 TXFIFO_UNF W 0h Set TX FIFO Underflow Event
  • 0h = Writing has no effect
  • 1h = Set interrupt
8 DMA_DONE_TX W 0h Set DMA Done 1 event for TX.
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
7 DMA_DONE_RX W 0h Set DMA Done 1 event for RX.
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
6 IDLE W 0h Set SPI IDLE mode event.
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
5 TXEMPTY W 0h Set Transmit FIFO Empty event.
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
4 TX W 0h Set Transmit FIFO event.
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
3 RX W 0h Set Receive FIFO event.
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
2 RTOUT W 0h Set SPI Receive Time-Out Event.
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt Mask
1 PER W 0h Set Parity error event.
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
0 RXFIFO_OVF W 0h Set RXFIFO overflow event.
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt

23.3.13 ICLR (Offset = 1048h) [Reset = 00000000h]

ICLR is shown in Figure 23-21 and described in Table 23-21.

Return to the Summary Table.

Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 23-21 ICLR
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED RXFULL TXFIFO_UNF DMA_DONE_TX
R-0h W-0h W-0h W-0h
7 6 5 4 3 2 1 0
DMA_DONE_RX IDLE TXEMPTY TX RX RTOUT PER RXFIFO_OVF
W-0h W-0h W-0h W-0h W-0h W-0h W-0h W-0h
Table 23-21 ICLR Field Descriptions
Bit Field Type Reset Description
31-11 RESERVED R 0h
10 RXFULL W 0h Clear RX FIFO underflow event
  • 0h = Writing has no effect
  • 1h = Clear interrupt
9 TXFIFO_UNF W 0h Clear TXFIFO underflow event
  • 0h = Writing has no effect
  • 1h = Clear interrupt
8 DMA_DONE_TX W 0h Clear DMA Done 1 event for TX.
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
7 DMA_DONE_RX W 0h Clear DMA Done 1 event for RX.
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
6 IDLE W 0h Clear SPI IDLE mode event.
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
5 TXEMPTY W 0h Clear Transmit FIFO Empty event.
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
4 TX W 0h Clear Transmit FIFO event.
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
3 RX W 0h Clear Receive FIFO event.
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
2 RTOUT W 0h Clear SPI Receive Time-Out Event.
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt Mask
1 PER W 0h Clear Parity error event.
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
0 RXFIFO_OVF W 0h Clear RXFIFO overflow event.
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt

23.3.14 IIDX (Offset = 1050h) [Reset = 00000000h]

IIDX is shown in Figure 23-22 and described in Table 23-22.

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This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, … IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred. On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in [RIS] and [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.

Figure 23-22 IIDX
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED STAT
R-0h R-0h
Table 23-22 IIDX Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-0 STAT R 0h Interrupt index status
  • 00h = No interrupt pending
  • 3h = SPI receive time-out interrupt
  • 4h = Receive Event/interrupt pending

23.3.15 IMASK (Offset = 1058h) [Reset = 00000000h]

IMASK is shown in Figure 23-23 and described in Table 23-23.

Return to the Summary Table.

Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Figure 23-23 IMASK
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED RX RTOUT RESERVED
R-0h R/W-0h R/W-0h R-0h
Table 23-23 IMASK Field Descriptions
Bit Field Type Reset Description
31-4 RESERVED R 0h
3 RX R/W 0h Receive FIFO event mask.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrupt Mask
2 RTOUT R/W 0h SPI Receive Time-Out event mask.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrupt Mask
1-0 RESERVED R 0h

23.3.16 RIS (Offset = 1060h) [Reset = 00000000h]

RIS is shown in Figure 23-24 and described in Table 23-24.

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Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 23-24 RIS
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED RX RTOUT RESERVED
R-0h R-0h R-0h R-0h
Table 23-24 RIS Field Descriptions
Bit Field Type Reset Description
31-4 RESERVED R 0h
3 RX R 0h Receive FIFO event.This interrupt is set if the selected Receive FIFO level has been reached
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
2 RTOUT R 0h SPI Receive Time-Out Event.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrupt Mask
1-0 RESERVED R 0h

23.3.17 MIS (Offset = 1068h) [Reset = 00000000h]

MIS is shown in Figure 23-25 and described in Table 23-25.

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Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 23-25 MIS
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED RX RTOUT RESERVED
R-0h R-0h R-0h R-0h
Table 23-25 MIS Field Descriptions
Bit Field Type Reset Description
31-4 RESERVED R 0h
3 RX R 0h Receive FIFO event mask.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
2 RTOUT R 0h SPI Receive Time-Out event mask.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrupt Mask
1-0 RESERVED R 0h

23.3.18 ISET (Offset = 1070h) [Reset = 00000000h]

ISET is shown in Figure 23-26 and described in Table 23-26.

Return to the Summary Table.

Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 23-26 ISET
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED RX RTOUT RESERVED
R-0h W-0h W-0h R-0h
Table 23-26 ISET Field Descriptions
Bit Field Type Reset Description
31-4 RESERVED R 0h
3 RX W 0h Set Receive FIFO event.
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
2 RTOUT W 0h Set SPI Receive Time-Out event.
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt Mask
1-0 RESERVED R 0h

23.3.19 ICLR (Offset = 1078h) [Reset = 00000000h]

ICLR is shown in Figure 23-27 and described in Table 23-27.

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Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 23-27 ICLR
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED RX RTOUT RESERVED
R-0h W-0h W-0h R-0h
Table 23-27 ICLR Field Descriptions
Bit Field Type Reset Description
31-4 RESERVED R 0h
3 RX W 0h Clear Receive FIFO event.
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
2 RTOUT W 0h Clear SPI Receive Time-Out event.
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt Mask
1-0 RESERVED R 0h

23.3.20 IIDX (Offset = 1080h) [Reset = 00000000h]

IIDX is shown in Figure 23-28 and described in Table 23-28.

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This register provides the highest priority enabled interrupt index. Value 0x00 means no event pending. Interrupt 1 is the highest priority, IIDX next highest, 4, 8, … IIDX^31 is the least priority. That is, the least bit position that is set to 1 denotes the highest priority pending interrupt. The priority order is fixed. However, users can implement their own prioritization schemes using other registers that expose the full set of interrupts that have occurred. On each read, only one interrupt is indicated. On a read, the current interrupt (highest priority) is automatically cleared by the hardware and the corresponding interrupt flag in [RIS] and [MIS] are cleared as well. After a read from the CPU (not from the debug interface), the register is updated with the next highest priority interrupt, if none are pending, then it should display 0x0.

Figure 23-28 IIDX
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED STAT
R-0h R-0h
Table 23-28 IIDX Field Descriptions
Bit Field Type Reset Description
31-8 RESERVED R 0h
7-0 STAT R 0h Interrupt index status
  • 00h = No interrupt pending
  • 5h = Transmit Event/interrupt pending

23.3.21 IMASK (Offset = 1088h) [Reset = 00000000h]

IMASK is shown in Figure 23-29 and described in Table 23-29.

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Interrupt Mask. If a bit is set, then corresponding interrupt is un-masked. Un-masking the interrupt causes the raw interrupt to be visible in IIDX, as well as MIS.

Figure 23-29 IMASK
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TX RESERVED
R-0h R/W-0h R-0h
Table 23-29 IMASK Field Descriptions
Bit Field Type Reset Description
31-5 RESERVED R 0h
4 TX R/W 0h Transmit FIFO event mask.
  • 0h = Clear Interrupt Mask
  • 1h = Set Interrupt Mask
3-0 RESERVED R 0h

23.3.22 RIS (Offset = 1090h) [Reset = 00000000h]

RIS is shown in Figure 23-30 and described in Table 23-30.

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Raw interrupt status. Reflects all pending interrupts, regardless of masking. The RIS register allows the user to implement a poll scheme. A flag set in this register can be cleared by writing 1 to the ICLR register bit even if the corresponding IMASK bit is not enabled.

Figure 23-30 RIS
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TX RESERVED
R-0h R-0h R-0h
Table 23-30 RIS Field Descriptions
Bit Field Type Reset Description
31-5 RESERVED R 0h
4 TX R 0h Transmit FIFO event: A read returns the current mask for transmit FIFO interrupt. On a write of 1, the mask for transmit FIFO interrupt is set which means the interrupt state will be reflected in MIS.TXMIS. A write of 0 clears the mask which means MIS.TXMIS will not reflect the interrupt.
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
3-0 RESERVED R 0h

23.3.23 MIS (Offset = 1098h) [Reset = 00000000h]

MIS is shown in Figure 23-31 and described in Table 23-31.

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Masked interrupt status. This is an AND of the IMASK and RIS registers.

Figure 23-31 MIS
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TX RESERVED
R-0h R-0h R-0h
Table 23-31 MIS Field Descriptions
Bit Field Type Reset Description
31-5 RESERVED R 0h
4 TX R 0h Masked Transmit FIFO event
  • 0h = Interrupt did not occur
  • 1h = Interrupt occurred
3-0 RESERVED R 0h

23.3.24 ISET (Offset = 10A0h) [Reset = 00000000h]

ISET is shown in Figure 23-32 and described in Table 23-32.

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Interrupt set. Allows interrupts to be set by software (useful in diagnostics and safety checks). Writing a 1 to a bit in ISET will set the event and therefore the related RIS bit also gets set. If the interrupt is enabled through the mask, then the corresponding MIS bit is also set.

Figure 23-32 ISET
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TX RESERVED
R-0h W-0h R-0h
Table 23-32 ISET Field Descriptions
Bit Field Type Reset Description
31-5 RESERVED R 0h
4 TX W 0h Set Transmit FIFO event.
  • 0h = Writing 0 has no effect
  • 1h = Set Interrupt
3-0 RESERVED R 0h

23.3.25 ICLR (Offset = 10A8h) [Reset = 00000000h]

ICLR is shown in Figure 23-33 and described in Table 23-33.

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Interrupt clear. Write a 1 to clear corresponding Interrupt.

Figure 23-33 ICLR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED TX RESERVED
R-0h W-0h R-0h
Table 23-33 ICLR Field Descriptions
Bit Field Type Reset Description
31-5 RESERVED R 0h
4 TX W 0h Clear Transmit FIFO event.
  • 0h = Writing 0 has no effect
  • 1h = Clear Interrupt
3-0 RESERVED R 0h

23.3.26 EVT_MODE (Offset = 10E0h) [Reset = 00000000h]

EVT_MODE is shown in Figure 23-34 and described in Table 23-34.

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Event mode register. It is used to select whether each line is disabled, in software mode (software clears the RIS) or in hardware mode (hardware clears the RIS)

Figure 23-34 EVT_MODE
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED INT2_CFG INT1_CFG INT0_CFG
R-0h R-0h R-0h R-0h
Table 23-34 EVT_MODE Field Descriptions
Bit Field Type Reset Description
31-6 RESERVED R 0h
5-4 INT2_CFG R 2h Event line mode select for event corresponding to none.DMA_TRIG_TX
  • 0h = The interrupt or event line is disabled.
  • 1h = The interrupt or event line is in software mode. Software must clear the RIS.
  • 2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.
3-2 INT1_CFG R 2h Event line mode select for event corresponding to none.DMA_TRIG_RX
  • 0h = The interrupt or event line is disabled.
  • 1h = The interrupt or event line is in software mode. Software must clear the RIS.
  • 2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.
1-0 INT0_CFG R 1h Event line mode select for event corresponding to none.CPU_INT
  • 0h = The interrupt or event line is disabled.
  • 1h = The interrupt or event line is in software mode. Software must clear the RIS.
  • 2h = The interrupt or event line is in hardware mode. The hardware (another module) clears automatically the associated RIS flag.

23.3.27 INTCTL (Offset = 10E4h) [Reset = 00000000h]

INTCTL is shown in Figure 23-35 and described in Table 23-35.

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Interrupt control register

Figure 23-35 INTCTL
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED INTEVAL
R-0h W-0h
Table 23-35 INTCTL Field Descriptions
Bit Field Type Reset Description
31-1 RESERVED R 0h
0 INTEVAL W 0h Writing a 1 to this field re-evaluates the interrupt sources.
  • 0h = The interrupt or event line is disabled.
  • 1h = The interrupt or event line is in software mode. Software must clear the RIS.

23.3.28 CTL0 (Offset = 1100h) [Reset = 00000000h]

CTL0 is shown in Figure 23-36 and described in Table 23-36.

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SPI control register 0

Figure 23-36 CTL0
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED CSCLR CSSEL RESERVED SPH SPO
R-0h R/W-0h R/W-0h R-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
PACKEN FRF DSS
R/W-0h R/W-0h R/W-0h
Table 23-36 CTL0 Field Descriptions
Bit Field Type Reset Description
31-15 RESERVED R 0h
14 CSCLR R/W 0h Clear shift register counter on CS inactive
This bit is relevant only in the peripheral, CTL1.CP=0.
  • 0h = Disable automatic clear of shift register when CS goes to disable.
  • 1h = Enable automatic clear of shift register when CS goes to disable.
13-12 CSSEL R/W 0h Select the CS line to control on data transfer
This bit is applicable for both controller/target mode
  • 0h (R/W) = CS line select: 0
  • 1h (R/W) = CS line select: 1
  • 2h (R/W) = CS line select: 2
  • 3h (R/W) = CS line select: 3
11-10 RESERVED R 0h
9 SPH R/W 0h CLKOUT phase (Motorola SPI frame format only)
This bit selects the clock edge that captures data and enables it to change state. It
has the most impact on the first bit transmitted by either permitting or not permitting a clock transition before the first data capture edge.
  • 0h = Data is captured on the first clock edge transition.
  • 1h = Data is captured on the second clock edge transition.
8 SPO R/W 0h CLKOUT polarity (Motorola SPI frame format only)
  • 0h = SPI produces a steady state LOW value on the CLKOUT
  • 1h = SPI produces a steady state HIGH value on the CLKOUT
7 PACKEN R/W 0h Packing Enable.
When 1, packing feature is enabled inside the IP
When 0, packing feature is disabled inside the IP
  • 0h = Packing feature disabled
  • 1h = Packing feature enabled
6-5 FRF R/W 0h Frame format Select
  • 0h = Motorola SPI frame format (3 wire mode)
  • 1h = Motorola SPI frame format (4 wire mode)
  • 2h = TI synchronous serial frame format
  • 3h = National Microwire frame format
4-0 DSS R/W 0h Data Size Select.
Values 0 - 2 are reserved and shall not be used.
3h = 4_BIT : 4-bit data
SPI allows only values up to 16 Bit
  • 3h (R/W) = Data Size Select bits: 4
  • 4h (R/W) = Data Size Select bits: 5
  • 5h (R/W) = Data Size Select bits: 6
  • 6h (R/W) = Data Size Select bits: 7
  • 7h (R/W) = Data Size Select bits: 8
  • 8h (R/W) = Data Size Select bits: 9
  • 9h (R/W) = Data Size Select bits: 10
  • Ah (R/W) = Data Size Select bits: 11
  • Bh (R/W) = Data Size Select bits: 12
  • Ch (R/W) = Data Size Select bits: 13
  • Dh (R/W) = Data Size Select bits: 14
  • Eh (R/W) = Data Size Select bits: 15
  • Fh (R/W) = Data Size Select bits: 16

23.3.29 CTL1 (Offset = 1104h) [Reset = 00000004h]

CTL1 is shown in Figure 23-37 and described in Table 23-37.

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SPI control register 1

Figure 23-37 CTL1
31 30 29 28 27 26 25 24
RESERVED RXTIMEOUT
R-0h R/W-0h
23 22 21 20 19 18 17 16
REPEATTX
R/W-0h
15 14 13 12 11 10 9 8
CDMODE CDENABLE RESERVED PTEN
R/W-0h R/W-0h R-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED PES PREN MSB POD CP LBM ENABLE
R-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-1h R/W-0h R/W-0h
Table 23-37 CTL1 Field Descriptions
Bit Field Type Reset Description
31-30 RESERVED R 0h
29-24 RXTIMEOUT R/W 0h Receive Timeout (only for Peripheral mode) Defines the number of Clock Cycles before after which the Receive Timeout flag RTOUT is set. The time is calculated using the control register for the clock selection and divider in the Controller mode configuration. A value of 0 disables this function.
  • 0h = Smallest value
  • 3Fh = Highest possible value
23-16 REPEATTX R/W 0h Counter to repeat last transfer 0: repeat last transfer is disabled. x: repeat the last transfer with the given number. The transfer will be started with writing a data into the TX Buffer. Sending the data will be repeated with the given value, so the data will be transferred X+1 times in total. The behavior is identical as if the data would be written into the TX Buffer that many times as defined by the value here. It can be used to clean a transfer or to pull a certain amount of data by a peripheral.
  • 0h = Smallest value
  • FFh = Highest possible value
15-12 CDMODE R/W 0h Command/Data Mode Value

When CTL1.CDENABLE is 1, CS3 line is used as C/D signal to distinguish between Command (C/D low) and Data (C/D high) information.

When a value is written into the CTL1.CDMODE bits, the C/D (CS3) line will go low for the given numbers of byte which are sent by the SPI, starting with the next value to be transmitted after which, C/D line will go high automatically

0: Manual mode with C/D signal as High
1-14: C/D is low while this number of bytes are being sent after which, this field sets to 0 and C/D goes high. Reading this field at any time returns the remaining number of command bytes.
15: Manual mode with C/D signal as Low.
  • 0h = Manual mode: Data
  • 0h = Smallest value
  • Fh = Manual mode: Command
11 CDENABLE R/W 0h Command/Data Mode enable
  • 0h = CS3 is used for Chip Select
  • 1h = CS3 is used as CD signal
10-9 RESERVED R 0h
8 PTEN R/W 0h Parity transmit enable
If enabled, parity transmission will be done for both controller and peripheral modes.
  • 0h = Parity transmission is disabled
  • 1h = Parity transmission is enabled
7 RESERVED R 0h
6 PES R/W 0h Even Parity Select
  • 0h = Odd Parity mode
  • 1h = Even Parity mode
5 PREN R/W 0h Parity receive enable
If enabled, parity reception check will be done for both controller and peripheral modes
In case of a parity miss-match the parity error flag RIS.PER will be set.
  • 0h = Disable Parity receive function
  • 1h = Enable Parity receive function
4 MSB R/W 0h MSB first select. Controls the direction of the receive and transmit shift register.
  • 0h = LSB first
  • 1h = MSB first
3 POD R/W 0h Peripheral-mode: Data output disabled
This bit is relevant only in Peripheral mode. In multiple-peripheral system topologies, SPI controller can broadcast a message to all peripherals, while only one peripheral drives the line.
POD can be used by the SPI peripheral to disable driving data on the line.
  • 0h = SPI can drive the MISO output in peripheral mode.
  • 1h = SPI cannot drive the MISO output in peripheral mode.
2 CP R/W 1h Controller or peripheral mode select. This bit can be modified only when SPI is disabled, CTL1.ENABLE=0.
  • 0h = Select Peripheral mode
  • 1h = Select Controller Mode
1 LBM R/W 0h Loop back mode
  • 0h = Disable loopback mode
  • 1h = Enable loopback mode
0 ENABLE R/W 0h SPI enable
  • 0h = Disable module function
  • 1h = Enable module function

23.3.30 CLKCTL (Offset = 1108h) [Reset = 00000000h]

CLKCTL is shown in Figure 23-38 and described in Table 23-38.

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Clock prescaler and divider register. This register contains the settings for the Clock prescaler and divider settings.

Figure 23-38 CLKCTL
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DSAMPLE RESERVED
R/W-0h R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED SCR
R-0h R/W-0h
Table 23-38 CLKCTL Field Descriptions
Bit Field Type Reset Description
31-28 DSAMPLE R/W 0h Delayed sampling value.
In controller mode the data on the input pin will be delayed sampled by the defined clock cycles of internal functional clock hence relaxing the setup time of input data. This setting is useful in systems where the board delays and external peripheral delays are more than the input setup time of the controller. Please refer to the datasheet for values of controller input setup time and assess what DSAMPLE value meets the requirement of the system.
Note: High values of DSAMPLE can cause HOLD time violations and must be factored in the calculations.
  • 0h = Smallest value
  • Fh = Highest possible value
27-10 RESERVED R 0h
9-0 SCR R/W 0h Serial clock divider: This is used to generate the transmit and receive bit rate of the SPI. The SPI bit rate is (SPI's functional clock frequency)/((SCR+1)*2). SCR is a value from 0-1023.
  • 0h = Smallest value
  • 3FFh = Highest possible value

23.3.31 IFLS (Offset = 110Ch) [Reset = 00000012h]

IFLS is shown in Figure 23-39 and described in Table 23-39.

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The IFLS register is the interrupt FIFO level select register. You can use this register to define the levels at which the TX, RX and timeout interrupt flags are triggered. The interrupts are generated based on a transition through a level rather than being based on the level. That is, the interrupts are generated when the fill level progresses through the trigger level. For example, if the receive trigger level is set to the half-way mark, the interrupt is triggered when the receive FIFO is filled with two or more characters. Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt at the half-way mark.

Figure 23-39 IFLS
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RXIFLSEL TXIFLSEL
R-0h R/W-2h R/W-2h
Table 23-39 IFLS Field Descriptions
Bit Field Type Reset Description
31-6 RESERVED R 0h
5-3 RXIFLSEL R/W 2h SPI Receive Interrupt FIFO Level Select The trigger points for the receive interrupt are as follows:
  • 0h = Reserved
  • 1h = RX FIFO >= 1/4 full
  • 2h = RX FIFO >= 1/2 full (default)
  • 3h = RX FIFO >= 3/4 full
  • 4h = Reserved
  • 5h = RX FIFO is full
  • 6h = Reserved
  • 7h = Trigger when RX FIFO contains >= 1 frame
2-0 TXIFLSEL R/W 2h SPI Transmit Interrupt FIFO Level Select The trigger points for the transmit interrupt are as follows:
  • 0h = Reserved
  • 1h = TX FIFO <= 3/4 empty
  • 2h = TX FIFO <= 1/2 empty (default)
  • 3h = TX FIFO <= 1/4 empty
  • 4h = Reserved
  • 5h = TX FIFO is empty
  • 6h = Reserved
  • 7h = Trigger when TX FIFO has >= 1 frame free.

23.3.32 STAT (Offset = 1110h) [Reset = 00000000h]

STAT is shown in Figure 23-40 and described in Table 23-40.

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Status Register

Figure 23-40 STAT
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED BUSY RNF RFE TNF TFE
R-0h R-0h R-0h R-0h R-0h R-0h
Table 23-40 STAT Field Descriptions
Bit Field Type Reset Description
31-5 RESERVED R 0h
4 BUSY R 0h Busy
  • 0h = SPI is in idle mode.
  • 1h = SPI is currently transmitting and/or receiving data, or transmit FIFO is not empty.
3 RNF R 1h Receive FIFO not full
  • 0h = Receive FIFO is full.
  • 1h = Receive FIFO is not full.
2 RFE R 1h Receive FIFO empty.
  • 0h = Receive FIFO is not empty.
  • 1h = Receive FIFO is empty.
1 TNF R 1h Transmit FIFO not full
  • 0h = Transmit FIFO is full.
  • 1h = Transmit FIFO is not full.
0 TFE R 1h Transmit FIFO empty.
  • 0h = Transmit FIFO is not empty.
  • 1h = Transmit FIFO is empty.

23.3.33 RXDATA (Offset = 1130h) [Reset = 00000000h]

RXDATA is shown in Figure 23-41 and described in Table 23-41.

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RXDATA Register
Reading this register returns value(s) of FIFO. If the FIFO is empty the last read value is returned.

Writing has not effect and is ignored.
When PACKEN=1,two entries of the FIFO are returned as a 32-bit value. When PACKEN=0, 1 entry of FIFO is returned as 16-bit value.

Figure 23-41 RXDATA
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R-0h
Table 23-41 RXDATA Field Descriptions
Bit Field Type Reset Description
31-0 DATA R 0h Received Data
When PACKEN=1,two entries of the FIFO are returned as a 32-bit value. When PACKEN=0, 1 entry of FIFO is returned as 16-bit value.
As data values are removed by the receive logic from the incoming data frame, they are placed into the entry in the receive FIFO, pointed to by the current FIFO write pointer.
Received data less than 16 bits is automatically right justified in the receive buffer.
  • 0h = Smallest value
  • FFFFFFFFh = Highest possible value

23.3.34 TXDATA (Offset = 1140h) [Reset = 00000000h]

TXDATA is shown in Figure 23-42 and described in Table 23-42.

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TXDATA Register
Writing puts the data into the TX FIFO. Reading this register returns the last written value.
When PACKEN=0, only the lower 16-bits of data written into the register is transferred to one 16-bits wide TX FIFO entry
When PACKEN=1, upper and lower 16-bits of 32-bit write data are transferred to two16-bits wide TX FIFO entry

Figure 23-42 TXDATA
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA
R/W-0h
Table 23-42 TXDATA Field Descriptions
Bit Field Type Reset Description
31-0 DATA R/W 0h Transmit Data

When read, last written value will be returned. If the last write to this field was a 32-bit write (with PACKEN=1), 32-bits will be returned and if the last write was a 16-bit write (PACKEN=0), those 16-bits will be returned.

When written, one or two FIFO entries will be written depending on PACKEN value. Data values are removed from the transmit FIFO one value at a time by the transmit logic. It is loaded into the transmit serial shifter, then serially shifted out onto the TXD output pin at the programmed bit rate.

When a data size of less than 16 bits is selected, the user must right-justify data written to the transmit FIFO. The transmit logic ignores the unused bits.
  • 0h = Smallest value
  • FFFFFFFFh = Highest possible value