ZHDU116G January 2018 – June 2024 CC1312PSIP , CC1312R , CC1352P , CC1352R , CC2642R , CC2642R-Q1 , CC2652P , CC2652PSIP , CC2652R , CC2652RB , CC2652RSIP , CC2662R-Q1
下面的软件伪代码示例描述了主机软件通常执行的操作。该示例启动哈希引擎,新建一个哈希会话以通过 DMA 接口接收输入数据。最终,通过从器件接口读取中间摘要(非最终哈希运算结果)或最终的哈希摘要(最终哈希运算结果)作为结果摘要。
// configure master control module
write CTRL_ALG_SEL 0x0000_0008 // enable DMA path to the SHA-512 engine
write CTRL_INT_CLR 0x0000_0001 // clear any outstanding events
// configure hash engine
write HASH_MODE = 0x0000_0020 // indicate the start of a resumed hash session and SHA512
write HASH_LENGTH_L// write the length of the total message (lo)
write HASH_LENGTH_H// write the length of the total message (hi)
// write the initial digest
write HASH_DIGEST_A
...
write HASH_DIGEST_P
// if the final digest is required (pad the input DMA data), write the following register
write HASH_IO_BUF_CTRL = 0x80 // pad the data that is transferred via DMA
// configure DMAC
write DMAC_CH0_CTRL 0x0000_00001 // enable DMA channel 0
write DMAC_CH0_EXTADDR <ext_memory_address>// base address of the data in ext. memory
write DMAC_CH0_DMALENGTH <length> // input data in bytes
wait CTRL_INT_STAT[0] = '1' // wait for operation done (hash and DMAC are ready)
check CTRL_INT_STAT[31] == '0' //check for the absence of errors
// read digest
read HASH_DIGEST_A
...
read HASH_DIGEST_P
// acknowledge result and clear interrupts
write HASH_IO_BUF_CTRL = 0x01 // acknowledge reading of the digest
write CTRL_INT_CLR 0x0000_0001// clear the interrupt
write CTRL_ALG_SEL 0x0000_0000// disable the master control/DMA clock
// end of algorithm