SLAU962A December   2025  â€“ June 2026 MSPM33C321A , MSPM33C321A-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation
    5.     Support Resources
    6.     Trademarks
  3. 1 Architecture
    1. 1.1 Architecture Overview
    2. 1.2 Bus Organization
    3. 1.3 Platform Memory Map
      1. 1.3.1 Code Region
      2. 1.3.2 SRAM Region
      3. 1.3.3 Peripheral Region
      4. 1.3.4 System PPB Region
    4. 1.4 Boot Configuration
      1. 1.4.1 Configuration Memory
      2. 1.4.2 NON_MAIN_Configuration Registers
    5. 1.5 Factory Constants
      1. 1.5.1 FACTORYREGION Registers
    6. 1.6 Memory configuration
      1. 1.6.1 memcfg Registers
  4. 2  PMCU
    1. 2.1 PMCU Overview
      1. 2.1.1 Power Domains
      2. 2.1.2 Operating Modes
        1. 2.1.2.1 RUN Mode
        2. 2.1.2.2 SLEEP Mode
        3. 2.1.2.3 STOP Mode
        4. 2.1.2.4 STANDBY Mode
        5. 2.1.2.5 SHUTDOWN Mode
        6. 2.1.2.6 Suspended Low-Power Mode Operation
    2. 2.2 Power Management (PMU)
      1. 2.2.1 Power Supply
      2. 2.2.2 Core Regulator
      3. 2.2.3 Supply Supervisors
        1. 2.2.3.1 Power-on Reset (POR)
        2. 2.2.3.2 Brownout Reset (BOR)
        3. 2.2.3.3 POR and BOR Behavior During Supply Changes
      4. 2.2.4 Bandgap Reference
      5. 2.2.5 VBOOST for Analog Muxes
      6. 2.2.6 Peripheral Enable
        1. 2.2.6.1 Automatic Peripheral Disable in Low Power Modes
    3. 2.3 Clock Module (CKM)
      1. 2.3.1 Oscillators
        1. 2.3.1.1 Internal Low-Frequency Oscillator (LFOSC)
        2. 2.3.1.2 Internal System Oscillator (SYSOSC)
          1. 2.3.1.2.1 SYSOSC Gear Shift
          2. 2.3.1.2.2 SYSOSC Frequency and User Trims
          3. 2.3.1.2.3 SYSOSC Frequency Correction Loop
            1. 2.3.1.2.3.1 SYSOSC FCL in Internal Resistor Mode
        3. 2.3.1.3 System Phase-Locked Loop (SYSPLL)
          1. 2.3.1.3.1 Configuring SYSPLL Output Frequencies
          2. 2.3.1.3.2 Loading SYSPLL Lookup Parameters
          3. 2.3.1.3.3 SYSPLL Startup Time
        4. 2.3.1.4 Low Frequency Crystal Oscillator (LFXT)
        5. 2.3.1.5 LFCLK_IN (Digital Clock)
        6. 2.3.1.6 High Frequency Crystal Oscillator (HFXT)
        7. 2.3.1.7 HFCLK_IN (Digital clock)
      2. 2.3.2 Clocks
        1. 2.3.2.1  MCLK (Main Clock) Tree
        2. 2.3.2.2  MCLK/2 (Half Clock)
        3. 2.3.2.3  MCLK/4 (Quarter Clock)
        4. 2.3.2.4  CPUCLK (Processor Clock)
        5. 2.3.2.5  ULPCLK (Low-Power Clock)
        6. 2.3.2.6  MFCLK (Middle Frequency Clock)
        7. 2.3.2.7  LFCLK (Low-Frequency Clock)
        8. 2.3.2.8  HFCLK (High-Frequency External Clock)
        9. 2.3.2.9  CANCLK (CAN-FD Functional Clock)
        10. 2.3.2.10 I2SCLK (I2S Functional Clock)
        11. 2.3.2.11 RTCCLK (RTC Clock)
        12. 2.3.2.12 External Clock Output (CLK_OUT)
        13. 2.3.2.13 Direct Clock Connections for Infrastructure
      3. 2.3.3 Clock Tree
        1. 2.3.3.1 Peripheral Clock Source Selection
    4. 2.4 Clock Monitors
      1. 2.4.1 LFCLK Monitor
      2. 2.4.2 MCLK Monitor
      3. 2.4.3 Startup Monitors
        1. 2.4.3.1 LFOSC Startup Monitor
        2. 2.4.3.2 LFXT Startup Monitor
        3. 2.4.3.3 HFCLK Startup Monitor
        4. 2.4.3.4 SYSPLL Startup Monitor
        5. 2.4.3.5 HSCLK Status
    5. 2.5 Frequency Clock Counter (FCC)
      1. 2.5.1 Using the FCC
      2. 2.5.2 FCC Frequency Computation and Accuracy
    6. 2.6 System Controller (SYSCTL)
      1. 2.6.1 Resets and Device Initialization
        1. 2.6.1.1 Reset Levels
          1. 2.6.1.1.1 Power-on Reset (POR) Reset Level
          2. 2.6.1.1.2 Brownout Reset (BOR) Reset Level
          3. 2.6.1.1.3 Boot Reset (BOOTRST) Reset Level
          4. 2.6.1.1.4 System Reset (SYSRST) Reset Level
          5. 2.6.1.1.5 CPU-only Reset (CPURST) Reset Level
        2. 2.6.1.2 Initial Conditions After Power-Up
        3. 2.6.1.3 NRST Pin
        4. 2.6.1.4 SWD Pins
        5. 2.6.1.5 Generating Resets in Software
        6. 2.6.1.6 Reset Cause
        7. 2.6.1.7 Peripheral Reset Control
        8. 2.6.1.8 Boot Fail Handling
      2. 2.6.2 Operating Mode Selection
      3. 2.6.3 Asynchronous Fast Clock Requests
      4. 2.6.4 Flash Bank Address Swap
      5. 2.6.5 Shutdown Mode Handling (if present)
      6. 2.6.6 Configuration Lockout
      7. 2.6.7 System Status
      8. 2.6.8 Error Handling
      9. 2.6.9 SYSCTL Events
        1. 2.6.9.1 CPU Interrupt Event (CPU_INT)
        2. 2.6.9.2 Nonmaskable Interrupt Event (NMI)
    7. 2.7 Quick Start Reference
      1. 2.7.1 Default Device Configuration
      2. 2.7.2 Leveraging MFCLK
      3. 2.7.3 Optimizing Power Consumption in STOP Mode
      4. 2.7.4 Optimizing Power Consumption in STANDBY Mode
      5. 2.7.5 Increasing MCLK and ULPCLK Precision
      6. 2.7.6 Configuring MCLK for Maximum Speed
      7. 2.7.7 High Speed Clock (SYSPLL, HFCLK) Handling in Low-Power Modes
      8. 2.7.8 Optimizing for Lowest Wakeup Latency
    8. 2.8 SYSCTL Registers
  5. 3  CPU
    1. 3.1 Overview
    2. 3.2 CPU
      1. 3.2.1 Arm Cortex-M33 CPU
      2. 3.2.2 CPU Register File
      3. 3.2.3 Stack Behavior
      4. 3.2.4 Execution Modes and Privilege Levels
      5. 3.2.5 Address Space and Supported Data Sizes
      6. 3.2.6 Secure memory partitioning
    3. 3.3 Interrupts and Exceptions
      1. 3.3.1 Peripheral Interrupts (IRQs)
        1. 3.3.1.1 Nested Vectored Interrupt Controller (NVIC)
        2. 3.3.1.2 Wake Up Controller (WUC)
      2. 3.3.2 Interrupt and Exception Table
      3. 3.3.3 Processor Lockup Scenario
    4. 3.4 CPU Peripherals
      1. 3.4.1 System Control Block (SCB)
      2. 3.4.2 System Tick Timer (SysTick)
      3. 3.4.3 Memory Protection Unit (MPU)
      4. 3.4.4 Security Attribute Unit
      5. 3.4.5 Implementation Defined Attribution Unit (IDAU)
      6. 3.4.6 Floating Point Unit (FPU)
      7. 3.4.7 Digital Signal Processing Extension
    5. 3.5 Read-Only Memory (ROM)
  6. 4 Secure ROM
    1. 4.1 ROM Overview
    2. 4.2 Memory Map
    3. 4.3 Boot Configuration Routine (BCR)
      1. 4.3.1 SWD Mass Erase and Factory Reset Commands
      2. 4.3.2 Application HASH Verification
      3. 4.3.3 Fast Boot
    4. 4.4 Bootstrap Loader (BSL)
      1. 4.4.1 Application Version
      2. 4.4.2 GPIO Invoke
      3. 4.4.3 BSL Triggered Mass Erase and Factory Reset
    5. 4.5 Lifecycle Management
      1. 4.5.1 Device Sub-Type
      2. 4.5.2 Lifecycle Transitions
    6. 4.6 Boot and Startup Sequence
      1. 4.6.1 Secure Boot
      2. 4.6.2 Customer Secure Code (CSC)
  7. 5 NVM (Flash)
    1. 5.1 NVM Overview
      1. 5.1.1 Key Features
      2. 5.1.2 System Components
      3. 5.1.3 Terminology
    2. 5.2 Flash Memory Bank Organization
      1. 5.2.1 Banks
      2. 5.2.2 Flash Memory Regions
      3. 5.2.3 Addressing
        1. 5.2.3.1 Flash Memory Map
    3. 5.3 Flash Controller
      1. 5.3.1 Overview of Flash Controller Commands
      2. 5.3.2 NOOP Command
      3. 5.3.3 PROGRAM Command
        1. 5.3.3.1 Program Bit Masking Behavior
        2. 5.3.3.2 Programming Less Than One Flash Word
        3. 5.3.3.3 Target Data Alignment (Devices with Single Flash Word Programming Only)
        4. 5.3.3.4 Target Data Alignment (Devices With Multiword Programming)
        5. 5.3.3.5 Executing a PROGRAM Operation
      4. 5.3.4 ERASE Command
        1. 5.3.4.1 Erase Sector Masking Behavior
        2. 5.3.4.2 Executing an ERASE Operation
      5. 5.3.5 READVERIFY Command
        1. 5.3.5.1 Executing a READVERIFY Operation
      6. 5.3.6 Command Diagnostics
        1. 5.3.6.1 Command Status
        2. 5.3.6.2 Address Translation
        3. 5.3.6.3 Pulse Counts
      7. 5.3.7 Overriding the System Address With a Bank ID, Region ID, and Bank Address
    4. 5.4 Flash Programming Interface
      1. 5.4.1 Flash Resource Ownership Check
      2. 5.4.2 Authorization Check
      3. 5.4.3 FPI SEC Error Handling
      4. 5.4.4 Bank Erase Protection
    5. 5.5 Flash Read Interface
      1. 5.5.1 Bank Address Swapping
      2. 5.5.2 ECC Error Handling
        1. 5.5.2.1 Single bit (correctable) errors
        2. 5.5.2.2 Dual bit (uncorrectable) errors
      3. 5.5.3 GSC SEC Error Handling
    6. 5.6 FLASHCTL Registers
    7. 5.7 FRI Registers
  8. 6 EAM
    1. 6.1 EAM Introduction
    2. 6.2 EAM Operation
      1. 6.2.1 Security Error Aggregator
      2. 6.2.2 Safety Error Aggregator
    3. 6.3 EAM Registers
  9. 7 Direct Memory Access (DMA)
    1. 7.1 DMA Overview
    2. 7.2 DMA Operation
      1. 7.2.1  Addressing Modes
      2. 7.2.2  Channel Types
      3. 7.2.3  Transfer Modes
        1. 7.2.3.1 Single Transfer
        2. 7.2.3.2 Block Transfer
        3. 7.2.3.3 Repeated Single Transfer
        4. 7.2.3.4 Repeated Block Transfer
        5. 7.2.3.5 Stride Mode
      4. 7.2.4  Extended Modes
        1. 7.2.4.1 Fill Mode
        2. 7.2.4.2 Table Mode
      5. 7.2.5  Initiating DMA Transfers
      6. 7.2.6  Stopping DMA Transfers
      7. 7.2.7  Channel Priorities
      8. 7.2.8  Burst Block Mode
      9. 7.2.9  Using DMA with System Interrupts
      10. 7.2.10 DMA Controller Interrupts
      11. 7.2.11 DMA Trigger Event Status
      12. 7.2.12 DMA Operating Mode Support
        1. 7.2.12.1 Transfer in RUN Mode
        2. 7.2.12.2 Transfer in SLEEP Mode
      13. 7.2.13 DMA Address and Data Errors
      14. 7.2.14 Interrupt and Event Support
    3. 7.3 DMA Registers
  10. 8 Events
    1. 8.1 Events Overview
      1. 8.1.1 Event Publisher
      2. 8.1.2 Event Subscriber
      3. 8.1.3 Event Fabric Routing
        1. 8.1.3.1 CPU Interrupt Event Route (CPU_INT)
        2. 8.1.3.2 DMA Trigger Event Route (DMA_TRIGx)
        3. 8.1.3.3 Generic Event Route (GEN_EVENTx)
      4. 8.1.4 Event Routing Map
      5. 8.1.5 Event Propagation Latency
    2. 8.2 Events Operation
      1. 8.2.1 CPU Interrupt
      2. 8.2.2 DMA Trigger
      3. 8.2.3 Peripheral to Peripheral Event
      4. 8.2.4 Extended Module Description Register
      5. 8.2.5 Using Event Registers
        1. 8.2.5.1 Event Registers
        2. 8.2.5.2 Configuring Events
        3. 8.2.5.3 Responding to CPU Interrupts in Application Software
        4. 8.2.5.4 Hardware Event Handling
  11. 9 IOMUX
    1. 9.1 IOMUX Overview
      1. 9.1.1 IO Types and Analog Sharing
    2. 9.2 IOMUX Operation
      1. 9.2.1 Peripheral Function (PF) Assignment
      2. 9.2.2 Logic High to Hi-Z Conversion
      3. 9.2.3 Logic Inversion
      4. 9.2.4 SHUTDOWN Mode Wakeup Logic
      5. 9.2.5 Pullup/Pulldown Resistors
      6. 9.2.6 Drive Strength Control
      7. 9.2.7 Hysteresis and Logic Level Control
    3. 9.3 IOMUX Registers
  12. 10General-Purpose Input/Output (GPIO)
    1. 10.1 GPIO Overview
    2. 10.2 GPIO Operation
      1. 10.2.1 GPIO Ports
      2. 10.2.2 GPIO Read/Write Interface
      3. 10.2.3 GPIO Input Glitch Filtering and Synchronization
      4. 10.2.4 GPIO Fast Wake
      5. 10.2.5 Event Publishers and Subscribers
    3. 10.3 GPIO Registers
  13. 11Global Security Controller
    1. 11.1 GSC Introduction
      1. 11.1.1 GSC Features
    2. 11.2 GSC Operation
      1. 11.2.1 Functional Block Diagram
      2. 11.2.2 Peripheral Protection Controller
        1. 11.2.2.1 DMA controller security
      3. 11.2.3 SRAM Protection Controller
        1. 11.2.3.1 SRAM Page Use Model
      4. 11.2.4 Flash Protection Controller
        1. 11.2.4.1 Flash Bank Security Implementation
        2. 11.2.4.2 Flash Hide Protection
      5. 11.2.5 Strict Secure and Privilege Context Protection
      6. 11.2.6 GSC Configuration Lock
    3. 11.3 GSC Registers
  14. 12PKA
    1. 12.1 PKA Introduction
      1. 12.1.1 PKA features
    2. 12.2 PKA Operation
      1. 12.2.1 Functional Block Diagram
      2. 12.2.2 Theory of Operations
        1. 12.2.2.1 PKCP
        2. 12.2.2.2 Sequencer
      3. 12.2.3 Complex Commands
      4. 12.2.4 Command Execution and Status
      5. 12.2.5 Initialization
      6. 12.2.6 Interrupts support
        1. 12.2.6.1 Interrupt Sources
    3. 12.3 PKA Registers
  15. 13AESADV
    1. 13.1 AES Overview
      1. 13.1.1 AESADV Performance
    2. 13.2 AESADV Operation
      1. 13.2.1 Loading the Key
      2. 13.2.2 Writing Input Data
      3. 13.2.3 Reading Output Data
      4. 13.2.4 Operation Descriptions
        1. 13.2.4.1 Single Block Operation
        2. 13.2.4.2 Electronic Codebook (ECB) Mode
          1. 13.2.4.2.1 ECB Encryption
          2. 13.2.4.2.2 ECB Decryption
        3. 13.2.4.3 Cipher Block Chaining (CBC) Mode
          1. 13.2.4.3.1 CBC Encryption
          2. 13.2.4.3.2 CBC Decryption
        4. 13.2.4.4 Output Feedback (OFB) Mode
          1. 13.2.4.4.1 OFB Encryption
          2. 13.2.4.4.2 OFB Decryption
        5. 13.2.4.5 Cipher Feedback (CFB) Mode
          1. 13.2.4.5.1 CFB Encryption
          2. 13.2.4.5.2 CFB Decryption
        6. 13.2.4.6 Counter (CTR) Mode
          1. 13.2.4.6.1 CTR Encryption
          2. 13.2.4.6.2 CTR Decryption
        7. 13.2.4.7 Galois Counter (GCM) Mode
          1. 13.2.4.7.1 GHASH Operation
          2. 13.2.4.7.2 GCM Operating Modes
            1. 13.2.4.7.2.1 Autonomous GCM Operation
              1. 13.2.4.7.2.1.1 GMAC
            2. 13.2.4.7.2.2 GCM With Pre-Calculations
            3. 13.2.4.7.2.3 GCM Operation With Precalculated H- and Y0-Encrypted Forced to Zero
        8. 13.2.4.8 Counter With Cipher Block Chaining Message Authentication Code (CCM)
          1. 13.2.4.8.1 CCM Operation
      5. 13.2.5 AES Events
        1. 13.2.5.1 CPU Interrupt Event Publisher (CPU_EVENT)
        2. 13.2.5.2 DMA Trigger Event Publisher (DMA_TRIG_DATAIN)
        3. 13.2.5.3 DMA Trigger Event Publisher (DMA_TRIG_DATAOUT)
    3. 13.3 AESADV Registers
  16. 14SHA2
    1. 14.1 SHA Introduction
      1. 14.1.1 SHA features
    2. 14.2 SHA Operation
      1. 14.2.1 Functional Block Diagram
      2. 14.2.2 HMAC Controller
      3. 14.2.3 HASH/HMAC Engine
        1. 14.2.3.1 HMAC processing with MAC Key Input
        2. 14.2.3.2 HMAC processing with digest
        3. 14.2.3.3 HMAC processing with reload digest
    3. 14.3 SHA Auto-Feed Mode
    4. 14.4 SHA Registers
  17. 15CRC
    1. 15.1 CRC Overview
      1. 15.1.1 CRC16-CCITT
      2. 15.1.2 CRC32-ISO3309
    2. 15.2 CRC Operation
      1. 15.2.1 CRC Generator Implementation
      2. 15.2.2 Configuration
        1. 15.2.2.1 Polynomial Selection
        2. 15.2.2.2 Bit Order
        3. 15.2.2.3 Byte Swap
        4. 15.2.2.4 Byte Order
        5. 15.2.2.5 CRC C Library Compatibility
    3. 15.3 CRCP0 Registers
  18. 16Keystore
    1. 16.1 Overview
    2. 16.2 Detailed Description
    3. 16.3 KEYSTORECTL Registers
  19. 17TRNG
    1. 17.1 TRNG Overview
    2. 17.2 TRNG Operation
      1. 17.2.1 TRNG Generation Data Path
      2. 17.2.2 Clock Configuration and Output Rate
      3. 17.2.3 Behavior in Low Power Modes
      4. 17.2.4 Health Tests
        1. 17.2.4.1 Digital Block Startup Self-Test
        2. 17.2.4.2 Analog Block Startup Self-Test
        3. 17.2.4.3 Runtime Health Test
          1. 17.2.4.3.1 Repetition Count Test
          2. 17.2.4.3.2 Adaptive Proportion Test
          3. 17.2.4.3.3 Handling Runtime Health Test Failures
      5. 17.2.5 Configuration
        1. 17.2.5.1 TRNG State Machine
          1. 17.2.5.1.1 Changing TRNG States
        2. 17.2.5.2 Using the TRNG
        3. 17.2.5.3 TRNG Events
          1. 17.2.5.3.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 17.3 TRNG Registers
  20. 18HSADC
    1. 18.1 Introduction
      1. 18.1.1 Features
      2. 18.1.2 Block Diagram
    2. 18.2 HSADC Operation
      1. 18.2.1 ADC Configurability
        1. 18.2.1.1 ADC Clock Configuration
        2. 18.2.1.2 Voltage Reference
        3. 18.2.1.3 Signal Mode
          1. 18.2.1.3.1 Expected Conversion Results
          2. 18.2.1.3.2 Interpreting Conversion Results
      2. 18.2.2 SOC Principle of Operation
        1. 18.2.2.1 HSADC Sequencer Operation
        2. 18.2.2.2 SOC Configuration
        3. 18.2.2.3 Trigger Operation
        4. 18.2.2.4 ADC Acquisition (Sample and Hold) Window
        5. 18.2.2.5 Sample Capacitor Reset
        6. 18.2.2.6 ADC Input Models
        7. 18.2.2.7 Channel Selection
      3. 18.2.3 EOC and Interrupt Operation
        1. 18.2.3.1 Interrupt Overflow
        2. 18.2.3.2 Continue to Interrupt Mode
        3. 18.2.3.3 Early Interrupt Configuration Mode
      4. 18.2.4 Post-Processing Blocks
        1. 18.2.4.1 PPB Limit Detection
        2. 18.2.4.2 PPB Oversampling
          1. 18.2.4.2.1 Accumulation and Average Functions
      5. 18.2.5 ADC Results
        1. 18.2.5.1 FIFO Operation
      6. 18.2.6 Power-Up Sequence
      7. 18.2.7 ADC Timings
        1. 18.2.7.1 ADC Timing Diagrams
    3. 18.3 ADC_LITE_REGS Registers
    4. 18.4 ADC_LITE_RESULT_REGS Registers
  21. 19VREF
    1. 19.1 VREF Overview
    2. 19.2 VREF Operation
      1. 19.2.1 Internal Reference Generation
      2. 19.2.2 External Reference Input
      3. 19.2.3 Analog Peripheral Interface
      4. 19.2.4 Sample and Hold Mode
    3. 19.3 VREF Registers
  22. 20COMP
    1. 20.1 Comparator Overview
    2. 20.2 Comparator Operation
      1. 20.2.1  Comparator Configuration
      2. 20.2.2  Comparator Channels Selection
      3. 20.2.3  Comparator Output
      4. 20.2.4  Output Filter
      5. 20.2.5  Sampled Output Mode
      6. 20.2.6  Blanking Mode
      7. 20.2.7  Reference Voltage Generator
      8. 20.2.8  Comparator Hysteresis
      9. 20.2.9  Input SHORT Switch
      10. 20.2.10 Analog Comparison Feature
      11. 20.2.11 Interrupt and Events Support
        1. 20.2.11.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 20.2.11.2 Generic Event Publisher (GEN_EVENT)
        3. 20.2.11.3 Generic Event Subscribers
    3. 20.3 COMP Registers
  23. 21UNICOMM
    1. 21.1 Overview
      1. 21.1.1 Block Diagram
    2. 21.2 Unicomm Architecture
      1. 21.2.1 Serial Peripheral Group (SPG) Configurations
        1. 21.2.1.1 I2C Pairings
      2. 21.2.2 Enables & Resets
    3. 21.3 High-Level Initialization
    4. 21.4 UNICOMM/SPGSS Registers
      1. 21.4.1 UNICOMM Registers
        1. 21.4.1.1 UNICOMM Registers
      2. 21.4.2 SPG Registers
        1. 21.4.2.1 SPGSS Registers
  24. 22UNICOMM UART
    1. 22.1 UART Overview
      1. 22.1.1 Purpose of the Peripheral
      2. 22.1.2 Features
      3. 22.1.3 Functional Block Diagram
    2. 22.2 UART Operation
      1. 22.2.1 Clock Control
      2. 22.2.2 General Architecture and Protocol
        1. 22.2.2.1 Signal Descriptions
        2. 22.2.2.2 Transmit and Receive Logic
        3. 22.2.2.3 Bit Sampling
        4. 22.2.2.4 Baud Rate Generation
        5. 22.2.2.5 Data Transmission
        6. 22.2.2.6 Error and Status
        7. 22.2.2.7 DMA Operation
        8. 22.2.2.8 Internal Loopback Operation
      3. 22.2.3 Additional Protocol and Feature Support
        1. 22.2.3.1  Local Interconnect Network (LIN) Support
          1. 22.2.3.1.1 LIN Commander Transmit
          2. 22.2.3.1.2 LIN Responder Receive
          3. 22.2.3.1.3 LIN Responder Transmission Delay
        2. 22.2.3.2  Flow Control
        3. 22.2.3.3  RS485 Support
        4. 22.2.3.4  FIFO Operation
        5. 22.2.3.5  Idle-Line Multiprocessor
        6. 22.2.3.6  9-Bit UART Mode
        7. 22.2.3.7  DALI Protocol
        8. 22.2.3.8  Manchester Encoding and Decoding
        9. 22.2.3.9  IrDA Encoding and Decoding
        10. 22.2.3.10 ISO7816 Smart Card Support
        11. 22.2.3.11 Address Detection
        12. 22.2.3.12 Glitch Suppression
      4. 22.2.4 Low Power Operation
      5. 22.2.5 Reset Considerations
      6. 22.2.6 UART Initialization
      7. 22.2.7 Interrupt and Events Support
        1. 22.2.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 22.2.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 22.2.8 Emulation Modes
    3. 22.3 UNICOMMUART Registers
  25. 23UNICOMM-I2C
    1. 23.1 UNICOMM-I2C Overview
      1. 23.1.1 Purpose of the Peripheral
      2. 23.1.2 Features
      3. 23.1.3 Functional Block Diagram
      4. 23.1.4 Environment and External Connections
    2. 23.2 UNICOMM Common Infrastructure
    3. 23.3 Peripheral Functional Description
      1. 23.3.1 Clock Control
        1. 23.3.1.1 Clock Select and I2C Speed
        2. 23.3.1.2 Clock Startup
      2. 23.3.2 Signal Descriptions
      3. 23.3.3 General Architecture
        1. 23.3.3.1  I2C Bus Functional Overview
        2. 23.3.3.2  START and STOP Conditions
        3. 23.3.3.3  Dual Address
        4. 23.3.3.4  Address Format
          1. 23.3.3.4.1 Data Format with 7-Bit Address
          2. 23.3.3.4.2 Data Format with 10-Bit Address
        5. 23.3.3.5  Acknowledge
        6. 23.3.3.6  Repeated Start
        7. 23.3.3.7  Clock Stretching
        8. 23.3.3.8  Clock Low Timeout
        9. 23.3.3.9  Burst Mode
        10. 23.3.3.10 Arbitration
        11. 23.3.3.11 Multiple Controller Mode
        12. 23.3.3.12 Glitch Suppression
        13. 23.3.3.13 DMA Operation
        14. 23.3.3.14 FIFO Operation
          1. 23.3.3.14.1 FIFO Status Flags
          2. 23.3.3.14.2 FIFO Levels
          3. 23.3.3.14.3 Clearing FIFO Contents
        15. 23.3.3.15 Suspend Communication
        16. 23.3.3.16 Low Power Operation
        17. 23.3.3.17 SMBUS 3.0 Support
          1. 23.3.3.17.1 Quick Command
          2. 23.3.3.17.2 SMBUS Enhanced Acknowledge Control
          3. 23.3.3.17.3 Clock Low Timeout Detection
          4. 23.3.3.17.4 Clock High Timeout Detection
          5. 23.3.3.17.5 Cumulative Clock Low Extended Timeout
          6. 23.3.3.17.6 Packet Error Checking (PEC)
          7. 23.3.3.17.7 Host Notify Protocol
          8. 23.3.3.17.8 Alert Response Protocol
          9. 23.3.3.17.9 Address Resolution Protocol
      4. 23.3.4 Protocol Descriptions & Initialization
        1. 23.3.4.1 I2C Controller Mode
          1. 23.3.4.1.1 I2C Controller Initialization
          2. 23.3.4.1.2 I2C Controller Status
          3. 23.3.4.1.3 I2C Controller Receive Mode
          4. 23.3.4.1.4 I2C Controller Transmitter Mode
          5. 23.3.4.1.5 Controller Transaction Configurations
        2. 23.3.4.2 I2C Target Mode
          1. 23.3.4.2.1 I2C Target Initialization
          2. 23.3.4.2.2 I2C Target Status
          3. 23.3.4.2.3 I2C Target Receiver Mode
          4. 23.3.4.2.4 I2C Target Transmitter Mode
      5. 23.3.5 Reset Considerations
      6. 23.3.6 Initialization
      7. 23.3.7 Interrupt and Events Support
        1. 23.3.7.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 23.3.7.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      8. 23.3.8 Emulation Modes
    4. 23.4 UNICOMM I2C Registers
      1. 23.4.1 UNICOMMI2CC Registers
      2. 23.4.2 UNICOMMI2CT Registers
  26. 24UNICOMM-SPI
    1. 24.1 UNICOMM-SPI Overview
      1. 24.1.1 Purpose of the Peripheral
      2. 24.1.2 Features
      3. 24.1.3 Functional Block Diagram
      4. 24.1.4 External Connections and Signal Descriptions
    2. 24.2 SPI Operation
      1. 24.2.1  Clock Frequency Support
        1. 24.2.1.1 SPI Clock Generation
      2. 24.2.2  General Architecture
        1. 24.2.2.1 Chip Select and Command Handling
          1. 24.2.2.1.1 Chip Select Control
        2. 24.2.2.2 Command Data Control
        3. 24.2.2.3 Data Format
        4. 24.2.2.4 Delayed data sampling
        5. 24.2.2.5 DMA Operation
      3. 24.2.3  FIFO Operation
        1. 24.2.3.1 FIFO Size
        2. 24.2.3.2 FIFO Status bits
          1. 24.2.3.2.1 RIS.RX based on FIFO threshold settings
          2. 24.2.3.2.2 RIS.TX based on FIFO threshold settings
        3. 24.2.3.3 Clearing FIFO contents
        4. 24.2.3.4 Hardware monitors empty, full and overflow conditions
      4. 24.2.4  Suspend communication
        1. 24.2.4.1 SPI IDLE State Requirements
      5. 24.2.5  Internal Loopback Operation
      6. 24.2.6  Repeat Transfer mode
      7. 24.2.7  Receive Timeout
      8. 24.2.8  Line Timeout
      9. 24.2.9  Protocol Descriptions
        1. 24.2.9.1 Motorola SPI Frame Format
        2. 24.2.9.2 Texas Instruments Synchronous Serial Frame Format
      10. 24.2.10 Status Flags
      11. 24.2.11 Module configuration
      12. 24.2.12 Reset Considerations
      13. 24.2.13 Initialization
      14. 24.2.14 Interrupt and Events Support
        1. 24.2.14.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 24.2.14.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      15. 24.2.15 Emulation Modes
        1. 24.2.15.1 Graceful Halt
    3. 24.3 UNICOMMSPI Registers
  27. 25QSPI
    1. 25.1 QSPI Overview
      1. 25.1.1 Purpose of the Peripheral
      2. 25.1.2 Features
      3. 25.1.3 Functional Block Diagram
      4. 25.1.4 External Connections and Signal Descriptions
    2. 25.2 QSPI Operation
      1. 25.2.1 Clock Control
      2. 25.2.2 General Architecture
        1. 25.2.2.1 Chip Select Control
        2. 25.2.2.2 Data Format
        3. 25.2.2.3 Delayed data sampling
        4. 25.2.2.4 Loopback mode
        5. 25.2.2.5 FIFO Operation
        6. 25.2.2.6 DMA Operation
        7. 25.2.2.7 Lower Power Mode
      3. 25.2.3 Reset Considerations
      4. 25.2.4 Initialization
      5. 25.2.5 QSPI Controller Description
        1. 25.2.5.1 Configuration Frame Access
        2. 25.2.5.2 Status Frame Access
        3. 25.2.5.3 Data packing and unpacking
        4. 25.2.5.4 Data Frame Access
          1. 25.2.5.4.1 SSS mode (QSPIFORMAT = 1000)
          2. 25.2.5.4.2 SSD mode (QSPIFORMAT = 1001)
          3. 25.2.5.4.3 SDD mode (QSPIFORMAT = 1010)
          4. 25.2.5.4.4 SSQ mode (QSPIFORMAT = 1011)
          5. 25.2.5.4.5 SQQ mode (QSPIFORMAT = 1100)
          6. 25.2.5.4.6 QQQ mode (QSPIFORMAT = 1101)
      6. 25.2.6 Interrupt and Events Support
        1. 25.2.6.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 25.2.6.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      7. 25.2.7 Emulation Modes
    3. 25.3 QSPI Registers
  28. 26CAN-FD
    1. 26.1 MCAN Overview
      1. 26.1.1 MCAN Features
    2. 26.2 MCAN Environment
    3. 26.3 CAN Network Basics
    4. 26.4 MCAN Functional Description
      1. 26.4.1  Clock Setup
      2. 26.4.2  Module Clocking Requirements
      3. 26.4.3  Interrupt Requests
      4. 26.4.4  Operating Modes
        1. 26.4.4.1 Normal Operation
        2. 26.4.4.2 CAN Classic
        3. 26.4.4.3 CAN FD Operation
      5. 26.4.5  Software Initialization
      6. 26.4.6  Transmitter Delay Compensation
        1. 26.4.6.1 Description
        2. 26.4.6.2 Transmitter Delay Compensation Measurement
      7. 26.4.7  Restricted Operation Mode
      8. 26.4.8  Bus Monitoring Mode
      9. 26.4.9  Disabled Automatic Retransmission (DAR) Mode
        1. 26.4.9.1 Frame Transmission in DAR Mode
      10. 26.4.10 Clock Stop Mode
        1. 26.4.10.1 Suspend Mode
        2. 26.4.10.2 Wakeup Request
      11. 26.4.11 Test Modes
        1. 26.4.11.1 External Loop Back Mode
        2. 26.4.11.2 Internal Loop Back Mode
      12. 26.4.12 Timestamp Generation
        1. 26.4.12.1 External Timestamp Counter
      13. 26.4.13 Timeout Counter
      14. 26.4.14 Safety
        1. 26.4.14.1 MCAN ECC Wrapper
        2. 26.4.14.2 MCAN ECC Aggregator
          1. 26.4.14.2.1 MCAN ECC Aggregator Overview
          2. 26.4.14.2.2 MCAN ECC Aggregator Registers
        3. 26.4.14.3 Reads to ECC Control and Status Registers
        4. 26.4.14.4 ECC Interrupts
      15. 26.4.15 Tx Handling
        1. 26.4.15.1 Transmit Pause
        2. 26.4.15.2 Dedicated Tx Buffers
        3. 26.4.15.3 Tx FIFO
        4. 26.4.15.4 Tx Queue
        5. 26.4.15.5 Mixed Dedicated Tx Buffers/Tx FIFO
        6. 26.4.15.6 Mixed Dedicated Tx Buffers/Tx Queue
        7. 26.4.15.7 Transmit Cancellation
        8. 26.4.15.8 Tx Event Handling
        9. 26.4.15.9 FIFO Acknowledge Handling
      16. 26.4.16 Rx Handling
        1. 26.4.16.1 Acceptance Filtering
          1. 26.4.16.1.1 Range Filter
          2. 26.4.16.1.2 Filter for Specific IDs
          3. 26.4.16.1.3 Classic Bit Mask Filter
          4. 26.4.16.1.4 Standard Message ID Filtering
          5. 26.4.16.1.5 Extended Message ID Filtering
      17. 26.4.17 Rx FIFOs
        1. 26.4.17.1 Rx FIFO Blocking Mode
        2. 26.4.17.2 Rx FIFO Overwrite Mode
      18. 26.4.18 Dedicated Rx Buffers
        1. 26.4.18.1 Rx Buffer Handling
      19. 26.4.19 Message RAM
        1. 26.4.19.1 Message RAM Configuration
        2. 26.4.19.2 Rx Buffer and FIFO Element
        3. 26.4.19.3 Tx Buffer Element
        4. 26.4.19.4 Tx Event FIFO Element
        5. 26.4.19.5 Standard Message ID Filter Element
        6. 26.4.19.6 Extended Message ID Filter Element
    5. 26.5 MCAN Integration
    6. 26.6 Interrupt and Event Support
      1. 26.6.1 CPU Interrupt Event Publisher (CPU_INT)
    7. 26.7 MCAN Registers
  29. 27I2S/TDM
    1. 27.1 I2S/TDM Introduction
      1. 27.1.1 I2S/TDM features
    2. 27.2 I2S/TDM Operation
      1. 27.2.1  Functional Block Diagram
      2. 27.2.2  Modes of Operation
        1. 27.2.2.1 Controller Mode
        2. 27.2.2.2 Target Mode
      3. 27.2.3  Clock and Timing Control
      4. 27.2.4  Frame Synchronization
        1. 27.2.4.1 Frame and Word Length
        2. 27.2.4.2 Polarity
        3. 27.2.4.3 Data Delay (Offset)
      5. 27.2.5  Slot Mapping and Configuration
        1.       Data Direction Configuration
        2. 27.2.5.1 Channel Mapping in Memory
      6. 27.2.6  Serial Frame Format Examples
        1. 27.2.6.1 I2S Format
        2. 27.2.6.2 Right Justified Format
        3. 27.2.6.3 Left Justified Format
        4. 27.2.6.4 DSP Format
        5. 27.2.6.5 PCM Long Frame Format
        6. 27.2.6.6 TDM Classic Format
      7. 27.2.7  Initialization
      8. 27.2.8  Disabling I2S
      9. 27.2.9  Interrupts and Events Support
        1. 27.2.9.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 27.2.9.2 DMA Trigger Publisher (DMA_TRIG_RX, DMA_TRIG_TX)
      10. 27.2.10 Emulation Modes
    3. 27.3 I2S Registers
  30. 28Timers (TIMx)
    1. 28.1 TIMx Overview
      1. 28.1.1 TIMG Overview
        1. 28.1.1.1 TIMG Features
        2. 28.1.1.2 Functional Block Diagram
      2. 28.1.2 TIMA Overview
        1. 28.1.2.1 TIMA Features
        2. 28.1.2.2 Functional Block Diagram
      3. 28.1.3 TIMx Instance Configuration
    2. 28.2 TIMx Operation
      1. 28.2.1  Timer Counter
        1. 28.2.1.1 Clock Source Select and Prescaler
          1. 28.2.1.1.1 Internal Clock and Prescaler
          2. 28.2.1.1.2 External Signal Trigger
        2. 28.2.1.2 Repeat Counter (TIMA only)
      2. 28.2.2  Counting Mode Control
        1. 28.2.2.1 One-shot and Periodic Modes
        2. 28.2.2.2 Down Counting Mode
        3. 28.2.2.3 Up/Down Counting Mode
        4. 28.2.2.4 Up Counting Mode
        5. 28.2.2.5 Phase Load (TIMA only)
      3. 28.2.3  Capture/Compare Module
        1. 28.2.3.1 Capture Mode
          1. 28.2.3.1.1 Input Selection, Counter Conditions, and Inversion
            1. 28.2.3.1.1.1 CCP Input Edge Synchronization
            2. 28.2.3.1.1.2 CCP Input Pulse Conditions
            3. 28.2.3.1.1.3 Counter Control Operation
            4. 28.2.3.1.1.4 CCP Input Filtering
            5. 28.2.3.1.1.5 Input Selection
          2. 28.2.3.1.2 Use Cases
            1. 28.2.3.1.2.1 Edge Time Capture
            2. 28.2.3.1.2.2 Period Capture
            3. 28.2.3.1.2.3 Pulse Width Capture
            4. 28.2.3.1.2.4 Combined Pulse Width and Period Time
          3. 28.2.3.1.3 QEI Mode (TIMG with QEI support only)
            1. 28.2.3.1.3.1 QEI With 2-Signal
            2. 28.2.3.1.3.2 QEI With Index Input
            3. 28.2.3.1.3.3 QEI Error Detection
          4. 28.2.3.1.4 Hall Input Mode (TIMG with QEI support only)
        2. 28.2.3.2 Compare Mode
          1. 28.2.3.2.1 Edge Count
      4. 28.2.4  Shadow Load and Shadow Compare
        1. 28.2.4.1 Shadow Load (TIMG4-7, TIMA only)
        2. 28.2.4.2 Shadow Compare (TIMG4-7, TIMG12-13, TIMA only)
      5. 28.2.5  Output Generator
        1. 28.2.5.1 Configuration
        2. 28.2.5.2 Use Cases
          1. 28.2.5.2.1 Edge-Aligned PWM
          2. 28.2.5.2.2 Center-Aligned PWM
          3. 28.2.5.2.3 Asymmetric PWM (TIMA only)
          4. 28.2.5.2.4 Complementary PWM With Deadband Insertion (TIMA only)
        3. 28.2.5.3 Forced Output
      6. 28.2.6  Fault Handler (TIMA only)
        1. 28.2.6.1 Fault Input Conditioning
        2. 28.2.6.2 Fault Input Sources
        3. 28.2.6.3 Counter Behavior With Fault Conditions
        4. 28.2.6.4 Output Behavior With Fault Conditions
      7. 28.2.7  Synchronization With Cross Trigger
        1. 28.2.7.1 Main Timer Cross Trigger Configuration
        2. 28.2.7.2 Secondary Timer Cross Trigger Configuration
      8. 28.2.8  Low Power Operation
      9. 28.2.9  Interrupt and Event Support
        1. 28.2.9.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 28.2.9.2 Generic Event Publisher and Subscriber (GEN_EVENT0 and GEN_EVENT1)
        3. 28.2.9.3 Generic Subscriber Event Example (COMP to TIMx)
      10. 28.2.10 Debug Handler (TIMA Only)
    3. 28.3 TIMx Registers
  31. 29Low Frequency Subsystem (LFSS)
    1. 29.1  Overview
    2. 29.2  Clock System
    3. 29.3  LFSS Reset Using VBAT
    4. 29.4  Power Domains and Supply Detection
      1. 29.4.1 Startup When VBAT Powers on First
      2. 29.4.2 Startup when VDD powers on first
      3. 29.4.3 Behavior When VDD is Lost
      4. 29.4.4 Behavior when VBAT is lost
      5. 29.4.5 Behavior when the device goes into SHUTDOWN mode
      6. 29.4.6 Supercapacitor Charging Circuit
    5. 29.5  Real Time Counter (RTC_x)
    6. 29.6  Independent Watchdog Timer (IWDT)
    7. 29.7  Tamper Input and Output
      1. 29.7.1 IOMUX Mode
      2. 29.7.2 Tamper Mode
        1. 29.7.2.1 Tamper Event Detection
        2. 29.7.2.2 Timestamp Event Output
        3. 29.7.2.3 Heartbeat Generator
        4. 29.7.2.4 RTC Clock Output
    8. 29.8  Scratchpad Memory
    9. 29.9  Lock Function of RTC, TIO, and IWDT
    10. 29.10 LFSS Registers
  32. 30RTC
    1. 30.1 Overview
      1. 30.1.1 RTC Instances
    2. 30.2 Basic Operation
    3. 30.3 Configuration
      1. 30.3.1  Clocking
      2. 30.3.2  Reading and Writing to RTC Peripheral Registers
      3. 30.3.3  Binary vs. BCD
      4. 30.3.4  Leap Year Handling
      5. 30.3.5  Calendar Alarm Configuration
      6. 30.3.6  Interval Alarm Configuration
      7. 30.3.7  Periodic Alarm Configuration
      8. 30.3.8  Calibration
        1. 30.3.8.1 Crystal Offset Error
          1. 30.3.8.1.1 Offset Error Correction Mechanism
        2. 30.3.8.2 Crystal Temperature Error
          1. 30.3.8.2.1 Temperature Drift Correction Mechanism
      9. 30.3.9  RTC Prescaler Extension
      10. 30.3.10 RTC Timestamp Capture
      11. 30.3.11 RTC Events
        1. 30.3.11.1 CPU Interrupt Event Publisher (CPU_INT)
        2. 30.3.11.2 Generic Event Publisher (GEN_EVENT)
    4. 30.4 RTC Registers
  33. 31IWDT
    1. 31.1 865
    2. 31.2 IWDT Clock Configuration
    3. 31.3 IWDT Period Selection
    4. 31.4 Debug Behavior of the IWDT
    5. 31.5 IWDT Registers
  34. 32Window Watchdog Timer (WWDT)
    1. 32.1 WWDT Overview
      1. 32.1.1 Watchdog Mode
      2. 32.1.2 Interval Timer Mode
    2. 32.2 WWDT Operation
      1. 32.2.1 Mode Selection
      2. 32.2.2 Clock Configuration
      3. 32.2.3 Low-Power Mode Behavior
      4. 32.2.4 Debug Behavior
      5. 32.2.5 WWDT Events
        1. 32.2.5.1 CPU Interrupt Event Publisher (CPU_INT)
    3. 32.3 WWDT Registers
  35. 33Debug
    1. 33.1 DEBUGSS Overview
      1. 33.1.1 Debug Interconnect
      2. 33.1.2 Physical Interface
      3. 33.1.3 Debug Access Ports
    2. 33.2 DEBUGSS Operation
      1. 33.2.1 Debug Features
        1. 33.2.1.1 Processor Debug
          1. 33.2.1.1.1 Breakpoint Unit (BPU)
          2. 33.2.1.1.2 Data Watchpoint and Trace Unit (DWT)
          3. 33.2.1.1.3 Processor Trace (MTB)
        2. 33.2.1.2 Peripheral Debug
      2. 33.2.2 Behavior in Low Power Modes
      3. 33.2.3 Restricting Debug Access
      4. 33.2.4 Mailbox (DSSM)
        1. 33.2.4.1 DSSM Events
          1. 33.2.4.1.1 CPU Interrupt Event (CPU_INT)
        2. 33.2.4.2 Reference
    3. 33.3 DEBUGSS Registers
  36. 34Revision History

3.3.1.1 Nested Vectored Interrupt Controller (NVIC)

The nested vectored interrupt controller (NVIC) is an industry-standard Arm component which interfaces peripheral interrupts (which are external to the processor) into the CPU. The NVIC supports connection of up to 480 native peripheral interrupt sources. For information on which peripheral is being mapped please see the corresponding data sheet.

The NVIC is configured through memory-mapped registers in the system private peripheral bus (PPB) region. See Arm Cortex-M33 NVIC Registers for the list of NVIC registers. The software development kit (SDK) provided with the devices supports the standard Arm Cortex Microcontroller Software Interface Standard (CMSIS) register access definitions for the NVIC. Application software must use 32-bit aligned, word-size transactions when accessing any NVIC register.

In addition to interfacing peripheral interrupts to the processor, the NVIC also supports programmable priority for each interrupt.

Enabling and Disabling Interrupts

Peripheral interrupt enables can be read, set, and cleared through the interrupt set-enable (ISER) and interrupt clear-enable (ICER) registers in the NVIC. Each ICER and ISER register supports 32 different interrupts. The interrupts are mapped to the ISER and ICER registers with interrupt zero in the BIT0 position (LSB) and interrupt 31 in the BIT31 position (MSB) of each register. For example, SETENA[m] in NVIC_ISERn, allows interrupt 32n + m to be accessed.

To enable an interrupt, set the corresponding enable bit in the ISER register. Writing a '0' to ISER has no effect. It is possible to read the ISER or ICER registers to determine which interrupts are enabled. Upon a read, a '1' indicates that an interrupt is enabled; a '0' indicates disabled. To disable an interrupt, set the corresponding clear enable bit in the ICER register. Writing a '0' to ICER has no effect.

Note: In addition to enabling a peripheral interrupt at the NVIC, it is generally necessary to also configure the interrupt configuration of the corresponding peripheral as well. Most peripherals have multiple interrupt sources, which are merged together in the peripheral to source a single NVIC interrupt. Masking of individual peripheral interrupts is done within the peripheral's interrupt management registers. When an interrupt happens the user can typically read the corresponding peripheral's IIDX regisister for details on the interrupt source. For peripheral interrupt handling please refer to the specific peripheral chapter for details on the IIDX register.

In the event that an interrupt is disabled in the NVIC, if the interrupt is asserted by the corresponding peripheral then the NVIC interrupt will go to a pending state but the processor is not interrupted. If an interrupt is disabled when in an active state (when a handler is running) it will remain active until the exception handler returns or a reset occurs, but no further activations will happen.

Note: If a peripheral asserts an interrupt to the NVIC, but that peripheral's interrupt in the NVIC is disabled, the device may remain in a higher power mode than expected as the wake-up controller (WUC) is holding an event for the processor. To prevent this situation, ensure peripheral interrupts are masked at the peripheral directly, versus only masking interrupts at the NVIC.

Setting and Clearing Pending Interrupt Status

Pending interrupt status can be read, set, and cleared through the interrupt set-pending (ISPR) and interrupt clear-pending (ICPR) registers in the NVIC. Each ISPR and ICPR register supports 32 interrupts, with interrupt zero in the BIT0 position (LSB) and interrupt 31 in the BIT31 position (MSB) of each register. For example, SETPEND[m] in NVIC_ISPRn, allows interrupt 32n + m to be accessed.

To read if an interrupt is pending, read either the ISPR or the ICPR. Upon a read, a '1' indicates that an interrupt is pending; a '0' indicates not pending. To set an interrupt to a pending state through software, set the corresponding bit in the ISPR register. Writing a '0' to ISPR has no effect. To clear an interrupt pending state, set the corresponding bit in the ICPR register. Writing a '0' to ICPR has no effect. Note that if a peripheral interrupt condition is still present, the pending state will be set again by hardware even if it is cleared.

Setting Interrupt Priority

Interrupts on the NVIC have programmable priority. There are 64 priority levels possible. Priority is set by programming the IPR registers in the NVIC. Each priority field is 8 bits in length, and the priority for 4 interrupts is configured per 32-bit IPR register. The Arm Cortex-M33 only implements the most significant 6 bits of each 8-bit priority field (giving the 64 priority levels). Lower priority values have higher priority. System exceptions (reset, NMI, hard fault) have fixed priorities of -3, -2, and -1, respectively. As such, these exceptions always have higher priority than peripheral interrupts. Peripheral interrupt priorities are programmable as 0, 64, 128, or 192, with 0 being highest priority and 192 being lowest priority.

If the processor is currently handling an exception, it can only be preempted by a higher priority exception. In the event that there are multiple exceptions in a pending state which all have the same priority level assigned, the exception with the lowest exception number is taken first.

Note: Application software must not change the priority of an interrupt while the corresponding interrupt is either active (being handled) or enabled. Doing so can result in unpredictable behavior.
Table 3-2 Arm Cortex-M33 NVIC Registers
Address Register CMSIS Description
0xE000.E100 - 0xE000.E13C NVIC_ISER0 - NVIC_ISER15 NVIC->ISER[0] - NVIC->ISER[15] Interrupt set-enable register
0xE000.E180 - 0xE000.E1BC NVIC_ICER0 - NVIC_ICER15 NVIC->ICER[0] - NVIC->ICER[15] Interrupt clear-enable register
0xE000.E200 - 0xE000.E23C NVIC_ISPR0 - NVIC_ISPR15 NVIC->ISPR[0] - NVIC->ISPR[15] Interrupt set-pending register
0xE000.E280 - 0xE000.E2BC NVIC_ICPR0 - NVIC_ICPR15 NVIC->ICPR[0] - NVIC->ICPR[15] Interrupt clear-pending register
0xE000.E300 - 0xE000.E33C NVIC_IABR0 - NVIC_IABR15 NVIC->IABR[0] - NVIC->IABR[15] Interrupt active bit register
0xE000.E400 - 0xE000.E5DC NVIC_IPR0 - NVIC_IPR119 NVIC->IPR[0] - NVIC->IPR[119] Interrupt priority register (0 - 3) - Interrupt priority register (115 - 119)