SWRU543B January   2019  – June 2025 CC3230S , CC3230SF , CC3235MODS , CC3235MODSF , CC3235S , CC3235SF

 

  1.   1
  2.   Read This First
    1.     Audience
    2.     About This Manual
    3.     Register Bit Conventions
    4.     Glossary
    5.     Related Documentation
    6.     Community Resources
    7.     Trademarks
  3. 1 Architecture Overview
    1. 1.1 Introduction
    2. 1.2 Architecture Overview
    3. 1.3 Functional Overview
      1. 1.3.1  Processor Core
        1. 1.3.1.1 Arm® Cortex®-M4 Processor Core
        2. 1.3.1.2 System Timer (SysTick)
        3. 1.3.1.3 Nested Vector Interrupt Controller (NVIC)
        4. 1.3.1.4 System Control Block
      2. 1.3.2  Memory
        1. 1.3.2.1 On-Chip SRAM
        2. 1.3.2.2 ROM
        3. 1.3.2.3 Flash Memory
      3. 1.3.3  Micro-Direct Memory Access Controller (µDMA)
      4. 1.3.4  General-Purpose Timer (GPT)
      5. 1.3.5  Watchdog Timer (WDT)
      6. 1.3.6  Multichannel Audio Serial Port (McASP)
      7. 1.3.7  Serial Peripheral Interface (SPI)
      8. 1.3.8  Inter-Integrated Circuit (I2C) Interface
      9. 1.3.9  Universal Asynchronous Receiver/Transmitter (UART)
      10. 1.3.10 General-Purpose Input/Output (GPIO)
      11. 1.3.11 Analog-to-Digital Converter (ADC)
      12. 1.3.12 SD Card Host
      13. 1.3.13 Parallel Camera Interface
      14. 1.3.14 Debug Interface
      15. 1.3.15 Hardware Cryptography Accelerator
      16. 1.3.16 Clock, Reset, and Power Management
      17. 1.3.17 SimpleLink™ Subsystem
      18. 1.3.18 I/O Pads and Pin Multiplexing
  4. 2 Cortex®-M4 Processor
    1. 2.1 Overview
      1. 2.1.1 Block Diagram
      2. 2.1.2 System-Level Interface
      3. 2.1.3 Integrated Configurable Debug
      4. 2.1.4 Trace Port Interface Unit (TPIU)
      5. 2.1.5 Cortex®-M4 System Component Details
    2. 2.2 Functional Description
      1. 2.2.1 Programming Model
        1. 2.2.1.1 Processor Mode and Privilege Levels for Software Execution
        2. 2.2.1.2 Stacks
      2. 2.2.2 Register Description
        1. 2.2.2.1 Register Map
        2. 2.2.2.2 Register Descriptions
          1. 2.2.2.2.1 Stack Pointer (SP)
          2. 2.2.2.2.2 Link Register (LR)
          3. 2.2.2.2.3 Program Counter (PC)
          4. 2.2.2.2.4 Program Status Register (PSR)
          5. 2.2.2.2.5 Priority Mask Register (PRIMASK)
          6. 2.2.2.2.6 Fault Mask Register (FAULTMASK)
          7. 2.2.2.2.7 Base Priority Mask Register (BASEPRI)
          8. 2.2.2.2.8 Control Register (CONTROL)
        3. 2.2.2.3 Exceptions and Interrupts
        4. 2.2.2.4 Data Types
      3. 2.2.3 Memory Model
        1. 2.2.3.1 Bit-Banding
          1. 2.2.3.1.1 Directly Accessing an Alias Region
          2. 2.2.3.1.2 Directly Accessing a Bit-Band Region
        2. 2.2.3.2 Data Storage
        3. 2.2.3.3 Synchronization Primitives
      4. 2.2.4 Exception Model
        1. 2.2.4.1 Exception States
        2. 2.2.4.2 Exception Types
        3. 2.2.4.3 Exception Handlers
        4. 2.2.4.4 Vector Table
        5. 2.2.4.5 Exception Priorities
        6. 2.2.4.6 Interrupt Priority Grouping
        7. 2.2.4.7 Exception Entry and Return
          1. 2.2.4.7.1 Exception Entry
      5. 2.2.5 Fault Handling
        1. 2.2.5.1 Fault Types
        2. 2.2.5.2 Fault Escalation and Hard Faults
        3. 2.2.5.3 Fault Status Registers and Fault Address Registers
        4. 2.2.5.4 Lockup State
      6. 2.2.6 Power Management
      7. 2.2.7 Instruction Set Summary
  5. 3 Cortex®-M4 Peripherals
    1. 3.1 Overview
    2. 3.2 Functional Description
      1. 3.2.1 System Timer (SysTick)
      2. 3.2.2 Nested Vectored Interrupt Controller (NVIC)
        1. 3.2.2.1 Level-Sensitive and Pulse Interrupts
        2. 3.2.2.2 Hardware and Software Control of Interrupts
      3. 3.2.3 System Control Block (SCB)
    3. 3.3 Register Map
      1. 3.3.1 Cortex Registers
  6. 4 Direct Memory Access (DMA)
    1. 4.1 Overview
    2. 4.2 Functional Description
      1. 4.2.1 Channel Assignment
      2. 4.2.2 Priority
      3. 4.2.3 Arbitration Size
      4. 4.2.4 Channel Configuration
      5. 4.2.5 Transfer Mode
        1. 4.2.5.1 Stop Mode
        2. 4.2.5.2 Basic Mode
        3. 4.2.5.3 Auto Mode
        4. 4.2.5.4 Ping-Pong Mode
        5. 4.2.5.5 Memory Scatter-Gather Mode
        6. 4.2.5.6 Peripheral Scatter-Gather Mode
      6. 4.2.6 Transfer Size and Increment
      7. 4.2.7 Peripheral Interface
        1. 4.2.7.1 FIFO Peripherals
        2. 4.2.7.2 Trigger Peripherals
        3. 4.2.7.3 Software Request
      8. 4.2.8 Interrupts and Errors
    3. 4.3 Register Description
      1. 4.3.1 DMA Register Map
      2. 4.3.2 µDMA Channel Control Structure
      3. 4.3.3 DMA Registers
      4. 4.3.4 DMA_(OFFSET_FROM_DMA_BASE_ADDRESS) Registers
  7. 5 General-Purpose Input/Outputs (GPIOs)
    1. 5.1 Overview
    2. 5.2 Functional Description
      1. 5.2.1 Data Control
        1. 5.2.1.1 Data Direction Operation
        2. 5.2.1.2 Data Register Operation
    3. 5.3 Interrupt Control
      1. 5.3.1 µDMA Trigger Source
    4. 5.4 Initialization and Configuration
    5. 5.5 GPIO Registers
  8. 6 Universal Asynchronous Receivers/Transmitters (UARTs)
    1. 6.1 Overview
      1. 6.1.1 Block Diagram
    2. 6.2 Functional Description
      1. 6.2.1 Transmit and Receive Logic
      2. 6.2.2 Baud-Rate Generation
      3. 6.2.3 Data Transmission
        1. 6.2.3.1 Flow Control
          1. 6.2.3.1.1 Hardware Flow Control (RTS/CTS)
          2. 6.2.3.1.2 Software Flow Control (Modem Status Interrupts)
        2. 6.2.3.2 FIFO Operation
        3. 6.2.3.3 Interrupts
        4. 6.2.3.4 LoopbackOperation
        5. 6.2.3.5 DMA Operation
      4. 6.2.4 Initialization and Configuration
    3. 6.3 UART Registers
  9. 7 Inter-Integrated Circuit (I2C) Interface
    1. 7.1 Overview
      1. 7.1.1 Block Diagram
      2. 7.1.2 Signal Description
    2. 7.2 Functional Description
      1. 7.2.1 I2C Bus Functional Overview
        1. 7.2.1.1 START and STOP Conditions
        2. 7.2.1.2 Data Format With 7-Bit Address
        3. 7.2.1.3 Data Validity
        4. 7.2.1.4 Acknowledge
        5. 7.2.1.5 Repeated Start
        6. 7.2.1.6 Clock Low Time-out (CLTO)
        7. 7.2.1.7 Dual Address
        8. 7.2.1.8 Arbitration
      2. 7.2.2 Supported Speed Modes
        1. 7.2.2.1 Standard and Fast Modes
      3. 7.2.3 Interrupts
      4. 7.2.4 Loopback Operation
      5. 7.2.5 FIFO and µDMA Operation
        1. 7.2.5.1 Master Module Burst Mode
          1. 7.2.5.1.1 Master Module µDMA Functionality
          2. 7.2.5.1.2 Slave Module
      6. 7.2.6 Command Sequence Flow Charts
        1. 7.2.6.1 I2C Master Command Sequences
        2. 7.2.6.2 I2C Slave Command Sequences
      7. 7.2.7 Initialization and Configuration
    3. 7.3 I2C Registers
  10. 8 SPI (Serial Peripheral Interface)
    1. 8.1 Overview
      1. 8.1.1 Features
    2. 8.2 Functional Description
      1. 8.2.1 SPI
      2. 8.2.2 SPI Transmission
        1. 8.2.2.1 Two Data Pins Interface Mode
        2. 8.2.2.2 Transfer Formats
          1. 8.2.2.2.1 Programmable Word Length
          2. 8.2.2.2.2 Programmable SPI Enable (SPIEN)
          3. 8.2.2.2.3 Programmable SPI Clock (SPICLK)
          4. 8.2.2.2.4 Bit Rate
          5. 8.2.2.2.5 Polarity and Phase
            1. 8.2.2.2.5.1 Transfer Format With PHA = 0
            2. 8.2.2.2.5.2 Transfer Format With PHA = 1
      3. 8.2.3 Master Mode
        1. 8.2.3.1 Interrupt Events in Master Mode
          1. 8.2.3.1.1 TX_empty
          2. 8.2.3.1.2 TX_underflow
          3. 8.2.3.1.3 RX_ full
          4. 8.2.3.1.4 End-of-Word Count
        2. 8.2.3.2 Master Transmit and Receive Mode
        3. 8.2.3.3 SPI Enable Control in Master Mode
          1. 8.2.3.3.1 Keep SPIEN Active Mode (Force SPIEN)
        4. 8.2.3.4 Clock Ratio Granularity
          1. 8.2.3.4.1 FIFO Buffer Management
            1. 8.2.3.4.1.1 Split FIFO
            2. 8.2.3.4.1.2 Buffer Almost Full
            3. 8.2.3.4.1.3 Buffer Almost Empty
            4. 8.2.3.4.1.4 End of Transfer Management
            5. 8.2.3.4.1.5 3- or 4-Pin Mode
      4. 8.2.4 Slave Mode
        1. 8.2.4.1 Interrupts Events in Slave Mode
          1. 8.2.4.1.1 TX_empty
          2. 8.2.4.1.2 TX_underflow
          3. 8.2.4.1.3 RX_ full
          4. 8.2.4.1.4 RX_overflow
          5. 8.2.4.1.5 End-of-Word Count
        2. 8.2.4.2 Slave Transmit and Receive Mode
      5. 8.2.5 Interrupts
        1. 8.2.5.1 Interrupt-Driven Operation
        2. 8.2.5.2 Polling
      6. 8.2.6 DMA Requests
        1. 8.2.6.1 FIFO Buffer Enabled
      7. 8.2.7 Reset
    3. 8.3 Initialization and Configuration
      1. 8.3.1 Basic Initialization
      2. 8.3.2 Master Mode Operation Without Interrupt (Polling)
      3. 8.3.3 Slave Mode Operation With Interrupt
      4. 8.3.4 Generic Interrupt Handler Implementation
    4. 8.4 Access to Data Registers
    5. 8.5 Module Initialization
      1. 8.5.1 Common Transfer Sequence
      2. 8.5.2 End-of-Transfer Sequences
      3. 8.5.3 FIFO Mode
        1. 8.5.3.1 Common Transfer Sequence
        2. 8.5.3.2 Transmit Receive With Word Count
        3. 8.5.3.3 Transmit Receive Without Word Count
    6. 8.6 SPI Registers
  11. 9 General-Purpose Timers
    1. 9.1 Overview
    2. 9.2 Block Diagram
    3. 9.3 Functional Description
      1. 9.3.1 GPTM Reset Conditions
      2. 9.3.2 Timer Modes
        1. 9.3.2.1 One-Shot or Periodic Timer Mode
        2. 9.3.2.2 Input Edge-Count Mode
        3. 9.3.2.3 Input Edge-Time Mode
        4. 9.3.2.4 PWM Mode
      3. 9.3.3 DMA Operation
      4. 9.3.4 Accessing Concatenated 16/32-Bit GPTM Register Values
    4. 9.4 Initialization and Configuration
      1. 9.4.1 One-Shot and Periodic Timer Mode
      2. 9.4.2 Input Edge-Count Mode
      3. 9.4.3 Input Edge-Time Mode
      4. 9.4.4 PWM Mode
    5. 9.5 Timer Registers
  12. 10Watchdog Timer
    1. 10.1 Overview
      1. 10.1.1 Block Diagram
    2. 10.2 Functional Description
      1. 10.2.1 Initialization and Configuration
    3. 10.3 WATCHDOG Registers
    4. 10.4 MCU Watchdog Controller Usage Caveats
      1. 10.4.1 System Watchdog
      2. 10.4.2 System Watchdog Recovery Sequence
  13. 11SD Host Controller Interface
    1. 11.1 Overview
    2. 11.2 SD Host Features
    3. 11.3 1-Bit SD Interface
      1. 11.3.1 Clock and Reset Management
    4. 11.4 Initialization and Configuration Using Peripheral APIs
      1. 11.4.1 Basic Initialization and Configuration
      2. 11.4.2 Sending Command
      3. 11.4.3 Card Detection and Initialization
      4. 11.4.4 Block Read
      5. 11.4.5 Block Write
    5. 11.5 Performance and Testing
    6. 11.6 Peripheral Library APIs
    7. 11.7 SD-HOST Registers
  14. 12Inter-Integrated Sound (I2S) Multichannel Audio Serial Port
    1. 12.1 Overview
      1. 12.1.1 I2S Format
    2. 12.2 Functional Description
    3. 12.3 Programming Model
      1. 12.3.1 Clock and Reset Management
      2. 12.3.2 I2S Data Port Interface
      3. 12.3.3 Initialization and Configuration
    4. 12.4 Peripheral Library APIs for I2S Configuration
      1. 12.4.1 Basic APIs for Enabling and Configuring the Interface
        1. 12.4.1.1 void I2SDisable (unsigned long ulBase)
        2. 12.4.1.2 void I2SEnable (unsigned long ulBase, unsigned long ulMode)
        3. 12.4.1.3 void I2SSerializerConfig (unsigned long ulBase, unsigned long ulDataLine, unsigned long ulSerMode, unsigned long ulInActState)
        4. 12.4.1.4 void I2SConfigSetExpClk (unsigned long ulBase, unsigned long ulI2SClk, unsigned long ulBitClk, unsigned long ulConfig)
      2. 12.4.2 APIs for Data Access if DMA is Not Used
        1. 12.4.2.1 void I2SDataGet (unsigned long ulBase, unsigned long ulDataLine, unsigned long * pulData)
        2. 12.4.2.2 long I2SDataGetNonBlocking (unsigned long ulBase, unsigned long ulDataLine, unsigned long * pulData)
        3. 12.4.2.3 void I2SDataPut (unsigned long ulBase, unsigned long ulDataLine, unsigned long ulData)
        4. 12.4.2.4 void I2SDataPut (unsigned long ulBase, unsigned long ulDataLine, unsigned long ulData)
      3. 12.4.3 APIs for Setting Up, Handling Interrupts, or Getting Status from I2S Peripheral
        1. 12.4.3.1 void I2SIntRegister (unsigned long ulBase, void(*)(void) pfnHandler)
        2. 12.4.3.2 void I2SIntEnable (unsigned long ulBase, unsigned long ulIntFlags)
        3. 12.4.3.3 void I2SIntDisable (unsigned long ulBase, unsigned long ulIntFlags)
        4. 12.4.3.4 unsigned long I2SIntStatus (unsigned long ulBase)
        5. 12.4.3.5 void I2SIntUnregister (unsigned long ulBase)
        6. 12.4.3.6 void I2SIntClear (unsigned long ulBase, unsigned long ulStatFlags)
        7. 12.4.3.7 Values that can be Passed to I2SIntEnable() and I2SIntDisable() as the ulIntFlags Parameter
        8. 12.4.3.8 Values that can be Passed to I2SIntClear() as the ulStatFlags Parameter and Returned from I2SIntStatus()
      4. 12.4.4 APIs to Control FIFO Structures Associated With I2S Peripheral
        1. 12.4.4.1 void I2SRxFIFODisable (unsigned long ulBase)
        2. 12.4.4.2 void I2SRxFIFOEnable (unsigned long ulBase, unsigned long ulRxLevel, unsigned long ulWordsPerTransfer)
        3. 12.4.4.3 unsigned long I2SRxFIFOStatusGet (unsigned long ulBase)
        4. 12.4.4.4 void I2STxFIFODisable (unsigned long ulBase)
        5. 12.4.4.5 void I2STxFIFOEnable (unsigned long ulBase, unsigned long ulTxLevel, unsigned long ulWordsPerTransfer)
        6. 12.4.4.6 unsigned long I2STxFIFOStatusGet (unsigned long ulBase)
    5. 12.5 I2S Registers
  15. 13Analog-to-Digital Converter (ADC)
    1. 13.1 Overview
    2. 13.2 Key Features
    3. 13.3 ADC Register Mapping
    4. 13.4 ADC_MODULE Registers
    5. 13.5 Initialization and Configuration
    6. 13.6 Peripheral Library APIs for ADC Operation
      1. 13.6.1 Overview
      2. 13.6.2 Configuring the ADC Channels
      3. 13.6.3 Basic APIs for Enabling and Configuring the Interface
        1. 13.6.3.1 void ADCEnable (unsigned long ulBase)
        2. 13.6.3.2 void ADCDisable (unsigned long ulBase)
        3. 13.6.3.3 void ADCChannelEnable (unsigned long ulBase, unsigned long ulChannel)
        4. 13.6.3.4 void ADCChannelDisable (unsigned long ulBase, unsigned long ulChannel)
      4. 13.6.4 APIs for Data Transfer [Direct Access to FIFO and DMA Setup]
        1. 13.6.4.1 unsigned char ADCFIFOLvlGet (unsigned long ulBase, unsigned long ulChannel)
        2. 13.6.4.2 unsigned long ADCFIFORead (unsigned long ulBase, unsigned long ulChannel)
        3. 13.6.4.3 void ADCDMAEnable (unsigned long ulBase, unsigned long ulChannel)
        4. 13.6.4.4 void ADCDMADisable (unsigned long ulBase, unsigned long ulChannel)
      5. 13.6.5 APIs for Interrupt Usage
        1. 13.6.5.1 void ADCIntEnable (unsigned long ulBase, unsigned long ulChannel, unsigned long ulIntFlags)
        2. 13.6.5.2 void ADCIntDisable (unsigned long ulBase, unsigned long ulChannel, unsigned long ulIntFlags)
        3. 13.6.5.3 void ADCIntRegister (unsigned long ulBase, unsigned long ulChannel, void(*)(void) pfnHandler)
        4. 13.6.5.4 void ADCIntUnregister (unsigned long ulBase, unsigned long ulChannel)
        5. 13.6.5.5 unsigned long ADCIntStatus (unsigned long ulBase, unsigned long ulChannel)
        6. 13.6.5.6 void ADCIntClear (unsigned long ulBase, unsigned long ulChannel, unsigned long ulIntFlags)
      6. 13.6.6 APIs for Setting Up ADC Timer for Time-Stamping the Samples
        1. 13.6.6.1 void ADCTimerConfig (unsigned long ulBase, unsigned long ulValue)
        2. 13.6.6.2 void ADCTimerDisable (unsigned long ulBase)
        3. 13.6.6.3 void ADCTimerEnable (unsigned long ulBase)
        4. 13.6.6.4 void ADCTimerReset (unsigned long ulBase)
        5. 13.6.6.5 unsigned long ADCTimerValueGet (unsigned long ulBase)
  16. 14Parallel Camera Interface Module
    1. 14.1 Overview
    2. 14.2 Image Sensor Interface
    3. 14.3 Functional Description
      1. 14.3.1 Modes of Operation
      2. 14.3.2 FIFO Buffer
      3. 14.3.3 Reset
      4. 14.3.4 Clock Generation
      5. 14.3.5 Interrupt Generation
      6. 14.3.6 DMA Interface
    4. 14.4 Programming Model
      1. 14.4.1 Camera Core Reset
      2. 14.4.2 Enable the Picture Acquisition
      3. 14.4.3 Disable the Picture Acquisition
    5. 14.5 Interrupt Handling
      1. 14.5.1 FIFO_OF_IRQ (FIFO Overflow)
      2. 14.5.2 FIFO_UF_IRQ (FIFO Underflow)
    6. 14.6 Camera Registers
    7. 14.7 Peripheral Library APIs
    8. 14.8 Developer’s Guide
      1. 14.8.1 Using Peripheral Driver APIs for Capturing an Image
      2. 14.8.2 Using Peripheral Driver APIs for Communicating With Image Sensors
  17. 15Power, Reset, and Clock Management
    1. 15.1 Overview
      1. 15.1.1 Power Management Unit (PMU)
      2. 15.1.2 VBAT Wide-Voltage Connection
      3. 15.1.3 Supply Brownout and Blackout
      4. 15.1.4 Application Processor Power Modes
    2. 15.2 Power Management Control Architecture
      1. 15.2.1 Global Power-Reset-Clock Manager (GPRCM)
      2. 15.2.2 Application Reset-Clock Manager (ARCM)
    3. 15.3 PRCM APIs
      1. 15.3.1  MCU Initialization
      2. 15.3.2  Reset Control
      3. 15.3.3  Peripheral Reset
      4. 15.3.4  Reset Cause
      5. 15.3.5  Clock Control
      6. 15.3.6  Low-Power Modes
      7. 15.3.7  Sleep (SLEEP)
      8. 15.3.8  Low-Power Deep Sleep (LPDS)
      9. 15.3.9  Hibernate (HIB)
      10. 15.3.10 Slow Clock Counter
    4. 15.4 Peripheral Macros
    5. 15.5 Power Management Framework
    6. 15.6 PRCM Registers
  18. 16I/O Pads and Pin Multiplexing
    1. 16.1 Overview
    2. 16.2 I/O Pad Electrical Specifications
    3. 16.3 Analog and Digital Pin Multiplexing
    4. 16.4 Special Analog/Digital Pins
      1. 16.4.1 Pins 45 and 52
      2. 16.4.2 Pins 29 and 30
      3. 16.4.3 Pins 57, 58, 59, and 60
    5. 16.5 Analog Mux Control Registers
    6. 16.6 Pins Available for Applications
    7. 16.7 Functional Pin Mux Configurations
    8. 16.8 Pin Mapping Recommendations
      1. 16.8.1 Pad Configuration Registers for Application Pins
        1. 16.8.1.1 Pad Mux and Electrical Configuration Register Bit Definitions
      2. 16.8.2 PAD Behavior During Reset and Hibernate
      3. 16.8.3 Control Architecture
      4. 16.8.4 CC32xx Pin-mux Examples
      5. 16.8.5 Wake on Pad
      6. 16.8.6 Sense on Power
  19. 17Advance Encryption Standard Accelerator (AES)
    1. 17.1 AES Overview
    2. 17.2 AES Functional Description
      1. 17.2.1 AES Block Diagram
        1. 17.2.1.1 Interfaces
        2. 17.2.1.2 AES Wide-Bus Engine
      2. 17.2.2 AES Algorithm
      3. 17.2.3 AES Operating Modes
        1. 17.2.3.1 Supported Modes of Operation
        2. 17.2.3.2 Extended and Combined Modes of Operations
      4. 17.2.4 Hardware Requests
    3. 17.3 AES Module Programming Guide
      1. 17.3.1 AES Low-Level Programming Models
        1. 17.3.1.1 Global Initialization
        2. 17.3.1.2 Initialization Subsequence
        3. 17.3.1.3 Operational Modes Configuration
        4. 17.3.1.4 AES Events Servicing
    4. 17.4 AES Registers
  20. 18Data Encryption Standard Accelerator (DES)
    1. 18.1 DES Functional Description
    2. 18.2 DES Block Diagram
      1. 18.2.1 µDMA Control
      2. 18.2.2 Interrupt Control
      3. 18.2.3 Register Interface
      4. 18.2.4 DES Enginer
        1. 18.2.4.1 Mode Control FSM
        2. 18.2.4.2 DES Feedback Mode Block
        3. 18.2.4.3 DES Cipher Core
    3. 18.3 DES-Supported Modes of Operation
      1. 18.3.1 ECB Feedback Mode
        1. 18.3.1.1 CBC Feedback Mode
        2. 18.3.1.2 CFB Feedback Mode
    4. 18.4 DES Module Programming Guide – Low-Level Programming Models
      1. 18.4.1 Surrounding Modules Global Initialization
        1. 18.4.1.1 Main Sequence – DES Global Initialization
        2. 18.4.1.2 Subsequence – Configure the DES Algorithm Type
        3. 18.4.1.3 Subsequence – Configure the 3DES Algorithm Type
      2. 18.4.2 Operational Modes Configuration
        1. 18.4.2.1 Main Sequence – DES Polling Mode
        2. 18.4.2.2 DES Interrupt Mode
        3. 18.4.2.3 DES Interrupt DMA Mode
      3. 18.4.3 DES Events Servicing
        1. 18.4.3.1 Interrupt Servicing
        2. 18.4.3.2 Context Input Event Servicing
    5. 18.5 DES Registers
  21. 19SHA/MD5 Accelerator
    1. 19.1 SHA/MD5 Functional Description
      1. 19.1.1 SHA/MD5 Block Diagram
        1. 19.1.1.1 Configuration Registers
        2. 19.1.1.2 Hash/HMAC Engine
        3. 19.1.1.3 Hash Core Control
        4. 19.1.1.4 Host Interface Bank
      2. 19.1.2 µDMA and Interrupt Requests
      3. 19.1.3 Operation Description
        1. 19.1.3.1 SHA Mode
          1. 19.1.3.1.1 Starting a New Hash
          2. 19.1.3.1.2 Outer Digest Registers
          3. 19.1.3.1.3 Inner Digest Registers
          4. 19.1.3.1.4 Closing a Hash
        2. 19.1.3.2 MD5 Mode
          1. 19.1.3.2.1 Starting a New Hash
          2. 19.1.3.2.2 Closing a Hash
        3. 19.1.3.3 Generating a Software Interrupt
      4. 19.1.4 SHA/MD5 Programming Guide
        1. 19.1.4.1 Global Initialization
          1. 19.1.4.1.1 Surrounding Modules Global Initialization
          2. 19.1.4.1.2 Starting a New HMAC using the SHA-1 Hash Function and HMAC Key Processing
          3. 19.1.4.1.3 Subsequence - Continuing a Prior HMAC Using the SHA-1 Hash Function
          4. 19.1.4.1.4 Subsequence - Hashing a Key Bigger than 512 Bits with the SHA-1 Hash Function
          5. 19.1.4.1.5 Operational Modes Configuration
          6. 19.1.4.1.6 SHA/MD5 Event Servicing
            1. 19.1.4.1.6.1 Interrupt Servicing
    2. 19.2 SHA-MD5 Registers
  22. 20Cyclical Redundancy Check (CRC)
    1. 20.1 Functional Description
      1. 20.1.1 CRC Support
        1. 20.1.1.1 CRC Checksum Engine
        2. 20.1.1.2 Data Size
        3. 20.1.1.3 Endian Configuration
    2. 20.2 Initialization and Configuration
      1. 20.2.1 CRC Initialization and Configuration
        1. 20.2.1.1 Data Endian Convention for the CRC Engine
    3. 20.3 CRC Registers
  23. 21On-Chip Parallel Flash
    1. 21.1  Flash Memory Configuration
    2. 21.2  Interrupts
    3. 21.3  Flash Memory Programming
    4. 21.4  32-Word Flash Memory Write Buffer
    5. 21.5  Flash Registers
    6. 21.6  CC323xSF Boot Flow
    7. 21.7  Flash User Application and Memory Partition
    8. 21.8  Programming, Bootstrapping, and Updating the Flash User Application
    9. 21.9  Image Authentication and Integrity Check
    10. 21.10 Debugging Flash User Application Using JTAG
  24. 22Revision History
  25.   A Software Development Kit Examples
  26.   B CC323x Device Miscellaneous Registers
    1. 24.1 DMA_IMR Register (offset = 8Ch) [reset = FF0Fh]
    2. 24.2 DMA_IMS Register (offset = 90h) [reset = 0h]
    3. 24.3 DMA_IMC Register (offset = 94h) [reset = 0h]
    4. 24.4 DMA_ICR Register (offset = 9Ch) [reset = 0h]
    5. 24.5 DMA_MIS Register (offset = A0h) [reset = 0h]
    6. 24.6 DMA_RIS Register (offset = A4h) [reset = 0h]
    7. 24.7 GPTTRIGSEL Register (offset = B0h) [reset = 0h]

14.6 Camera Registers

Table 14-3 lists the memory-mapped Camera registers. All register offset addresses not listed in Table 14-3 should be considered as reserved locations and the register contents should not be modified. TI recommends using the APIs instead of directly accessing the register bits in this module.

Table 14-3 Camera Registers
Offset Acronym Register Name Section
10h CC_SYSCONFIG System Configuration Register Section 14.6.1
14h CC_SYSSTATUS System Status Register Section 14.6.2
18h CC_IRQSTATUS Interrupt Status Register Section 14.6.3
1Ch CC_IRQENABLE Interrupt Enable Register Section 14.6.4
40h CC_CTRL Control Register Section 14.6.5
44h CC_CTRL_DMA Control DMA Register Section 14.6.6
48h CC_CTRL_XCLK External Clock Control Register Section 14.6.7
4Ch to 1FCh CC_FIFODATA FIFO Data Register Section 14.6.8

14.6.1 CC_SYSCONFIG Register (Offset = 10h) [reset = 0h]

CC_SYSCONFIG is shown in Figure 14-9 and described in Table 14-4.

Return to Summary Table.

This register controls the various parameters of the OCP interface (CCP and parallel mode).

Figure 14-9 CC_SYSCONFIG Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED SIdleMode RESERVED SoftReset AutoIdle
R-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-4 CC_SYSCONFIG Register Field Descriptions
Bit Field Type Reset Description
31-5 RESERVED R 0h
4-3 SIdleMode R/W 0h

Slave interface power management, req/ack control

00h = Force-idle. An idle request is acknowledged unconditionally.

01h = No-idle. An idle request is never acknowledged.

10h = Reserved (Smart-idle not implemented)

11h = Reserved – Do not use
2 RESERVED R/W 0h
1 SoftReset R/W 0h

Software reset

Set this bit to 1 to trigger a module reset. The bit is automatically reset by the hardware. During reset it always returns 0.

0h = Normal mode

1h = The module is reset
0 AutoIdle R/W 0h

Internal OCP clock gating strategy

0h = OCP clock is free-running

1h = Automatic OCP clock gating strategy is applied, based on the OCP interface activity

14.6.2 CC_SYSSTATUS Register (Offset = 14h) [reset = X]

Register mask: FFFFFFFEh

CC_SYSSTATUS is shown in Figure 14-10 and described in Table 14-5.

Return to Summary Table.

This register provides status information about the module, excluding the interrupt status information (CCP and parallel mode)

Figure 14-10 CC_SYSSTATUS Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED
R-0h
15 14 13 12 11 10 9 8
RESERVED
R-0h
7 6 5 4 3 2 1 0
RESERVED ResetDone
R-0h R-X
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-5 CC_SYSSTATUS Register Field Descriptions
Bit Field Type Reset Description
31-1 RESERVED R 0h
0 ResetDone R X

Internal Reset Monitoring

0h = Internal module reset is ongoing.

1h = Reset completed

14.6.3 CC_IRQSTATUS Register (Offset = 18h) [reset = 0h]

CC_IRQSTATUS is shown in Figure 14-11 and described in Table 14-6.

Return to Summary Table.

The interrupt status regroups all the status of the module internal events that can generate an interrupt (CCP and parallel mode)

Figure 14-11 CC_IRQSTATUS Register
31 30 29 28 27 26 25 24
RESERVED
R-0h
23 22 21 20 19 18 17 16
RESERVED FS_IRQ LE_IRQ LS_IRQ FE_IRQ
R-0h R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED FSP_ERR-IRQ FW_ERR_IRQ FSC_ERR_IRQ SSC_ERR_IRQ
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED FIFO_NOEMPTY_IRQ FIFO_FULL_IRQ FIFO_THR_IRQ FIFO_OF_IRQ FIFO_UF_IRQ
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-6 CC_IRQSTATUS Register Field Descriptions
Bit Field Type Reset Description
31-20 RESERVED R 0h
19 FS_IRQ R/W 0h

Frame Start has occurred

0h (W) = Event status bit unchanged

0h (R) = Event false

1h (W) = Event status bit is reset

1h (R) = Event is true ("pending")
18 LE_IRQ R/W 0h

Line End has occurred

0h (W) = Event status bit unchanged

0h (R) = Event false

1h (W) = Event status bit is reset

1h (R) = Event is true ("pending")
17 LS_IRQ R/W 0h

Line Start has occurred

0h (W) = Event status bit unchanged

0h (R) = Event false

1h (W) = Event status bit is reset

1h (R) = Event is true ("pending")
16 FE_IRQ R/W 0h

Frame End has occurred

0h (W) = Event status bit unchanged

0h (R) = Event false

1h (W) = Event status bit is reset

1h (R) = Event is true ("pending")
15-12 RESERVED R/W 0h
11 FSP_ERR-IRQ R/W 0h

FSP code error

0h (W) = Event status bit unchanged

0h (R) = Event false

1h (W) = Event status bit is reset

1h (R) = Event is true ("pending")
10 FW_ERR_IRQ R/W 0h

Frame Height Error

0h (W) = Event status bit unchanged

0h (R) = Event false

1h (W) = Event status bit is reset

1h (R) = Event is true ("pending")
9 FSC_ERR_IRQ R/W 0h

False Synchronization Code

0h (W) = Event status bit unchanged

0h (R) = Event false

1h (W) = Event status bit is reset

1h (R) = Event is true ("pending")
8 SSC_ERR_IRQ R/W 0h

Shifted Synchronization Code

0h (W) = Event status bit unchanged

0h (R) = Event false

1h (W) = Event status bit is reset

1h (R) = Event is true ("pending")
7-5 RESERVED R/W 0h
4 FIFO_NOEMPTY_IRQ R/W 0h

FIFO is not empty

0h (W) = Event status bit unchanged

0h (R) = Event false

1h (W) = Event status bit is reset

1h (R) = Event is true ("pending")
3 FIFO_FULL_IRQ R/W 0h

FIFO is full

0h (W) = Event status bit unchanged

0h (R) = Event false

1h (W) = Event status bit is reset

1h (R) = Event is true ("pending")
2 FIFO_THR_IRQ R/W 0h

FIFO threshold has been reached

0h (W) = Event status bit unchanged

0h (R) = Event false

1h (W) = Event status bit is reset

1h (R) = Event is true ("pending")
1 FIFO_OF_IRQ R/W 0h

FIFO overflow has occurred

0h (W) = Event status bit unchanged

0h (R) = Event false

1h (W) = Event status bit is reset

1h (R) = Event is true ("pending")
0 FIFO_UF_IRQ R/W 0h

FIFO underflow has occurred

0h (W) = Event status bit unchanged

0h (R) = Event false

1h (W) = Event status bit is reset

1h (R) = Event is true ("pending")

14.6.4 CC_IRQENABLE Register (Offset = 1Ch) [reset = 0h]

CC_IRQENABLE is shown in Figure 14-12 and described in Table 14-7.

Return to Summary Table.

The interrupt enable register enables or disables the module internal sources of interrupt on an event-by-event basis (CCP and parallel mode).

Figure 14-12 CC_IRQENABLE Register
31 30 29 28 27 26 25 24
RESERVED
R/W-0h
23 22 21 20 19 18 17 16
RESERVED FS_IRQ_EN LE_IRQ_EN LS_IRQ_EN FE_IRQ_EN
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED FSP_ERR_IRQ_EN FW_ERR_IRQ_EN FSC_ERR_IRQ_EN SSC_ERR_IRQ_EN
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED FIFO_NOEMPTY_IRQ_EN FIFO_FULL_IRQ_EN FIFO_THR_IRQ_EN FIFO_OF_IRQ_EN FIFO_UF_IRQ_EN
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-7 CC_IRQENABLE Register Field Descriptions
Bit Field Type Reset Description
31-20 RESERVED R/W 0h
19 FS_IRQ_EN R/W 0h

Frame Start Interrupt Enable

0h = Event is masked

1h = Event generates an interrupt when it occurs
18 LE_IRQ_EN R/W 0h

Line End Interrupt Enable

0h = Event is masked

1h = Event generates an interrupt when it occurs
17 LS_IRQ_EN R/W 0h

Line Start Interrupt Enable

0h = Event is masked

1h = Event generates an interrupt when it occurs
16 FE_IRQ_EN R/W 0h

Frame End Interrupt Enable

0h = Event is masked

1h = Event generates an interrupt when it occurs
15-12 RESERVED R/W 0h
11 FSP_ERR_IRQ_EN R/W 0h

FSP code Interrupt Enable

0h = Event is masked

1h = Event generates an interrupt when it occurs
10 FW_ERR_IRQ_EN R/W 0h

Frame Height Error Interrupt Enable

0h = Event is masked

1h = Event generates an interrupt when it occurs
9 FSC_ERR_IRQ_EN R/W 0h

False Synchronization Code Interrupt Enable

0h = Event is masked

1h = Event generates an interrupt when it occurs
8 SSC_ERR_IRQ_EN R/W 0h

False Synchronization Code Interrupt Enable

0h = Event is masked

1h = Event generates an interrupt when it occurs
7-5 RESERVED R/W 0h
4 FIFO_NOEMPTY_IRQ_EN R/W 0h

FIFO Not Empty Interrupt Enable

0h = Event is masked

1h = Event generates an interrupt when it occurs
3 FIFO_FULL_IRQ_EN R/W 0h

FIFO Full Interrupt Enable

0h = Event is masked

1h = Event generates an interrupt when it occurs
2 FIFO_THR_IRQ_EN R/W 0h

FIFO Threshold Interrupt Enable

0h = Event is masked

1h = Event generates an interrupt when it occurs
1 FIFO_OF_IRQ_EN R/W 0h

FIFO Overflow Interrupt Enable

0h = Event is masked

1h = Event generates an interrupt when it occurs
0 FIFO_UF_IRQ_EN R/W 0h

FIFO Underflow Interrupt Enable

0h = Event is masked

1h = Event generates an interrupt when it occurs

14.6.5 CC_CTRL Register (Offset = 40h) [reset = 1001h]

CC_CTRL is shown in Figure 14-13 and described in Table 14-8.

Return to Summary Table.

This register controls the various parameters of the camera core block (CCP and parallel mode). In CCP_MODE, configure PAR_MODE to 0x0.

Figure 14-13 CC_CTRL Register
31 30 29 28 27 26 25 24
RESERVED
R/W-0h
23 22 21 20 19 18 17 16
RESERVED CC_ONE_SHOT CC_IF_SYNCHRO CC_RST CC_FRAME_TRIG CC_EN
R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h R/W-0h
15 14 13 12 11 10 9 8
RESERVED NOBT_SYNCHRO BT_CORRECT PAR_ORDERCAM PAR_CLK_POL NOBT_HS_POL NOBT_VS_POL
R/W-0h R/W-0h R/W-1h R/W-0h R/W-0h R/W-0h R/W-0h
7 6 5 4 3 2 1 0
RESERVED PORT_SELECT PAR_MODE
R/W-0h R/W-0h R/W-1h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-8 CC_CTRL Register Field Descriptions
Bit Field Type Reset Description
31-21 RESERVED R/W 0h
20 CC_ONE_SHOT R/W 0h

One-shot capability (one frame captured)

This must be set in the same time as CC_EN is set to 1.

One frame acquisition starts and stops automatically. Reads returns 0

0h = No synchro (most of applications)

1h = Synchro enabled (should never be required)
19 CC_IF_SYNCHRO R/W 0h

Synchronize all camera sensor inputs

This must be set during the configuration phase before CC_EN set to 1.

Used in very high frequency to avoid dependancy to the I/O timings.

0h = No synchro (most of applications)

1h = Synchro enabled (should never be required)
18 CC_RST R/W 0h

Reset all the internal finite state machines of the camera core module by writing a 1 to this bit.

Must be applied when CC_EN = 0. Reads returns 0
17 CC_FRAME_TRIG R/W 0h

Sets the modality in which CC_EN works when disabling the sensor camera core.

If CC_FRAME_TRIG = 1, by writing 0 to CC_EN the module is disabled at the end of the frame

If CC_FRAME_TRIG = 0, by writing 0 to CC_EN the module is disabled immediately
16 CC_EN R/W 0h

Enables the sensor interface of the camera core module.

By writing 1 to this field, the module is enabled

By writing 0 to this field, the module is disabled at the end of the frame if CC_FRAME_TRIG = 1, and is disabled immediately if CC_FRAME_TRIG = 0.
15-14 RESERVED R/W 0h
13 NOBT_SYNCHRO R/W 0h

Enables start at the beginning of the frame or not in NoBT

0h = Acquisition starts when vertical synchro is high

1h = Acquisition starts when vertical synchro goes from low to high (beginning of the frame) (recommended)
12 BT_CORRECT R/W 1h

Enables the correct sync codes in BT mode.

0h = Correction is not enabled

1h = Correction is enabled
11 PAR_ORDERCAM R/W 0h

Enables swap between image-data in parallel mode.

0h = Swap is not enabled

1h = Swap is enabled
10 PAR_CLK_POL R/W 0h

Inverts the clock coming from the sensor in parallel mode.

0h = Clock not inverted - data sampled on rising edge

1h = Clock inverted - data sampled on falling edge
9 NOBT_HS_POL R/W 0h

Sets the polarity of the synchronization signals in NOBT parallel mode.

0h = CAM_P_HS is active high

1h = CAM_P_HS is active low
8 NOBT_VS_POL R/W 0h

Sets the polarity of the synchronization signals in NOBT parallel mode.

0h = CAM_P_VS is active high

1h = CAM_P_VS is active low
7-5 RESERVED R/W 0h
4 PORT_SELECT R/W 0h

Determines which OCP port can perform read access from internal FIFO when DMA_EN bit is set to 1.

0h = OCP 2

1h = OCP 1
3-0 PAR_MODE R/W 1h

Sets the protocol mode of the camera core module in parallel mode (when CCP_MODE = 0).

000h = Parallel NOBT 8-bit

001h = Parallel NOBT 10-bit

010h = Parallel NOBT 12-bit

011h = Reserved

100h = Parallel BT 8-bit

101h = Parallel BT 10-bit

110h = Reserved

111h = FIFO test mode.

14.6.6 CC_CTRL_DMA Register (Offset = 44h) [reset = 207h]

CC_CTRL_DMA is shown in Figure 14-14 and described in Table 14-9.

Return to Summary Table.

This register controls the DMA interface of the camera core block (CCP and parallel mode).

Figure 14-14 CC_CTRL_DMA Register
31 30 29 28 27 26 25 24
RESERVED
R/W-1h
23 22 21 20 19 18 17 16
RESERVED
R/W-1h
15 14 13 12 11 10 9 8
RESERVED DMA_EN
R/W-1h R/W-0h
7 6 5 4 3 2 1 0
RESERVED FIFO_THRESHOLD
R/W-0h R/W-7h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-9 CC_CTRL_DMA Register Field Descriptions
Bit Field Type Reset Description
31-9 RESERVED R/W 1h
8 DMA1_DISABLE R/W 0h

DMA1 disable capability. Only use DMA0 (threshold-based).

0h = DMA1 line can be activated

1h = DMA1 line can not be activated
8 DMA_EN R/W 0h

Sets the number of DMA request lines.

0h = DMA interface disabled. The DMA request line stays inactive.

1h = DMA interface enabled. The DMA request line is operational.
7 RESERVED R/W 0h
6-0 FIFO_THRESHOLD R/W 7h

Sets the threshold of the FIFO. The assertion of the DMA request line takes place when the threshold is reached.

00000000h = Threshold set to 1

00000001h = Threshold set to 2

...

01111111h = Threshold set to 128

14.6.7 CC_CTRL_XCLK Register (Offset = 48h) [reset = 0h]

CC_CTRL_XCLK is shown in Figure 14-15 and described in Table 14-10.

Return to Summary Table.

This register controls the value of the clock divisor used to generate the external clock (parallel mode). Refer to Table 14-2 for details about the ratio of XCLK frequency.

Figure 14-15 CC_CTRL_XCLK Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESERVED
R/W-0h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED XCLK_DIV
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-10 CC_CTRL_XCLK Register Field Descriptions
Bit Field Type Reset Description
31-5 RESERVED R/W 0h
4-0 XCLK_DIV R/W 0h

Sets the clock divisor value for CAM_XCLK generation.

Based on CAM_MCLK (value of CAM_MCLK IS 96 MHz).

Divider not enabled

00000000h = CAM_XCLK Stable low level

00000001h = CAM_XCLK Stable high level

from 2 to 30 = CAM_XCLK = CAM_MCLK / XCLK DIV

00011111h = Bypass - CAM_XCLK = CAM_MCLK

14.6.8 CC_FIFODATA Register (Offset = 4Ch) [reset = X]

CC_FIFODATA is shown in Figure 14-16 and described in Table 14-11.

Return to Summary Table.

This register allows the user to write and read from the FIFO (CCP and parallel mode). Refer to Section 14.3.2 for details about FIFO write and read accesses into this register bank.

Figure 14-16 CC_FIFODATA Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIFO_DATA
R/W-X
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 14-11 CC_FIFODATA Register Field Descriptions
Bit Field Type Reset Description
31-0 FIFO_DATA R/W X

Reads or writes the 32-bit word from or into the FIFO.