SWRU543B January   2019  – June 2025 CC3230S , CC3230SF , CC3235MODS , CC3235MODSF , CC3235S , CC3235SF

 

  1.   1
  2.   Read This First
    1.     Audience
    2.     About This Manual
    3.     Register Bit Conventions
    4.     Glossary
    5.     Related Documentation
    6.     Community Resources
    7.     Trademarks
  3. 1 Architecture Overview
    1. 1.1 Introduction
    2. 1.2 Architecture Overview
    3. 1.3 Functional Overview
      1. 1.3.1  Processor Core
        1. 1.3.1.1 Arm® Cortex®-M4 Processor Core
        2. 1.3.1.2 System Timer (SysTick)
        3. 1.3.1.3 Nested Vector Interrupt Controller (NVIC)
        4. 1.3.1.4 System Control Block
      2. 1.3.2  Memory
        1. 1.3.2.1 On-Chip SRAM
        2. 1.3.2.2 ROM
        3. 1.3.2.3 Flash Memory
      3. 1.3.3  Micro-Direct Memory Access Controller (µDMA)
      4. 1.3.4  General-Purpose Timer (GPT)
      5. 1.3.5  Watchdog Timer (WDT)
      6. 1.3.6  Multichannel Audio Serial Port (McASP)
      7. 1.3.7  Serial Peripheral Interface (SPI)
      8. 1.3.8  Inter-Integrated Circuit (I2C) Interface
      9. 1.3.9  Universal Asynchronous Receiver/Transmitter (UART)
      10. 1.3.10 General-Purpose Input/Output (GPIO)
      11. 1.3.11 Analog-to-Digital Converter (ADC)
      12. 1.3.12 SD Card Host
      13. 1.3.13 Parallel Camera Interface
      14. 1.3.14 Debug Interface
      15. 1.3.15 Hardware Cryptography Accelerator
      16. 1.3.16 Clock, Reset, and Power Management
      17. 1.3.17 SimpleLink™ Subsystem
      18. 1.3.18 I/O Pads and Pin Multiplexing
  4. 2 Cortex®-M4 Processor
    1. 2.1 Overview
      1. 2.1.1 Block Diagram
      2. 2.1.2 System-Level Interface
      3. 2.1.3 Integrated Configurable Debug
      4. 2.1.4 Trace Port Interface Unit (TPIU)
      5. 2.1.5 Cortex®-M4 System Component Details
    2. 2.2 Functional Description
      1. 2.2.1 Programming Model
        1. 2.2.1.1 Processor Mode and Privilege Levels for Software Execution
        2. 2.2.1.2 Stacks
      2. 2.2.2 Register Description
        1. 2.2.2.1 Register Map
        2. 2.2.2.2 Register Descriptions
          1. 2.2.2.2.1 Stack Pointer (SP)
          2. 2.2.2.2.2 Link Register (LR)
          3. 2.2.2.2.3 Program Counter (PC)
          4. 2.2.2.2.4 Program Status Register (PSR)
          5. 2.2.2.2.5 Priority Mask Register (PRIMASK)
          6. 2.2.2.2.6 Fault Mask Register (FAULTMASK)
          7. 2.2.2.2.7 Base Priority Mask Register (BASEPRI)
          8. 2.2.2.2.8 Control Register (CONTROL)
        3. 2.2.2.3 Exceptions and Interrupts
        4. 2.2.2.4 Data Types
      3. 2.2.3 Memory Model
        1. 2.2.3.1 Bit-Banding
          1. 2.2.3.1.1 Directly Accessing an Alias Region
          2. 2.2.3.1.2 Directly Accessing a Bit-Band Region
        2. 2.2.3.2 Data Storage
        3. 2.2.3.3 Synchronization Primitives
      4. 2.2.4 Exception Model
        1. 2.2.4.1 Exception States
        2. 2.2.4.2 Exception Types
        3. 2.2.4.3 Exception Handlers
        4. 2.2.4.4 Vector Table
        5. 2.2.4.5 Exception Priorities
        6. 2.2.4.6 Interrupt Priority Grouping
        7. 2.2.4.7 Exception Entry and Return
          1. 2.2.4.7.1 Exception Entry
      5. 2.2.5 Fault Handling
        1. 2.2.5.1 Fault Types
        2. 2.2.5.2 Fault Escalation and Hard Faults
        3. 2.2.5.3 Fault Status Registers and Fault Address Registers
        4. 2.2.5.4 Lockup State
      6. 2.2.6 Power Management
      7. 2.2.7 Instruction Set Summary
  5. 3 Cortex®-M4 Peripherals
    1. 3.1 Overview
    2. 3.2 Functional Description
      1. 3.2.1 System Timer (SysTick)
      2. 3.2.2 Nested Vectored Interrupt Controller (NVIC)
        1. 3.2.2.1 Level-Sensitive and Pulse Interrupts
        2. 3.2.2.2 Hardware and Software Control of Interrupts
      3. 3.2.3 System Control Block (SCB)
    3. 3.3 Register Map
      1. 3.3.1 Cortex Registers
  6. 4 Direct Memory Access (DMA)
    1. 4.1 Overview
    2. 4.2 Functional Description
      1. 4.2.1 Channel Assignment
      2. 4.2.2 Priority
      3. 4.2.3 Arbitration Size
      4. 4.2.4 Channel Configuration
      5. 4.2.5 Transfer Mode
        1. 4.2.5.1 Stop Mode
        2. 4.2.5.2 Basic Mode
        3. 4.2.5.3 Auto Mode
        4. 4.2.5.4 Ping-Pong Mode
        5. 4.2.5.5 Memory Scatter-Gather Mode
        6. 4.2.5.6 Peripheral Scatter-Gather Mode
      6. 4.2.6 Transfer Size and Increment
      7. 4.2.7 Peripheral Interface
        1. 4.2.7.1 FIFO Peripherals
        2. 4.2.7.2 Trigger Peripherals
        3. 4.2.7.3 Software Request
      8. 4.2.8 Interrupts and Errors
    3. 4.3 Register Description
      1. 4.3.1 DMA Register Map
      2. 4.3.2 µDMA Channel Control Structure
      3. 4.3.3 DMA Registers
      4. 4.3.4 DMA_(OFFSET_FROM_DMA_BASE_ADDRESS) Registers
  7. 5 General-Purpose Input/Outputs (GPIOs)
    1. 5.1 Overview
    2. 5.2 Functional Description
      1. 5.2.1 Data Control
        1. 5.2.1.1 Data Direction Operation
        2. 5.2.1.2 Data Register Operation
    3. 5.3 Interrupt Control
      1. 5.3.1 µDMA Trigger Source
    4. 5.4 Initialization and Configuration
    5. 5.5 GPIO Registers
  8. 6 Universal Asynchronous Receivers/Transmitters (UARTs)
    1. 6.1 Overview
      1. 6.1.1 Block Diagram
    2. 6.2 Functional Description
      1. 6.2.1 Transmit and Receive Logic
      2. 6.2.2 Baud-Rate Generation
      3. 6.2.3 Data Transmission
        1. 6.2.3.1 Flow Control
          1. 6.2.3.1.1 Hardware Flow Control (RTS/CTS)
          2. 6.2.3.1.2 Software Flow Control (Modem Status Interrupts)
        2. 6.2.3.2 FIFO Operation
        3. 6.2.3.3 Interrupts
        4. 6.2.3.4 LoopbackOperation
        5. 6.2.3.5 DMA Operation
      4. 6.2.4 Initialization and Configuration
    3. 6.3 UART Registers
  9. 7 Inter-Integrated Circuit (I2C) Interface
    1. 7.1 Overview
      1. 7.1.1 Block Diagram
      2. 7.1.2 Signal Description
    2. 7.2 Functional Description
      1. 7.2.1 I2C Bus Functional Overview
        1. 7.2.1.1 START and STOP Conditions
        2. 7.2.1.2 Data Format With 7-Bit Address
        3. 7.2.1.3 Data Validity
        4. 7.2.1.4 Acknowledge
        5. 7.2.1.5 Repeated Start
        6. 7.2.1.6 Clock Low Time-out (CLTO)
        7. 7.2.1.7 Dual Address
        8. 7.2.1.8 Arbitration
      2. 7.2.2 Supported Speed Modes
        1. 7.2.2.1 Standard and Fast Modes
      3. 7.2.3 Interrupts
      4. 7.2.4 Loopback Operation
      5. 7.2.5 FIFO and µDMA Operation
        1. 7.2.5.1 Master Module Burst Mode
          1. 7.2.5.1.1 Master Module µDMA Functionality
          2. 7.2.5.1.2 Slave Module
      6. 7.2.6 Command Sequence Flow Charts
        1. 7.2.6.1 I2C Master Command Sequences
        2. 7.2.6.2 I2C Slave Command Sequences
      7. 7.2.7 Initialization and Configuration
    3. 7.3 I2C Registers
  10. 8 SPI (Serial Peripheral Interface)
    1. 8.1 Overview
      1. 8.1.1 Features
    2. 8.2 Functional Description
      1. 8.2.1 SPI
      2. 8.2.2 SPI Transmission
        1. 8.2.2.1 Two Data Pins Interface Mode
        2. 8.2.2.2 Transfer Formats
          1. 8.2.2.2.1 Programmable Word Length
          2. 8.2.2.2.2 Programmable SPI Enable (SPIEN)
          3. 8.2.2.2.3 Programmable SPI Clock (SPICLK)
          4. 8.2.2.2.4 Bit Rate
          5. 8.2.2.2.5 Polarity and Phase
            1. 8.2.2.2.5.1 Transfer Format With PHA = 0
            2. 8.2.2.2.5.2 Transfer Format With PHA = 1
      3. 8.2.3 Master Mode
        1. 8.2.3.1 Interrupt Events in Master Mode
          1. 8.2.3.1.1 TX_empty
          2. 8.2.3.1.2 TX_underflow
          3. 8.2.3.1.3 RX_ full
          4. 8.2.3.1.4 End-of-Word Count
        2. 8.2.3.2 Master Transmit and Receive Mode
        3. 8.2.3.3 SPI Enable Control in Master Mode
          1. 8.2.3.3.1 Keep SPIEN Active Mode (Force SPIEN)
        4. 8.2.3.4 Clock Ratio Granularity
          1. 8.2.3.4.1 FIFO Buffer Management
            1. 8.2.3.4.1.1 Split FIFO
            2. 8.2.3.4.1.2 Buffer Almost Full
            3. 8.2.3.4.1.3 Buffer Almost Empty
            4. 8.2.3.4.1.4 End of Transfer Management
            5. 8.2.3.4.1.5 3- or 4-Pin Mode
      4. 8.2.4 Slave Mode
        1. 8.2.4.1 Interrupts Events in Slave Mode
          1. 8.2.4.1.1 TX_empty
          2. 8.2.4.1.2 TX_underflow
          3. 8.2.4.1.3 RX_ full
          4. 8.2.4.1.4 RX_overflow
          5. 8.2.4.1.5 End-of-Word Count
        2. 8.2.4.2 Slave Transmit and Receive Mode
      5. 8.2.5 Interrupts
        1. 8.2.5.1 Interrupt-Driven Operation
        2. 8.2.5.2 Polling
      6. 8.2.6 DMA Requests
        1. 8.2.6.1 FIFO Buffer Enabled
      7. 8.2.7 Reset
    3. 8.3 Initialization and Configuration
      1. 8.3.1 Basic Initialization
      2. 8.3.2 Master Mode Operation Without Interrupt (Polling)
      3. 8.3.3 Slave Mode Operation With Interrupt
      4. 8.3.4 Generic Interrupt Handler Implementation
    4. 8.4 Access to Data Registers
    5. 8.5 Module Initialization
      1. 8.5.1 Common Transfer Sequence
      2. 8.5.2 End-of-Transfer Sequences
      3. 8.5.3 FIFO Mode
        1. 8.5.3.1 Common Transfer Sequence
        2. 8.5.3.2 Transmit Receive With Word Count
        3. 8.5.3.3 Transmit Receive Without Word Count
    6. 8.6 SPI Registers
  11. 9 General-Purpose Timers
    1. 9.1 Overview
    2. 9.2 Block Diagram
    3. 9.3 Functional Description
      1. 9.3.1 GPTM Reset Conditions
      2. 9.3.2 Timer Modes
        1. 9.3.2.1 One-Shot or Periodic Timer Mode
        2. 9.3.2.2 Input Edge-Count Mode
        3. 9.3.2.3 Input Edge-Time Mode
        4. 9.3.2.4 PWM Mode
      3. 9.3.3 DMA Operation
      4. 9.3.4 Accessing Concatenated 16/32-Bit GPTM Register Values
    4. 9.4 Initialization and Configuration
      1. 9.4.1 One-Shot and Periodic Timer Mode
      2. 9.4.2 Input Edge-Count Mode
      3. 9.4.3 Input Edge-Time Mode
      4. 9.4.4 PWM Mode
    5. 9.5 Timer Registers
  12. 10Watchdog Timer
    1. 10.1 Overview
      1. 10.1.1 Block Diagram
    2. 10.2 Functional Description
      1. 10.2.1 Initialization and Configuration
    3. 10.3 WATCHDOG Registers
    4. 10.4 MCU Watchdog Controller Usage Caveats
      1. 10.4.1 System Watchdog
      2. 10.4.2 System Watchdog Recovery Sequence
  13. 11SD Host Controller Interface
    1. 11.1 Overview
    2. 11.2 SD Host Features
    3. 11.3 1-Bit SD Interface
      1. 11.3.1 Clock and Reset Management
    4. 11.4 Initialization and Configuration Using Peripheral APIs
      1. 11.4.1 Basic Initialization and Configuration
      2. 11.4.2 Sending Command
      3. 11.4.3 Card Detection and Initialization
      4. 11.4.4 Block Read
      5. 11.4.5 Block Write
    5. 11.5 Performance and Testing
    6. 11.6 Peripheral Library APIs
    7. 11.7 SD-HOST Registers
  14. 12Inter-Integrated Sound (I2S) Multichannel Audio Serial Port
    1. 12.1 Overview
      1. 12.1.1 I2S Format
    2. 12.2 Functional Description
    3. 12.3 Programming Model
      1. 12.3.1 Clock and Reset Management
      2. 12.3.2 I2S Data Port Interface
      3. 12.3.3 Initialization and Configuration
    4. 12.4 Peripheral Library APIs for I2S Configuration
      1. 12.4.1 Basic APIs for Enabling and Configuring the Interface
        1. 12.4.1.1 void I2SDisable (unsigned long ulBase)
        2. 12.4.1.2 void I2SEnable (unsigned long ulBase, unsigned long ulMode)
        3. 12.4.1.3 void I2SSerializerConfig (unsigned long ulBase, unsigned long ulDataLine, unsigned long ulSerMode, unsigned long ulInActState)
        4. 12.4.1.4 void I2SConfigSetExpClk (unsigned long ulBase, unsigned long ulI2SClk, unsigned long ulBitClk, unsigned long ulConfig)
      2. 12.4.2 APIs for Data Access if DMA is Not Used
        1. 12.4.2.1 void I2SDataGet (unsigned long ulBase, unsigned long ulDataLine, unsigned long * pulData)
        2. 12.4.2.2 long I2SDataGetNonBlocking (unsigned long ulBase, unsigned long ulDataLine, unsigned long * pulData)
        3. 12.4.2.3 void I2SDataPut (unsigned long ulBase, unsigned long ulDataLine, unsigned long ulData)
        4. 12.4.2.4 void I2SDataPut (unsigned long ulBase, unsigned long ulDataLine, unsigned long ulData)
      3. 12.4.3 APIs for Setting Up, Handling Interrupts, or Getting Status from I2S Peripheral
        1. 12.4.3.1 void I2SIntRegister (unsigned long ulBase, void(*)(void) pfnHandler)
        2. 12.4.3.2 void I2SIntEnable (unsigned long ulBase, unsigned long ulIntFlags)
        3. 12.4.3.3 void I2SIntDisable (unsigned long ulBase, unsigned long ulIntFlags)
        4. 12.4.3.4 unsigned long I2SIntStatus (unsigned long ulBase)
        5. 12.4.3.5 void I2SIntUnregister (unsigned long ulBase)
        6. 12.4.3.6 void I2SIntClear (unsigned long ulBase, unsigned long ulStatFlags)
        7. 12.4.3.7 Values that can be Passed to I2SIntEnable() and I2SIntDisable() as the ulIntFlags Parameter
        8. 12.4.3.8 Values that can be Passed to I2SIntClear() as the ulStatFlags Parameter and Returned from I2SIntStatus()
      4. 12.4.4 APIs to Control FIFO Structures Associated With I2S Peripheral
        1. 12.4.4.1 void I2SRxFIFODisable (unsigned long ulBase)
        2. 12.4.4.2 void I2SRxFIFOEnable (unsigned long ulBase, unsigned long ulRxLevel, unsigned long ulWordsPerTransfer)
        3. 12.4.4.3 unsigned long I2SRxFIFOStatusGet (unsigned long ulBase)
        4. 12.4.4.4 void I2STxFIFODisable (unsigned long ulBase)
        5. 12.4.4.5 void I2STxFIFOEnable (unsigned long ulBase, unsigned long ulTxLevel, unsigned long ulWordsPerTransfer)
        6. 12.4.4.6 unsigned long I2STxFIFOStatusGet (unsigned long ulBase)
    5. 12.5 I2S Registers
  15. 13Analog-to-Digital Converter (ADC)
    1. 13.1 Overview
    2. 13.2 Key Features
    3. 13.3 ADC Register Mapping
    4. 13.4 ADC_MODULE Registers
    5. 13.5 Initialization and Configuration
    6. 13.6 Peripheral Library APIs for ADC Operation
      1. 13.6.1 Overview
      2. 13.6.2 Configuring the ADC Channels
      3. 13.6.3 Basic APIs for Enabling and Configuring the Interface
        1. 13.6.3.1 void ADCEnable (unsigned long ulBase)
        2. 13.6.3.2 void ADCDisable (unsigned long ulBase)
        3. 13.6.3.3 void ADCChannelEnable (unsigned long ulBase, unsigned long ulChannel)
        4. 13.6.3.4 void ADCChannelDisable (unsigned long ulBase, unsigned long ulChannel)
      4. 13.6.4 APIs for Data Transfer [Direct Access to FIFO and DMA Setup]
        1. 13.6.4.1 unsigned char ADCFIFOLvlGet (unsigned long ulBase, unsigned long ulChannel)
        2. 13.6.4.2 unsigned long ADCFIFORead (unsigned long ulBase, unsigned long ulChannel)
        3. 13.6.4.3 void ADCDMAEnable (unsigned long ulBase, unsigned long ulChannel)
        4. 13.6.4.4 void ADCDMADisable (unsigned long ulBase, unsigned long ulChannel)
      5. 13.6.5 APIs for Interrupt Usage
        1. 13.6.5.1 void ADCIntEnable (unsigned long ulBase, unsigned long ulChannel, unsigned long ulIntFlags)
        2. 13.6.5.2 void ADCIntDisable (unsigned long ulBase, unsigned long ulChannel, unsigned long ulIntFlags)
        3. 13.6.5.3 void ADCIntRegister (unsigned long ulBase, unsigned long ulChannel, void(*)(void) pfnHandler)
        4. 13.6.5.4 void ADCIntUnregister (unsigned long ulBase, unsigned long ulChannel)
        5. 13.6.5.5 unsigned long ADCIntStatus (unsigned long ulBase, unsigned long ulChannel)
        6. 13.6.5.6 void ADCIntClear (unsigned long ulBase, unsigned long ulChannel, unsigned long ulIntFlags)
      6. 13.6.6 APIs for Setting Up ADC Timer for Time-Stamping the Samples
        1. 13.6.6.1 void ADCTimerConfig (unsigned long ulBase, unsigned long ulValue)
        2. 13.6.6.2 void ADCTimerDisable (unsigned long ulBase)
        3. 13.6.6.3 void ADCTimerEnable (unsigned long ulBase)
        4. 13.6.6.4 void ADCTimerReset (unsigned long ulBase)
        5. 13.6.6.5 unsigned long ADCTimerValueGet (unsigned long ulBase)
  16. 14Parallel Camera Interface Module
    1. 14.1 Overview
    2. 14.2 Image Sensor Interface
    3. 14.3 Functional Description
      1. 14.3.1 Modes of Operation
      2. 14.3.2 FIFO Buffer
      3. 14.3.3 Reset
      4. 14.3.4 Clock Generation
      5. 14.3.5 Interrupt Generation
      6. 14.3.6 DMA Interface
    4. 14.4 Programming Model
      1. 14.4.1 Camera Core Reset
      2. 14.4.2 Enable the Picture Acquisition
      3. 14.4.3 Disable the Picture Acquisition
    5. 14.5 Interrupt Handling
      1. 14.5.1 FIFO_OF_IRQ (FIFO Overflow)
      2. 14.5.2 FIFO_UF_IRQ (FIFO Underflow)
    6. 14.6 Camera Registers
    7. 14.7 Peripheral Library APIs
    8. 14.8 Developer’s Guide
      1. 14.8.1 Using Peripheral Driver APIs for Capturing an Image
      2. 14.8.2 Using Peripheral Driver APIs for Communicating With Image Sensors
  17. 15Power, Reset, and Clock Management
    1. 15.1 Overview
      1. 15.1.1 Power Management Unit (PMU)
      2. 15.1.2 VBAT Wide-Voltage Connection
      3. 15.1.3 Supply Brownout and Blackout
      4. 15.1.4 Application Processor Power Modes
    2. 15.2 Power Management Control Architecture
      1. 15.2.1 Global Power-Reset-Clock Manager (GPRCM)
      2. 15.2.2 Application Reset-Clock Manager (ARCM)
    3. 15.3 PRCM APIs
      1. 15.3.1  MCU Initialization
      2. 15.3.2  Reset Control
      3. 15.3.3  Peripheral Reset
      4. 15.3.4  Reset Cause
      5. 15.3.5  Clock Control
      6. 15.3.6  Low-Power Modes
      7. 15.3.7  Sleep (SLEEP)
      8. 15.3.8  Low-Power Deep Sleep (LPDS)
      9. 15.3.9  Hibernate (HIB)
      10. 15.3.10 Slow Clock Counter
    4. 15.4 Peripheral Macros
    5. 15.5 Power Management Framework
    6. 15.6 PRCM Registers
  18. 16I/O Pads and Pin Multiplexing
    1. 16.1 Overview
    2. 16.2 I/O Pad Electrical Specifications
    3. 16.3 Analog and Digital Pin Multiplexing
    4. 16.4 Special Analog/Digital Pins
      1. 16.4.1 Pins 45 and 52
      2. 16.4.2 Pins 29 and 30
      3. 16.4.3 Pins 57, 58, 59, and 60
    5. 16.5 Analog Mux Control Registers
    6. 16.6 Pins Available for Applications
    7. 16.7 Functional Pin Mux Configurations
    8. 16.8 Pin Mapping Recommendations
      1. 16.8.1 Pad Configuration Registers for Application Pins
        1. 16.8.1.1 Pad Mux and Electrical Configuration Register Bit Definitions
      2. 16.8.2 PAD Behavior During Reset and Hibernate
      3. 16.8.3 Control Architecture
      4. 16.8.4 CC32xx Pin-mux Examples
      5. 16.8.5 Wake on Pad
      6. 16.8.6 Sense on Power
  19. 17Advance Encryption Standard Accelerator (AES)
    1. 17.1 AES Overview
    2. 17.2 AES Functional Description
      1. 17.2.1 AES Block Diagram
        1. 17.2.1.1 Interfaces
        2. 17.2.1.2 AES Wide-Bus Engine
      2. 17.2.2 AES Algorithm
      3. 17.2.3 AES Operating Modes
        1. 17.2.3.1 Supported Modes of Operation
        2. 17.2.3.2 Extended and Combined Modes of Operations
      4. 17.2.4 Hardware Requests
    3. 17.3 AES Module Programming Guide
      1. 17.3.1 AES Low-Level Programming Models
        1. 17.3.1.1 Global Initialization
        2. 17.3.1.2 Initialization Subsequence
        3. 17.3.1.3 Operational Modes Configuration
        4. 17.3.1.4 AES Events Servicing
    4. 17.4 AES Registers
  20. 18Data Encryption Standard Accelerator (DES)
    1. 18.1 DES Functional Description
    2. 18.2 DES Block Diagram
      1. 18.2.1 µDMA Control
      2. 18.2.2 Interrupt Control
      3. 18.2.3 Register Interface
      4. 18.2.4 DES Enginer
        1. 18.2.4.1 Mode Control FSM
        2. 18.2.4.2 DES Feedback Mode Block
        3. 18.2.4.3 DES Cipher Core
    3. 18.3 DES-Supported Modes of Operation
      1. 18.3.1 ECB Feedback Mode
        1. 18.3.1.1 CBC Feedback Mode
        2. 18.3.1.2 CFB Feedback Mode
    4. 18.4 DES Module Programming Guide – Low-Level Programming Models
      1. 18.4.1 Surrounding Modules Global Initialization
        1. 18.4.1.1 Main Sequence – DES Global Initialization
        2. 18.4.1.2 Subsequence – Configure the DES Algorithm Type
        3. 18.4.1.3 Subsequence – Configure the 3DES Algorithm Type
      2. 18.4.2 Operational Modes Configuration
        1. 18.4.2.1 Main Sequence – DES Polling Mode
        2. 18.4.2.2 DES Interrupt Mode
        3. 18.4.2.3 DES Interrupt DMA Mode
      3. 18.4.3 DES Events Servicing
        1. 18.4.3.1 Interrupt Servicing
        2. 18.4.3.2 Context Input Event Servicing
    5. 18.5 DES Registers
  21. 19SHA/MD5 Accelerator
    1. 19.1 SHA/MD5 Functional Description
      1. 19.1.1 SHA/MD5 Block Diagram
        1. 19.1.1.1 Configuration Registers
        2. 19.1.1.2 Hash/HMAC Engine
        3. 19.1.1.3 Hash Core Control
        4. 19.1.1.4 Host Interface Bank
      2. 19.1.2 µDMA and Interrupt Requests
      3. 19.1.3 Operation Description
        1. 19.1.3.1 SHA Mode
          1. 19.1.3.1.1 Starting a New Hash
          2. 19.1.3.1.2 Outer Digest Registers
          3. 19.1.3.1.3 Inner Digest Registers
          4. 19.1.3.1.4 Closing a Hash
        2. 19.1.3.2 MD5 Mode
          1. 19.1.3.2.1 Starting a New Hash
          2. 19.1.3.2.2 Closing a Hash
        3. 19.1.3.3 Generating a Software Interrupt
      4. 19.1.4 SHA/MD5 Programming Guide
        1. 19.1.4.1 Global Initialization
          1. 19.1.4.1.1 Surrounding Modules Global Initialization
          2. 19.1.4.1.2 Starting a New HMAC using the SHA-1 Hash Function and HMAC Key Processing
          3. 19.1.4.1.3 Subsequence - Continuing a Prior HMAC Using the SHA-1 Hash Function
          4. 19.1.4.1.4 Subsequence - Hashing a Key Bigger than 512 Bits with the SHA-1 Hash Function
          5. 19.1.4.1.5 Operational Modes Configuration
          6. 19.1.4.1.6 SHA/MD5 Event Servicing
            1. 19.1.4.1.6.1 Interrupt Servicing
    2. 19.2 SHA-MD5 Registers
  22. 20Cyclical Redundancy Check (CRC)
    1. 20.1 Functional Description
      1. 20.1.1 CRC Support
        1. 20.1.1.1 CRC Checksum Engine
        2. 20.1.1.2 Data Size
        3. 20.1.1.3 Endian Configuration
    2. 20.2 Initialization and Configuration
      1. 20.2.1 CRC Initialization and Configuration
        1. 20.2.1.1 Data Endian Convention for the CRC Engine
    3. 20.3 CRC Registers
  23. 21On-Chip Parallel Flash
    1. 21.1  Flash Memory Configuration
    2. 21.2  Interrupts
    3. 21.3  Flash Memory Programming
    4. 21.4  32-Word Flash Memory Write Buffer
    5. 21.5  Flash Registers
    6. 21.6  CC323xSF Boot Flow
    7. 21.7  Flash User Application and Memory Partition
    8. 21.8  Programming, Bootstrapping, and Updating the Flash User Application
    9. 21.9  Image Authentication and Integrity Check
    10. 21.10 Debugging Flash User Application Using JTAG
  24. 22Revision History
  25.   A Software Development Kit Examples
  26.   B CC323x Device Miscellaneous Registers
    1. 24.1 DMA_IMR Register (offset = 8Ch) [reset = FF0Fh]
    2. 24.2 DMA_IMS Register (offset = 90h) [reset = 0h]
    3. 24.3 DMA_IMC Register (offset = 94h) [reset = 0h]
    4. 24.4 DMA_ICR Register (offset = 9Ch) [reset = 0h]
    5. 24.5 DMA_MIS Register (offset = A0h) [reset = 0h]
    6. 24.6 DMA_RIS Register (offset = A4h) [reset = 0h]
    7. 24.7 GPTTRIGSEL Register (offset = B0h) [reset = 0h]

17.4 AES Registers

Table 17-3 lists the memory-mapped registers for the AES. All register offset addresses not listed in Table 17-3 should be considered as reserved locations and the register contents should not be modified.

Table 17-3 AES Registers
OffsetAcronymRegister NameSection
0hAES_KEY2_6Key registerSection 17.4.1
4hAES_KEY2_7Key registerSection 17.4.2
8hAES_KEY2_4Key registerSection 17.4.3
ChAES_KEY2_5Key registerSection 17.4.4
10hAES_KEY2_2Key registerSection 17.4.5
14hAES_KEY2_3Key registerSection 17.4.6
18hAES_KEY2_0Key registerSection 17.4.7
1ChAES_KEY2_1Key registerSection 17.4.8
20hAES_KEY1_6Key registerSection 17.4.9
24hAES_KEY1_7Key registerSection 17.4.10
28hAES_KEY1_4Key registerSection 17.4.11
2ChAES_KEY1_5Key registerSection 17.4.12
30hAES_KEY1_2Key registerSection 17.4.13
34hAES_KEY1_3Key registerSection 17.4.14
38hAES_KEY1_0Key registerSection 17.4.15
3ChAES_KEY1_1Key registerSection 17.4.16
40hAES_IV_IN_0Section 17.4.17
44hAES_IV_IN_1Section 17.4.18
48hAES_IV_IN_2Section 17.4.19
4ChAES_IV_IN_3Section 17.4.20
50hAES_CTRLSection 17.4.21
54hAES_C_LENGTH_0Section 17.4.22
58hAES_C_LENGTH_1Section 17.4.23
5ChAES_AUTH_LENGTHSection 17.4.24
60hAES_DATA_IN_0Data registerSection 17.4.25
64hAES_DATA_IN_1Data registerSection 17.4.26
68hAES_DATA_IN_2Data registerSection 17.4.27
6ChAES_DATA_IN_3Data registerSection 17.4.28
70hAES_TAG_OUT_0Section 17.4.29
74hAES_TAG_OUT_1Section 17.4.30
78hAES_TAG_OUT_2Section 17.4.31
7ChAES_TAG_OUT_3Section 17.4.32
80hAES_REVISIONSection 17.4.33
84hAES_SYSCONFIGSection 17.4.34
8ChAES_IRQSTATUSSection 17.4.35
90hAES_IRQENABLESection 17.4.36
B8hCRYPTOCLKENSection 17.4.37
820hDTHE_AES_IMAES Interrupt Mask Set registerSection 17.4.38
824hDTHE_AES_RISAES Interrupt Raw Interrupt Status registerSection 17.4.39
828hDTHE_AES_MISAES Interrupt Masked interrupt Status registerSection 17.4.40
82ChDTHE_AES_ICAES Interrupt Clear Interrupt Status registerSection 17.4.41

17.4.1 AES_KEY2_6 Register (Offset = 0h) [reset = 0h]

AES_KEY2_6 is shown in Figure 17-14 and described in Table 17-4.

Return to Summary Table.

XTS second key, CBC-MAC third key.

Figure 17-14 AES_KEY2_6 Register
313029282726252423222120191817161514131211109876543210
KEY
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-4 AES_KEY2_6 Register Field Descriptions
BitFieldTypeResetDescription
31-0KEYR/W0h

Key data

17.4.2 AES_KEY2_7 Register (Offset = 4h) [reset = 0h]

AES_KEY2_7 is shown in Figure 17-15 and described in Table 17-5.

Return to Summary Table.

XTS second key (MSW for 256-bit key), CBC-MAC third key (MSW).

Figure 17-15 AES_KEY2_7 Register
313029282726252423222120191817161514131211109876543210
KEY
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-5 AES_KEY2_7 Register Field Descriptions
BitFieldTypeResetDescription
31-0KEYR/W0h

Key data

17.4.3 AES_KEY2_4 Register (Offset = 8h) [reset = 0h]

AES_KEY2_4 is shown in Figure 17-16 and described in Table 17-6.

Return to Summary Table.

XTS/CCM second key, CBC-MAC third key (LSW).

Figure 17-16 AES_KEY2_4 Register
313029282726252423222120191817161514131211109876543210
KEY
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-6 AES_KEY2_4 Register Field Descriptions
BitFieldTypeResetDescription
31-0KEYR/W0h

Key data

17.4.4 AES_KEY2_5 Register (Offset = Ch) [reset = 0h]

AES_KEY2_5 is shown in Figure 17-17 and described in Table 17-7.

Return to Summary Table.

XTS second key (MSW for 192-bit key), CBC-MAC third key.

Figure 17-17 AES_KEY2_5 Register
313029282726252423222120191817161514131211109876543210
KEY
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-7 AES_KEY2_5 Register Field Descriptions
BitFieldTypeResetDescription
31-0KEYR/W0h

Key data

17.4.5 AES_KEY2_2 Register (Offset = 10h) [reset = 0h]

AES_KEY2_2 is shown in Figure 17-18 and described in Table 17-8.

Return to Summary Table.

XTS/CCM/CBC-MAC second key, hash key input

Figure 17-18 AES_KEY2_2 Register
313029282726252423222120191817161514131211109876543210
KEY
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-8 AES_KEY2_2 Register Field Descriptions
BitFieldTypeResetDescription
31-0KEYR/W0h

Key data

17.4.6 AES_KEY2_3 Register (Offset = 14h) [reset = 0h]

AES_KEY2_3 is shown in Figure 17-19 and described in Table 17-9.

Return to Summary Table.

XTS second key (MSW for 128-bit key), CCM/CBC-MAC second key (MSW), hash key input (MSW).

Figure 17-19 AES_KEY2_3 Register
313029282726252423222120191817161514131211109876543210
KEY
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-9 AES_KEY2_3 Register Field Descriptions
BitFieldTypeResetDescription
31-0KEYR/W0h

Key data

17.4.7 AES_KEY2_0 Register (Offset = 18h) [reset = 0h]

AES_KEY2_0 is shown in Figure 17-20 and described in Table 17-10.

Return to Summary Table.

XTS/CCM/CBC-MAC second key (LSW), hash key input (LSW).

Figure 17-20 AES_KEY2_0 Register
313029282726252423222120191817161514131211109876543210
KEY
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-10 AES_KEY2_0 Register Field Descriptions
BitFieldTypeResetDescription
31-0KEYR/W0h

Key data

17.4.8 AES_KEY2_1 Register (Offset = 1Ch) [reset = 0h]

AES_KEY2_1 is shown in Figure 17-21 and described in Table 17-11.

Return to Summary Table.

XTS/CCM/CBC-MAC second key (LSW), hash key input.

Figure 17-21 AES_KEY2_1 Register
313029282726252423222120191817161514131211109876543210
KEY
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-11 AES_KEY2_1 Register Field Descriptions
BitFieldTypeResetDescription
31-0KEYR/W0h

Key data

17.4.9 AES_KEY1_6 Register (Offset = 20h) [reset = 0h]

AES_KEY1_6 is shown in Figure 17-22 and described in Table 17-12.

Return to Summary Table.

Key (LSW for 256-bit key)

Figure 17-22 AES_KEY1_6 Register
313029282726252423222120191817161514131211109876543210
KEY
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-12 AES_KEY1_6 Register Field Descriptions
BitFieldTypeResetDescription
31-0KEYR/W0h

Key data

17.4.10 AES_KEY1_7 Register (Offset = 24h) [reset = 0h]

AES_KEY1_7 is shown in Figure 17-23 and described in Table 17-13.

Return to Summary Table.

Key (MSW for 256-bit key)

Figure 17-23 AES_KEY1_7 Register
313029282726252423222120191817161514131211109876543210
KEY
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-13 AES_KEY1_7 Register Field Descriptions
BitFieldTypeResetDescription
31-0KEYR/W0h

Key data

17.4.11 AES_KEY1_4 Register (Offset = 28h) [reset = 0h]

AES_KEY1_4 is shown in Figure 17-24 and described in Table 17-14.

Return to Summary Table.

Key (LSW for 192-bit key)

Figure 17-24 AES_KEY1_4 Register
313029282726252423222120191817161514131211109876543210
KEY
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-14 AES_KEY1_4 Register Field Descriptions
BitFieldTypeResetDescription
31-0KEYR/W0h

Key data

17.4.12 AES_KEY1_5 Register (Offset = 2Ch) [reset = 0h]

AES_KEY1_5 is shown in Figure 17-25 and described in Table 17-15.

Return to Summary Table.

Key (MSW for 192-bit key)

Figure 17-25 AES_KEY1_5 Register
313029282726252423222120191817161514131211109876543210
KEY
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-15 AES_KEY1_5 Register Field Descriptions
BitFieldTypeResetDescription
31-0KEYR/W0h

Key data

17.4.13 AES_KEY1_2 Register (Offset = 30h) [reset = 0h]

AES_KEY1_2 is shown in Figure 17-26 and described in Table 17-16.

Return to Summary Table.

Key ? Missing content here?

Figure 17-26 AES_KEY1_2 Register
313029282726252423222120191817161514131211109876543210
KEY
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-16 AES_KEY1_2 Register Field Descriptions
BitFieldTypeResetDescription
31-0KEYR/W0h

Key data

17.4.14 AES_KEY1_3 Register (Offset = 34h) [reset = 0h]

AES_KEY1_3 is shown in Figure 17-27 and described in Table 17-17.

Return to Summary Table.

Key (MSW for 128-bit key)

Figure 17-27 AES_KEY1_3 Register
313029282726252423222120191817161514131211109876543210
KEY
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-17 AES_KEY1_3 Register Field Descriptions
BitFieldTypeResetDescription
31-0KEYR/W0h

Key data

17.4.15 AES_KEY1_0 Register (Offset = 38h) [reset = 0h]

AES_KEY1_0 is shown in Figure 17-28 and described in Table 17-18.

Return to Summary Table.

Key (LSW for 128-bit key)

Figure 17-28 AES_KEY1_0 Register
313029282726252423222120191817161514131211109876543210
KEY
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-18 AES_KEY1_0 Register Field Descriptions
BitFieldTypeResetDescription
31-0KEYR/W0h

Key data

17.4.16 AES_KEY1_1 Register (Offset = 3Ch) [reset = 0h]

AES_KEY1_1 is shown in Figure 17-29 and described in Table 17-19.

Return to Summary Table.

Key ? Missing content here?

Figure 17-29 AES_KEY1_1 Register
313029282726252423222120191817161514131211109876543210
KEY
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-19 AES_KEY1_1 Register Field Descriptions
BitFieldTypeResetDescription
31-0KEYR/W0h

Key data

17.4.17 AES_IV_IN_0 Register (Offset = 40h) [reset = 0h]

AES_IV_IN_0 is shown in Figure 17-30 and described in Table 17-20.

Return to Summary Table.

Initialization vector input (LSW)

Figure 17-30 AES_IV_IN_0 Register
313029282726252423222120191817161514131211109876543210
DATA
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-20 AES_IV_IN_0 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0h

IV data

17.4.18 AES_IV_IN_1 Register (Offset = 44h) [reset = 0h]

AES_IV_IN_1 is shown in Figure 17-31 and described in Table 17-21.

Return to Summary Table.

Initialization vector input

Figure 17-31 AES_IV_IN_1 Register
313029282726252423222120191817161514131211109876543210
DATA
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-21 AES_IV_IN_1 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0h

IV data

17.4.19 AES_IV_IN_2 Register (Offset = 48h) [reset = 0h]

AES_IV_IN_2 is shown in Figure 17-32 and described in Table 17-22.

Return to Summary Table.

Initialization vector input

Figure 17-32 AES_IV_IN_2 Register
313029282726252423222120191817161514131211109876543210
DATA
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-22 AES_IV_IN_2 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0h

IV data

17.4.20 AES_IV_IN_3 Register (Offset = 4Ch) [reset = 0h]

AES_IV_IN_3 is shown in Figure 17-33 and described in Table 17-23.

Return to Summary Table.

Initialization vector input (MSW)

Figure 17-33 AES_IV_IN_3 Register
313029282726252423222120191817161514131211109876543210
DATA
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-23 AES_IV_IN_3 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0h

IV data

17.4.21 AES_CTRL Register (Offset = 50h) [reset = X]

AES_CTRL is shown in Figure 17-34 and described in Table 17-24.

Return to Summary Table.

Determines the mode of operation of the AES engine.

Figure 17-34 AES_CTRL Register
3130292827262524
CONTEXT_READYSAVE_CONTEXT_READYSAVE_CONTEXTRESERVEDCCM_M
RO-1hRO-0hR/W-0hR-XR/W-0h
2322212019181716
CCM_MCCM_LCCMGCM
R/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
CBCMACF9F8XTSCFBICMCTR_WIDTH
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
CTR_WIDTHCTRMODEKEY_SIZEDIRECTIONINPUT_READYOUTPUT_READY
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hRO-0hRO-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-24 AES_CTRL Register Field Descriptions
BitFieldTypeResetDescription
31CONTEXT_READYRO1h

If 1, this read-only status bit indicates that the context data registers can be overwritten, and the host is permitted to write the next context.

30SAVE_CONTEXT_READYRO0h

If 1, this read-only status bit indicates that an AES authentication TAG or IV blocks are available for the host to retrieve. This bit is only asserted if the ‘save_context’ bit is set to 1. The bit is mutually exclusive with the ‘context_ready’ bit.

29SAVE_CONTEXTR/W0h

This bit indicates that an authentication TAG or result IV must be stored as a result context. If this bit is set, context output DMA or interrupt are asserted if the operation is finished and related signals are enabled.

28-25RESERVEDRX
24-22CCM_MR/W0h

Defines “M” that indicated the length of the authentication field for CCM operations; the authentication field length equals two times (the value of CCM-M plus one). The AES engine always returns a 128-bit authentication field, of which the M least significant bytes are valid. All values are supported.

21-19CCM_LR/W0h

Defines “L” that indicated the width of the length field for CCM operations; the length field in bytes equals the value of CMM-L plus one. Supported values for L are (programmed value): 2 (1), 4 (3) and 8 (7).

18CCMR/W0h

AES-CCM is selected; this is a combined mode, using AES for both authentication and encryption. No additional mode selection is required.

0h = Other mode selected

1h = CCM mode selected

17-16GCMR/W0h

AES-GCM mode is selected; this is a combined mode, using the Galois field multiplier GF(2128) for authentication and AES-CTR mode for encryption, the bits specify the GCM mode.

0h = No operation

1h = GHASH with H loaded and Y0-encrypted forced to zero

2h = GHASH with H loaded and Y0-encrypted calculated internally

3h = Autonomous GHASH (both H and Y0-encrypted calculated internally)

15CBCMACR/W0h

AES-CBC MAC is selected; the Direction bit must be set to 1 for this mode.

0h = Other mode selected

1h = CBCMAC mode selected

14F9R/W0h

AES f9 mode is selected; the AES key size must be set to 128-bit for this mode.

0h = Other mode selected

1h = f9 selected

13F8R/W0h

AES f8 mode is selected; the AES key size must be set to 128-bit for this mode.

0h = Other mode selected

1h = f8 selected

12-11XTSR/W0h

AES-XTS operation is selected; the bits specify the XTS mode.

0h = No operation

1h = Previous/intermediate tweak value and j loaded (value is loaded through IV, j is loaded through the AAD length register)

2h = Key2, i and j loaded (i is loaded through IV, j is loaded through the AAD length register)

3h = Key2 and i loaded, j=0 (i is loaded through IV)

10CFBR/W0h

Full block AES cipher feedback mode (CFB128) is selected.

0h = Other mode selected

1h = CFB selected

9ICMR/W0h

AES integer counter mode (ICM) is selected, this is a counter mode with a 16-bit wide counter.

0h = Other mode selected

1h = ICM mode selected

8-7CTR_WIDTHR/W0h

Specifies the counter width for AES-CTR mode

0h = Counter is 32 bits

1h = Counter is 64 bits

2h = Counter is 128 bits

3h = Counter is 192 bits

6CTRR/W0h

This bit must also be set for GCM and CCM, when encryption or decryption is required.

0h = Other mode selected

1h = Counter mode

5MODER/W0h

ECB/CBC mode

0h = ECB mode

1h = CBC mode

4-3KEY_SIZER/W0h

Key Size

0h = Reserved

1h = Key is 128 bits

2h = Key is 192 bits

3h = Key is 256

2DIRECTIONR/W0h

If set to 1, an encrypt operation is performed. If set to 0, a decrypt operation is performed.

0h = Decryption is selected

1h = Encryption is selected

1INPUT_READYRO0h

If 1, this read-only status bit indicates that the 16-byte input buffer is empty, and the host is permitted to write the next block of data.

0OUTPUT_READYRO0h

If 1, this read-only status bit indicates that an AES output block is available for the host to retrieve.

17.4.22 AES_C_LENGTH_0 Register (Offset = 54h) [reset = 0h]

AES_C_LENGTH_0 is shown in Figure 17-35 and described in Table 17-25.

Return to Summary Table.

Crypto data length registers (LSW and MSW) store the cryptographic data length in bytes for all modes. Once processing with this context is started, this length decrements to zero. Data lengths up to (261 – 1) bytes are allowed.

For GCM, any value up to 236 – 32 bytes can be used. This is because a 32-bit counter mode is used; the maximum number of 128-bit blocks is 232 – 2, resulting in a maximum number of bytes of 236 – 32.

A write to this register triggers the engine to start using this context. This is valid for all modes except GCM and CCM.

For the combined modes, this length does not include the authentication-only data; the authentication length is specified in the AES_AUTH_LENGTH register below.

All modes must have a length > 0. For the combined modes, it is allowed to have one of the lengths equal to zero.

For the basic encryption modes (ECB/CBC/CTR/ICM/CFB128) it is allowed to program zero to the length field; in that case the length is assumed infinite.

All data must be byte (8-bit) aligned; bit aligned data streams are not supported by the AES Engine.

For a host read operation, these registers return all-zeroes.

Figure 17-35 AES_C_LENGTH_0 Register
313029282726252423222120191817161514131211109876543210
LENGTH
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-25 AES_C_LENGTH_0 Register Field Descriptions
BitFieldTypeResetDescription
31-0LENGTHR/W0h

Data length (LSW)

17.4.23 AES_C_LENGTH_1 Register (Offset = 58h) [reset = X]

AES_C_LENGTH_1 is shown in Figure 17-36 and described in Table 17-26.

Return to Summary Table.

Crypto data length registers (LSW and MSW) store the cryptographic data length in bytes for all modes. Once processing with this context is started, this length decrements to zero. Data lengths up to (261 – 1) bytes are allowed.

For GCM, any value up to 236 – 32 bytes can be used. This is because a 32-bit counter mode is used; the maximum number of 128-bit blocks is 232 – 2, resulting in a maximum number of bytes of 236 – 32.

A write to this register triggers the engine to start using this context. This is valid for all modes except GCM and CCM.

For the combined modes, this length does not include the authentication-only data; the authentication length is specified in the AES_AUTH_LENGTH register below.

All modes must have a length > 0. For the combined modes, it is allowed to have one of the lengths equal to zero.

For the basic encryption modes (ECB/CBC/CTR/ICM/CFB128) it is allowed to program zero to the length field; in that case the length is assumed infinite.

All data must be byte (8-bit) aligned; bit aligned data streams are not supported by the AES Engine.

For a host read operation, these registers return all-zeroes.

Figure 17-36 AES_C_LENGTH_1 Register
31302928272625242322212019181716
RESERVEDLENGTH
R-XR/W-0h
1514131211109876543210
LENGTH
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-26 AES_C_LENGTH_1 Register Field Descriptions
BitFieldTypeResetDescription
31-29RESERVEDRX
28-0LENGTHR/W0h

Data length (MSW)

17.4.24 AES_AUTH_LENGTH Register (Offset = 5Ch) [reset = 0h]

AES_AUTH_LENGTH is shown in Figure 17-37 and described in Table 17-27.

Return to Summary Table.

AAD data length. The authentication length register store the authentication data length in bytes for combined modes only (GCM or CCM).

Supported AAD-lengths for CCM are from 0 to (216 – 28) bytes. For GCM any value up to (232 – 1) bytes can be used. Once processing with this context is started, this length decrements to zero.

A write to this register triggers the engine to start using this context for GCM and CCM. For XTS this register is optionally used to load ‘j’. Loading of ‘j’ is only required if ‘j’ != 0. ‘j’ is a 28-bit value and must be written to bits [31-4] of this register. ‘j’ represents the sequential number of the 128-bit block inside the data unit. For the first block in a unit, this value is zero. It is not required to provide a ‘j’ for each new data block within a unit. It is possible to start with a ‘j’ unequal to zero. For a Host read operation, these registers return all-zeroes.

Figure 17-37 AES_AUTH_LENGTH Register
313029282726252423222120191817161514131211109876543210
AUTH
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-27 AES_AUTH_LENGTH Register Field Descriptions
BitFieldTypeResetDescription
31-0AUTHR/W0h

Data

17.4.25 AES_DATA_IN_0 Register (Offset = 60h) [reset = 0h]

AES_DATA_IN_0 is shown in Figure 17-38 and described in Table 17-28.

Return to Summary Table.

Data register to read and write plaintext and ciphertext (MSW).

Figure 17-38 AES_DATA_IN_0 Register
313029282726252423222120191817161514131211109876543210
DATA
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-28 AES_DATA_IN_0 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0h

Data to encrypt or decrypt

17.4.26 AES_DATA_IN_1 Register (Offset = 64h) [reset = 0h]

AES_DATA_IN_1 is shown in Figure 17-39 and described in Table 17-29.

Return to Summary Table.

Data register to read and write plaintext and ciphertext.

Figure 17-39 AES_DATA_IN_1 Register
313029282726252423222120191817161514131211109876543210
DATA
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-29 AES_DATA_IN_1 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0h

Data to encrypt or decrypt

17.4.27 AES_DATA_IN_2 Register (Offset = 68h) [reset = 0h]

AES_DATA_IN_2 is shown in Figure 17-40 and described in Table 17-30.

Return to Summary Table.

Data register to read and write plaintext and ciphertext.

Figure 17-40 AES_DATA_IN_2 Register
313029282726252423222120191817161514131211109876543210
DATA
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-30 AES_DATA_IN_2 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0h

Data to encrypt or decrypt

17.4.28 AES_DATA_IN_3 Register (Offset = 6Ch) [reset = 0h]

AES_DATA_IN_3 is shown in Figure 17-41 and described in Table 17-31.

Return to Summary Table.

Data register to read and write plaintext and ciphertext (LSW).

Figure 17-41 AES_DATA_IN_3 Register
313029282726252423222120191817161514131211109876543210
DATA
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-31 AES_DATA_IN_3 Register Field Descriptions
BitFieldTypeResetDescription
31-0DATAR/W0h

Data to encrypt or decrypt

17.4.29 AES_TAG_OUT_0 Register (Offset = 70h) [reset = 0h]

AES_TAG_OUT_0 is shown in Figure 17-42 and described in Table 17-32.

Return to Summary Table.

Figure 17-42 AES_TAG_OUT_0 Register
313029282726252423222120191817161514131211109876543210
HASH
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-32 AES_TAG_OUT_0 Register Field Descriptions
BitFieldTypeResetDescription
31-0HASHR/W0h

Hash result (MSW)

17.4.30 AES_TAG_OUT_1 Register (Offset = 74h) [reset = 0h]

AES_TAG_OUT_1 is shown in Figure 17-43 and described in Table 17-33.

Return to Summary Table.

Figure 17-43 AES_TAG_OUT_1 Register
313029282726252423222120191817161514131211109876543210
HASH
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-33 AES_TAG_OUT_1 Register Field Descriptions
BitFieldTypeResetDescription
31-0HASHR/W0h

Hash result (MSW)

17.4.31 AES_TAG_OUT_2 Register (Offset = 78h) [reset = 0h]

AES_TAG_OUT_2 is shown in Figure 17-44 and described in Table 17-34.

Return to Summary Table.

Figure 17-44 AES_TAG_OUT_2 Register
313029282726252423222120191817161514131211109876543210
HASH
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-34 AES_TAG_OUT_2 Register Field Descriptions
BitFieldTypeResetDescription
31-0HASHR/W0h

Hash result (MSW)

17.4.32 AES_TAG_OUT_3 Register (Offset = 7Ch) [reset = 0h]

AES_TAG_OUT_3 is shown in Figure 17-45 and described in Table 17-35.

Return to Summary Table.

Figure 17-45 AES_TAG_OUT_3 Register
313029282726252423222120191817161514131211109876543210
HASH
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-35 AES_TAG_OUT_3 Register Field Descriptions
BitFieldTypeResetDescription
31-0HASHR/W0h

Hash result (LSW)

17.4.33 AES_REVISION Register (Offset = 80h) [reset = X]

AES_REVISION is shown in Figure 17-46 and described in Table 17-36.

Return to Summary Table.

Figure 17-46 AES_REVISION Register
3130292827262524
SCHEMERESERVEDFUNC
RO-0hR-XRO-0h
2322212019181716
FUNC
RO-0h
15141312111098
R_RTLX_MAJOR
RO-0hRO-0h
76543210
CUSTOMY_MINOR
RO-0hRO-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-36 AES_REVISION Register Field Descriptions
BitFieldTypeResetDescription
31-30SCHEMERO0h

Used to distinguish between old scheme and current.

0h = (Read): Legacy ASP or WTBU scheme

1h = (Read): Highlander 0.8 scheme

29-28RESERVEDRX
27-16FUNCRO0h

Function indicates a software compatible module family. If there is no level of software compatibility, a new Func number (and hence REVISION) should be assigned.

15-11R_RTLRO0h

RTL Version (R), maintained by IP design owner.

RTL follows a numbering such as X.Y.R.Z which are explained in this table.

R changes ONLY when:

(1) PDS uploads occur which may have been due to spec changes

(2) Bug fixes occur

(3) Resets to 0 when X or Y changes.

Design team has an internal Z (customer-invisible) number which increments on every drop that happens due to DV and RTL updates. Z resets to 0 when R increments.

10-8X_MAJORRO0h

Major Revision (X), maintained by IP specification owner.

X changes ONLY when:

(1) There is a major feature addition. An example would be adding master mode to Utopia Level2. The Func field (or class/type in old PID format) remains the same.

X does NOT change due to:

(1) Bug fixes

(2) Change in feature parameters.

7-6CUSTOMRO0h

Indicates a special version for a particular device. Consequence of use may avoid use of standard Chip Support Library (CSL) / Drivers.

0h = (Read): Non-custom (standard) revision

5-0Y_MINORRO0h

Minor Revision (Y), maintained by IP specification owner.

Y changes ONLY when:

(1) Features are scaled (up or down). Flexibility exists in that this feature scalability may either be represented in the Y change or a specific register in the IP that indicates which features are exactly available.

(2) When feature creeps from Is-Not list to Is list. But this may not be the case once it sees silicon; in which case X changes.

Y does NOT change due to:

(1) Bug fixes

(2) Typos or clarifications

(3) major functional or feature changes, additions, and deletions. Instead, these changes may be reflected through R, S, and X, as applicable.

Spec owner maintains a customer-invisible number 'S' which changes due to:

(1) Typos and clarifications

(2) Bug documentation. Note that this bug is not due to a spec change but due to implementation. Nevertheless, the spec tracks the IP bugs. An RTL release (say for silicon PG1.1) that occurs due to bug fix should document the corresponding spec number (X.Y.S) in its release notes.

17.4.34 AES_SYSCONFIG Register (Offset = 84h) [reset = X]

AES_SYSCONFIG is shown in Figure 17-47 and described in Table 17-37.

Return to Summary Table.

This register configures the DMA signals.

Figure 17-47 AES_SYSCONFIG Register
3130292827262524
RESERVED
R-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVEDMAP_CONTEXT_OUT_ON_DATA_OUTDMA_REQ_CONTEXT_OUT_EN
R-XR/W-0hR/W-0h
76543210
DMA_REQ_CONTEXT_IN_ENDMA_REQ_DATA_OUT_ENDMA_REQ_DATA_IN_ENRESERVED
R/W-0hR/W-0hR/W-0hR-X
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-37 AES_SYSCONFIG Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDRX
9MAP_CONTEXT_OUT_ON_DATA_OUTR/W0h

If set to 1, the two context out requests (dma_req_context_out_en, Bit [8] above, and context_out interrupt enable, Bit [3] of AES_IRQENABLE register) are mapped on the corresponding data output request bit. In this case, the original ‘context out’ bit values are ignored.

8DMA_REQ_CONTEXT_OUT_ENR/W0h

If set to 1, the DMA context output request is enabled (for context data out, for example, TAG for authentication modes).

0h = DMA disabled

1h = DMA enabled

7DMA_REQ_CONTEXT_IN_ENR/W0h

If set to 1, the DMA context request is enabled.

0h = DMA disabled

1h = DMA enabled

6DMA_REQ_DATA_OUT_ENR/W0h

If set to 1, the DMA output request is enabled.

0h = DMA disabled

1h = DMA enabled

5DMA_REQ_DATA_IN_ENR/W0h

If set to 1, the DMA input request is enabled.

0h = DMA disabled

1h = DMA enabled

4-0RESERVEDRX

17.4.35 AES_IRQSTATUS Register (Offset = 8Ch) [reset = X]

AES_IRQSTATUS is shown in Figure 17-48 and described in Table 17-38.

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This register indicates the interrupt status. If one of the interrupt bits is set, the interrupt output is asserted.

Figure 17-48 AES_IRQSTATUS Register
3130292827262524
RESERVED
R-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVED
R-X
76543210
RESERVEDCONTEXT_OUTDATA_OUTDATA_INCONTEXT_IN
R-XR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-38 AES_IRQSTATUS Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDRX
3CONTEXT_OUTR/W0h

This bit indicates authentication tag (and IV) interrupts are active, and triggers the interrupt output.

2DATA_OUTR/W0h

This bit indicates data output interrupt is active, and triggers the interrupt output

1DATA_INR/W0h

This bit indicates data input interrupt is active, and triggers the interrupt output

0CONTEXT_INR/W0h

This bit indicates context interrupt is active, and triggers the interrupt output.

17.4.36 AES_IRQENABLE Register (Offset = 90h) [reset = X]

AES_IRQENABLE is shown in Figure 17-49 and described in Table 17-39.

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This register contains an enable bit for each unique interrupt generated by the module. It matches the layout of AES_IRQSTATUS register. An interrupt is enabled when the bit in this register is set to 1. An interrupt that is enabled is propagated to the SINTREQUEST_x output. All interrupts must be enabled explicitly by writing this register.

Figure 17-49 AES_IRQENABLE Register
3130292827262524
RESERVED
R-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVED
R-X
76543210
RESERVEDCONTEXT_OUTDATA_OUTDATA_INCONTEXT_IN
R-XR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-39 AES_IRQENABLE Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDRX
3CONTEXT_OUTR/W0h

This bit indicates authentication tag (and IV) interrupts are active, and triggers the interrupt output.

2DATA_OUTR/W0h

This bit indicates data output interrupt is active, and triggers the interrupt output

1DATA_INR/W0h

This bit indicates data input interrupt is active, and triggers the interrupt output

0CONTEXT_INR/W0h

This bit indicates context interrupt is active, and triggers the interrupt output.

17.4.37 CRYPTOCLKEN Register (Offset = B8h) [reset = X]

CRYPTOCLKEN is shown in Figure 17-50 and described in Table 17-40.

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Physical address: 0x4402 50B8. CRYPTO_CLK_GATING

Figure 17-50 CRYPTOCLKEN Register
3130292827262524
RESERVED
R-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVED
R-X
76543210
RESERVEDRUNCLKEN
R-XR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-40 CRYPTOCLKEN Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDRX
0RUNCLKENR/W0h

CRYPTO_RUN_CLK_ENABLE:

0h = Enable the crypto clock during run

1h = Disable the crypto clock during run

17.4.38 DTHE_AES_IM Register (Offset = 820h) [reset = X]

DTHE_AES_IM is shown in Figure 17-51 and described in Table 17-41.

Return to Summary Table.

The interrupt mask set register controls which interrupt source interrupts the processor.

Figure 17-51 DTHE_AES_IM Register
3130292827262524
RESERVED
R-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVED
R-X
76543210
RESERVEDDoutDinCoutCin
R-XR/W-1hR/W-1hR/W-1hR/W-1h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-41 DTHE_AES_IM Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDRX
3DoutR/W1h

Data out: This interrupt is raised when DMA finishes writing last word of the process result.

2DinR/W1h

Data in: This interrupt is raised when DMA writes last word of input data to internal FIFO of the engine.

1CoutR/W1h

Context out: This interrupt is raised when DMA completes the output context movement from internal register.

0CinR/W1h

Context in: This interrupt is raised when DMA completes context write to internal register.

17.4.39 DTHE_AES_RIS Register (Offset = 824h) [reset = X]

DTHE_AES_RIS is shown in Figure 17-52 and described in Table 17-42.

Return to Summary Table.

AES Raw Interrupt status register.

Figure 17-52 DTHE_AES_RIS Register
3130292827262524
RESERVED
R-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVED
R-X
76543210
RESERVEDDoutDinCoutCin
R-XR-0hR-0hR-0hR-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-42 DTHE_AES_RIS Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDRX
3DoutR0h

Output data movement is done

2DinR0h

Input data movement is done

1CoutR0h

Context output is done

0CinR0h

Context input is done

17.4.40 DTHE_AES_MIS Register (Offset = 828h) [reset = X]

DTHE_AES_MIS is shown in Figure 17-53 and described in Table 17-43.

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Figure 17-53 DTHE_AES_MIS Register
3130292827262524
RESERVED
R-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVED
R-X
76543210
RESERVEDDoutDinCoutCin
R-XR-0hR-0hR-0hR-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-43 DTHE_AES_MIS Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDRX
3DoutR0h

Output data movement is done

2DinR0h

Input data movement is done

1CoutR0h

Context output is done

0CinR0h

Context input is done

17.4.41 DTHE_AES_IC Register (Offset = 82Ch) [reset = X]

DTHE_AES_IC is shown in Figure 17-54 and described in Table 17-44.

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Figure 17-54 DTHE_AES_IC Register
3130292827262524
RESERVED
R-X
2322212019181716
RESERVED
R-X
15141312111098
RESERVED
R-X
76543210
RESERVEDDoutDinCoutCin
R-XWC-0hWC-0hWC-0hWC-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 17-44 DTHE_AES_IC Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDRX
3DoutWC0h

Clear “output data movement done” flag

2DinWC0h

Clear “input data movement done” flag

1CoutWC0h

Clear “context output done” flag

0CinWC0h

Clear “context input done” flag