SWRU543B January   2019  – June 2025 CC3230S , CC3230SF , CC3235MODS , CC3235MODSF , CC3235S , CC3235SF

 

  1.   1
  2.   Read This First
    1.     Audience
    2.     About This Manual
    3.     Register Bit Conventions
    4.     Glossary
    5.     Related Documentation
    6.     Community Resources
    7.     Trademarks
  3. 1 Architecture Overview
    1. 1.1 Introduction
    2. 1.2 Architecture Overview
    3. 1.3 Functional Overview
      1. 1.3.1  Processor Core
        1. 1.3.1.1 Arm® Cortex®-M4 Processor Core
        2. 1.3.1.2 System Timer (SysTick)
        3. 1.3.1.3 Nested Vector Interrupt Controller (NVIC)
        4. 1.3.1.4 System Control Block
      2. 1.3.2  Memory
        1. 1.3.2.1 On-Chip SRAM
        2. 1.3.2.2 ROM
        3. 1.3.2.3 Flash Memory
      3. 1.3.3  Micro-Direct Memory Access Controller (µDMA)
      4. 1.3.4  General-Purpose Timer (GPT)
      5. 1.3.5  Watchdog Timer (WDT)
      6. 1.3.6  Multichannel Audio Serial Port (McASP)
      7. 1.3.7  Serial Peripheral Interface (SPI)
      8. 1.3.8  Inter-Integrated Circuit (I2C) Interface
      9. 1.3.9  Universal Asynchronous Receiver/Transmitter (UART)
      10. 1.3.10 General-Purpose Input/Output (GPIO)
      11. 1.3.11 Analog-to-Digital Converter (ADC)
      12. 1.3.12 SD Card Host
      13. 1.3.13 Parallel Camera Interface
      14. 1.3.14 Debug Interface
      15. 1.3.15 Hardware Cryptography Accelerator
      16. 1.3.16 Clock, Reset, and Power Management
      17. 1.3.17 SimpleLink™ Subsystem
      18. 1.3.18 I/O Pads and Pin Multiplexing
  4. 2 Cortex®-M4 Processor
    1. 2.1 Overview
      1. 2.1.1 Block Diagram
      2. 2.1.2 System-Level Interface
      3. 2.1.3 Integrated Configurable Debug
      4. 2.1.4 Trace Port Interface Unit (TPIU)
      5. 2.1.5 Cortex®-M4 System Component Details
    2. 2.2 Functional Description
      1. 2.2.1 Programming Model
        1. 2.2.1.1 Processor Mode and Privilege Levels for Software Execution
        2. 2.2.1.2 Stacks
      2. 2.2.2 Register Description
        1. 2.2.2.1 Register Map
        2. 2.2.2.2 Register Descriptions
          1. 2.2.2.2.1 Stack Pointer (SP)
          2. 2.2.2.2.2 Link Register (LR)
          3. 2.2.2.2.3 Program Counter (PC)
          4. 2.2.2.2.4 Program Status Register (PSR)
          5. 2.2.2.2.5 Priority Mask Register (PRIMASK)
          6. 2.2.2.2.6 Fault Mask Register (FAULTMASK)
          7. 2.2.2.2.7 Base Priority Mask Register (BASEPRI)
          8. 2.2.2.2.8 Control Register (CONTROL)
        3. 2.2.2.3 Exceptions and Interrupts
        4. 2.2.2.4 Data Types
      3. 2.2.3 Memory Model
        1. 2.2.3.1 Bit-Banding
          1. 2.2.3.1.1 Directly Accessing an Alias Region
          2. 2.2.3.1.2 Directly Accessing a Bit-Band Region
        2. 2.2.3.2 Data Storage
        3. 2.2.3.3 Synchronization Primitives
      4. 2.2.4 Exception Model
        1. 2.2.4.1 Exception States
        2. 2.2.4.2 Exception Types
        3. 2.2.4.3 Exception Handlers
        4. 2.2.4.4 Vector Table
        5. 2.2.4.5 Exception Priorities
        6. 2.2.4.6 Interrupt Priority Grouping
        7. 2.2.4.7 Exception Entry and Return
          1. 2.2.4.7.1 Exception Entry
      5. 2.2.5 Fault Handling
        1. 2.2.5.1 Fault Types
        2. 2.2.5.2 Fault Escalation and Hard Faults
        3. 2.2.5.3 Fault Status Registers and Fault Address Registers
        4. 2.2.5.4 Lockup State
      6. 2.2.6 Power Management
      7. 2.2.7 Instruction Set Summary
  5. 3 Cortex®-M4 Peripherals
    1. 3.1 Overview
    2. 3.2 Functional Description
      1. 3.2.1 System Timer (SysTick)
      2. 3.2.2 Nested Vectored Interrupt Controller (NVIC)
        1. 3.2.2.1 Level-Sensitive and Pulse Interrupts
        2. 3.2.2.2 Hardware and Software Control of Interrupts
      3. 3.2.3 System Control Block (SCB)
    3. 3.3 Register Map
      1. 3.3.1 Cortex Registers
  6. 4 Direct Memory Access (DMA)
    1. 4.1 Overview
    2. 4.2 Functional Description
      1. 4.2.1 Channel Assignment
      2. 4.2.2 Priority
      3. 4.2.3 Arbitration Size
      4. 4.2.4 Channel Configuration
      5. 4.2.5 Transfer Mode
        1. 4.2.5.1 Stop Mode
        2. 4.2.5.2 Basic Mode
        3. 4.2.5.3 Auto Mode
        4. 4.2.5.4 Ping-Pong Mode
        5. 4.2.5.5 Memory Scatter-Gather Mode
        6. 4.2.5.6 Peripheral Scatter-Gather Mode
      6. 4.2.6 Transfer Size and Increment
      7. 4.2.7 Peripheral Interface
        1. 4.2.7.1 FIFO Peripherals
        2. 4.2.7.2 Trigger Peripherals
        3. 4.2.7.3 Software Request
      8. 4.2.8 Interrupts and Errors
    3. 4.3 Register Description
      1. 4.3.1 DMA Register Map
      2. 4.3.2 µDMA Channel Control Structure
      3. 4.3.3 DMA Registers
      4. 4.3.4 DMA_(OFFSET_FROM_DMA_BASE_ADDRESS) Registers
  7. 5 General-Purpose Input/Outputs (GPIOs)
    1. 5.1 Overview
    2. 5.2 Functional Description
      1. 5.2.1 Data Control
        1. 5.2.1.1 Data Direction Operation
        2. 5.2.1.2 Data Register Operation
    3. 5.3 Interrupt Control
      1. 5.3.1 µDMA Trigger Source
    4. 5.4 Initialization and Configuration
    5. 5.5 GPIO Registers
  8. 6 Universal Asynchronous Receivers/Transmitters (UARTs)
    1. 6.1 Overview
      1. 6.1.1 Block Diagram
    2. 6.2 Functional Description
      1. 6.2.1 Transmit and Receive Logic
      2. 6.2.2 Baud-Rate Generation
      3. 6.2.3 Data Transmission
        1. 6.2.3.1 Flow Control
          1. 6.2.3.1.1 Hardware Flow Control (RTS/CTS)
          2. 6.2.3.1.2 Software Flow Control (Modem Status Interrupts)
        2. 6.2.3.2 FIFO Operation
        3. 6.2.3.3 Interrupts
        4. 6.2.3.4 LoopbackOperation
        5. 6.2.3.5 DMA Operation
      4. 6.2.4 Initialization and Configuration
    3. 6.3 UART Registers
  9. 7 Inter-Integrated Circuit (I2C) Interface
    1. 7.1 Overview
      1. 7.1.1 Block Diagram
      2. 7.1.2 Signal Description
    2. 7.2 Functional Description
      1. 7.2.1 I2C Bus Functional Overview
        1. 7.2.1.1 START and STOP Conditions
        2. 7.2.1.2 Data Format With 7-Bit Address
        3. 7.2.1.3 Data Validity
        4. 7.2.1.4 Acknowledge
        5. 7.2.1.5 Repeated Start
        6. 7.2.1.6 Clock Low Time-out (CLTO)
        7. 7.2.1.7 Dual Address
        8. 7.2.1.8 Arbitration
      2. 7.2.2 Supported Speed Modes
        1. 7.2.2.1 Standard and Fast Modes
      3. 7.2.3 Interrupts
      4. 7.2.4 Loopback Operation
      5. 7.2.5 FIFO and µDMA Operation
        1. 7.2.5.1 Master Module Burst Mode
          1. 7.2.5.1.1 Master Module µDMA Functionality
          2. 7.2.5.1.2 Slave Module
      6. 7.2.6 Command Sequence Flow Charts
        1. 7.2.6.1 I2C Master Command Sequences
        2. 7.2.6.2 I2C Slave Command Sequences
      7. 7.2.7 Initialization and Configuration
    3. 7.3 I2C Registers
  10. 8 SPI (Serial Peripheral Interface)
    1. 8.1 Overview
      1. 8.1.1 Features
    2. 8.2 Functional Description
      1. 8.2.1 SPI
      2. 8.2.2 SPI Transmission
        1. 8.2.2.1 Two Data Pins Interface Mode
        2. 8.2.2.2 Transfer Formats
          1. 8.2.2.2.1 Programmable Word Length
          2. 8.2.2.2.2 Programmable SPI Enable (SPIEN)
          3. 8.2.2.2.3 Programmable SPI Clock (SPICLK)
          4. 8.2.2.2.4 Bit Rate
          5. 8.2.2.2.5 Polarity and Phase
            1. 8.2.2.2.5.1 Transfer Format With PHA = 0
            2. 8.2.2.2.5.2 Transfer Format With PHA = 1
      3. 8.2.3 Master Mode
        1. 8.2.3.1 Interrupt Events in Master Mode
          1. 8.2.3.1.1 TX_empty
          2. 8.2.3.1.2 TX_underflow
          3. 8.2.3.1.3 RX_ full
          4. 8.2.3.1.4 End-of-Word Count
        2. 8.2.3.2 Master Transmit and Receive Mode
        3. 8.2.3.3 SPI Enable Control in Master Mode
          1. 8.2.3.3.1 Keep SPIEN Active Mode (Force SPIEN)
        4. 8.2.3.4 Clock Ratio Granularity
          1. 8.2.3.4.1 FIFO Buffer Management
            1. 8.2.3.4.1.1 Split FIFO
            2. 8.2.3.4.1.2 Buffer Almost Full
            3. 8.2.3.4.1.3 Buffer Almost Empty
            4. 8.2.3.4.1.4 End of Transfer Management
            5. 8.2.3.4.1.5 3- or 4-Pin Mode
      4. 8.2.4 Slave Mode
        1. 8.2.4.1 Interrupts Events in Slave Mode
          1. 8.2.4.1.1 TX_empty
          2. 8.2.4.1.2 TX_underflow
          3. 8.2.4.1.3 RX_ full
          4. 8.2.4.1.4 RX_overflow
          5. 8.2.4.1.5 End-of-Word Count
        2. 8.2.4.2 Slave Transmit and Receive Mode
      5. 8.2.5 Interrupts
        1. 8.2.5.1 Interrupt-Driven Operation
        2. 8.2.5.2 Polling
      6. 8.2.6 DMA Requests
        1. 8.2.6.1 FIFO Buffer Enabled
      7. 8.2.7 Reset
    3. 8.3 Initialization and Configuration
      1. 8.3.1 Basic Initialization
      2. 8.3.2 Master Mode Operation Without Interrupt (Polling)
      3. 8.3.3 Slave Mode Operation With Interrupt
      4. 8.3.4 Generic Interrupt Handler Implementation
    4. 8.4 Access to Data Registers
    5. 8.5 Module Initialization
      1. 8.5.1 Common Transfer Sequence
      2. 8.5.2 End-of-Transfer Sequences
      3. 8.5.3 FIFO Mode
        1. 8.5.3.1 Common Transfer Sequence
        2. 8.5.3.2 Transmit Receive With Word Count
        3. 8.5.3.3 Transmit Receive Without Word Count
    6. 8.6 SPI Registers
  11. 9 General-Purpose Timers
    1. 9.1 Overview
    2. 9.2 Block Diagram
    3. 9.3 Functional Description
      1. 9.3.1 GPTM Reset Conditions
      2. 9.3.2 Timer Modes
        1. 9.3.2.1 One-Shot or Periodic Timer Mode
        2. 9.3.2.2 Input Edge-Count Mode
        3. 9.3.2.3 Input Edge-Time Mode
        4. 9.3.2.4 PWM Mode
      3. 9.3.3 DMA Operation
      4. 9.3.4 Accessing Concatenated 16/32-Bit GPTM Register Values
    4. 9.4 Initialization and Configuration
      1. 9.4.1 One-Shot and Periodic Timer Mode
      2. 9.4.2 Input Edge-Count Mode
      3. 9.4.3 Input Edge-Time Mode
      4. 9.4.4 PWM Mode
    5. 9.5 Timer Registers
  12. 10Watchdog Timer
    1. 10.1 Overview
      1. 10.1.1 Block Diagram
    2. 10.2 Functional Description
      1. 10.2.1 Initialization and Configuration
    3. 10.3 WATCHDOG Registers
    4. 10.4 MCU Watchdog Controller Usage Caveats
      1. 10.4.1 System Watchdog
      2. 10.4.2 System Watchdog Recovery Sequence
  13. 11SD Host Controller Interface
    1. 11.1 Overview
    2. 11.2 SD Host Features
    3. 11.3 1-Bit SD Interface
      1. 11.3.1 Clock and Reset Management
    4. 11.4 Initialization and Configuration Using Peripheral APIs
      1. 11.4.1 Basic Initialization and Configuration
      2. 11.4.2 Sending Command
      3. 11.4.3 Card Detection and Initialization
      4. 11.4.4 Block Read
      5. 11.4.5 Block Write
    5. 11.5 Performance and Testing
    6. 11.6 Peripheral Library APIs
    7. 11.7 SD-HOST Registers
  14. 12Inter-Integrated Sound (I2S) Multichannel Audio Serial Port
    1. 12.1 Overview
      1. 12.1.1 I2S Format
    2. 12.2 Functional Description
    3. 12.3 Programming Model
      1. 12.3.1 Clock and Reset Management
      2. 12.3.2 I2S Data Port Interface
      3. 12.3.3 Initialization and Configuration
    4. 12.4 Peripheral Library APIs for I2S Configuration
      1. 12.4.1 Basic APIs for Enabling and Configuring the Interface
        1. 12.4.1.1 void I2SDisable (unsigned long ulBase)
        2. 12.4.1.2 void I2SEnable (unsigned long ulBase, unsigned long ulMode)
        3. 12.4.1.3 void I2SSerializerConfig (unsigned long ulBase, unsigned long ulDataLine, unsigned long ulSerMode, unsigned long ulInActState)
        4. 12.4.1.4 void I2SConfigSetExpClk (unsigned long ulBase, unsigned long ulI2SClk, unsigned long ulBitClk, unsigned long ulConfig)
      2. 12.4.2 APIs for Data Access if DMA is Not Used
        1. 12.4.2.1 void I2SDataGet (unsigned long ulBase, unsigned long ulDataLine, unsigned long * pulData)
        2. 12.4.2.2 long I2SDataGetNonBlocking (unsigned long ulBase, unsigned long ulDataLine, unsigned long * pulData)
        3. 12.4.2.3 void I2SDataPut (unsigned long ulBase, unsigned long ulDataLine, unsigned long ulData)
        4. 12.4.2.4 void I2SDataPut (unsigned long ulBase, unsigned long ulDataLine, unsigned long ulData)
      3. 12.4.3 APIs for Setting Up, Handling Interrupts, or Getting Status from I2S Peripheral
        1. 12.4.3.1 void I2SIntRegister (unsigned long ulBase, void(*)(void) pfnHandler)
        2. 12.4.3.2 void I2SIntEnable (unsigned long ulBase, unsigned long ulIntFlags)
        3. 12.4.3.3 void I2SIntDisable (unsigned long ulBase, unsigned long ulIntFlags)
        4. 12.4.3.4 unsigned long I2SIntStatus (unsigned long ulBase)
        5. 12.4.3.5 void I2SIntUnregister (unsigned long ulBase)
        6. 12.4.3.6 void I2SIntClear (unsigned long ulBase, unsigned long ulStatFlags)
        7. 12.4.3.7 Values that can be Passed to I2SIntEnable() and I2SIntDisable() as the ulIntFlags Parameter
        8. 12.4.3.8 Values that can be Passed to I2SIntClear() as the ulStatFlags Parameter and Returned from I2SIntStatus()
      4. 12.4.4 APIs to Control FIFO Structures Associated With I2S Peripheral
        1. 12.4.4.1 void I2SRxFIFODisable (unsigned long ulBase)
        2. 12.4.4.2 void I2SRxFIFOEnable (unsigned long ulBase, unsigned long ulRxLevel, unsigned long ulWordsPerTransfer)
        3. 12.4.4.3 unsigned long I2SRxFIFOStatusGet (unsigned long ulBase)
        4. 12.4.4.4 void I2STxFIFODisable (unsigned long ulBase)
        5. 12.4.4.5 void I2STxFIFOEnable (unsigned long ulBase, unsigned long ulTxLevel, unsigned long ulWordsPerTransfer)
        6. 12.4.4.6 unsigned long I2STxFIFOStatusGet (unsigned long ulBase)
    5. 12.5 I2S Registers
  15. 13Analog-to-Digital Converter (ADC)
    1. 13.1 Overview
    2. 13.2 Key Features
    3. 13.3 ADC Register Mapping
    4. 13.4 ADC_MODULE Registers
    5. 13.5 Initialization and Configuration
    6. 13.6 Peripheral Library APIs for ADC Operation
      1. 13.6.1 Overview
      2. 13.6.2 Configuring the ADC Channels
      3. 13.6.3 Basic APIs for Enabling and Configuring the Interface
        1. 13.6.3.1 void ADCEnable (unsigned long ulBase)
        2. 13.6.3.2 void ADCDisable (unsigned long ulBase)
        3. 13.6.3.3 void ADCChannelEnable (unsigned long ulBase, unsigned long ulChannel)
        4. 13.6.3.4 void ADCChannelDisable (unsigned long ulBase, unsigned long ulChannel)
      4. 13.6.4 APIs for Data Transfer [Direct Access to FIFO and DMA Setup]
        1. 13.6.4.1 unsigned char ADCFIFOLvlGet (unsigned long ulBase, unsigned long ulChannel)
        2. 13.6.4.2 unsigned long ADCFIFORead (unsigned long ulBase, unsigned long ulChannel)
        3. 13.6.4.3 void ADCDMAEnable (unsigned long ulBase, unsigned long ulChannel)
        4. 13.6.4.4 void ADCDMADisable (unsigned long ulBase, unsigned long ulChannel)
      5. 13.6.5 APIs for Interrupt Usage
        1. 13.6.5.1 void ADCIntEnable (unsigned long ulBase, unsigned long ulChannel, unsigned long ulIntFlags)
        2. 13.6.5.2 void ADCIntDisable (unsigned long ulBase, unsigned long ulChannel, unsigned long ulIntFlags)
        3. 13.6.5.3 void ADCIntRegister (unsigned long ulBase, unsigned long ulChannel, void(*)(void) pfnHandler)
        4. 13.6.5.4 void ADCIntUnregister (unsigned long ulBase, unsigned long ulChannel)
        5. 13.6.5.5 unsigned long ADCIntStatus (unsigned long ulBase, unsigned long ulChannel)
        6. 13.6.5.6 void ADCIntClear (unsigned long ulBase, unsigned long ulChannel, unsigned long ulIntFlags)
      6. 13.6.6 APIs for Setting Up ADC Timer for Time-Stamping the Samples
        1. 13.6.6.1 void ADCTimerConfig (unsigned long ulBase, unsigned long ulValue)
        2. 13.6.6.2 void ADCTimerDisable (unsigned long ulBase)
        3. 13.6.6.3 void ADCTimerEnable (unsigned long ulBase)
        4. 13.6.6.4 void ADCTimerReset (unsigned long ulBase)
        5. 13.6.6.5 unsigned long ADCTimerValueGet (unsigned long ulBase)
  16. 14Parallel Camera Interface Module
    1. 14.1 Overview
    2. 14.2 Image Sensor Interface
    3. 14.3 Functional Description
      1. 14.3.1 Modes of Operation
      2. 14.3.2 FIFO Buffer
      3. 14.3.3 Reset
      4. 14.3.4 Clock Generation
      5. 14.3.5 Interrupt Generation
      6. 14.3.6 DMA Interface
    4. 14.4 Programming Model
      1. 14.4.1 Camera Core Reset
      2. 14.4.2 Enable the Picture Acquisition
      3. 14.4.3 Disable the Picture Acquisition
    5. 14.5 Interrupt Handling
      1. 14.5.1 FIFO_OF_IRQ (FIFO Overflow)
      2. 14.5.2 FIFO_UF_IRQ (FIFO Underflow)
    6. 14.6 Camera Registers
    7. 14.7 Peripheral Library APIs
    8. 14.8 Developer’s Guide
      1. 14.8.1 Using Peripheral Driver APIs for Capturing an Image
      2. 14.8.2 Using Peripheral Driver APIs for Communicating With Image Sensors
  17. 15Power, Reset, and Clock Management
    1. 15.1 Overview
      1. 15.1.1 Power Management Unit (PMU)
      2. 15.1.2 VBAT Wide-Voltage Connection
      3. 15.1.3 Supply Brownout and Blackout
      4. 15.1.4 Application Processor Power Modes
    2. 15.2 Power Management Control Architecture
      1. 15.2.1 Global Power-Reset-Clock Manager (GPRCM)
      2. 15.2.2 Application Reset-Clock Manager (ARCM)
    3. 15.3 PRCM APIs
      1. 15.3.1  MCU Initialization
      2. 15.3.2  Reset Control
      3. 15.3.3  Peripheral Reset
      4. 15.3.4  Reset Cause
      5. 15.3.5  Clock Control
      6. 15.3.6  Low-Power Modes
      7. 15.3.7  Sleep (SLEEP)
      8. 15.3.8  Low-Power Deep Sleep (LPDS)
      9. 15.3.9  Hibernate (HIB)
      10. 15.3.10 Slow Clock Counter
    4. 15.4 Peripheral Macros
    5. 15.5 Power Management Framework
    6. 15.6 PRCM Registers
  18. 16I/O Pads and Pin Multiplexing
    1. 16.1 Overview
    2. 16.2 I/O Pad Electrical Specifications
    3. 16.3 Analog and Digital Pin Multiplexing
    4. 16.4 Special Analog/Digital Pins
      1. 16.4.1 Pins 45 and 52
      2. 16.4.2 Pins 29 and 30
      3. 16.4.3 Pins 57, 58, 59, and 60
    5. 16.5 Analog Mux Control Registers
    6. 16.6 Pins Available for Applications
    7. 16.7 Functional Pin Mux Configurations
    8. 16.8 Pin Mapping Recommendations
      1. 16.8.1 Pad Configuration Registers for Application Pins
        1. 16.8.1.1 Pad Mux and Electrical Configuration Register Bit Definitions
      2. 16.8.2 PAD Behavior During Reset and Hibernate
      3. 16.8.3 Control Architecture
      4. 16.8.4 CC32xx Pin-mux Examples
      5. 16.8.5 Wake on Pad
      6. 16.8.6 Sense on Power
  19. 17Advance Encryption Standard Accelerator (AES)
    1. 17.1 AES Overview
    2. 17.2 AES Functional Description
      1. 17.2.1 AES Block Diagram
        1. 17.2.1.1 Interfaces
        2. 17.2.1.2 AES Wide-Bus Engine
      2. 17.2.2 AES Algorithm
      3. 17.2.3 AES Operating Modes
        1. 17.2.3.1 Supported Modes of Operation
        2. 17.2.3.2 Extended and Combined Modes of Operations
      4. 17.2.4 Hardware Requests
    3. 17.3 AES Module Programming Guide
      1. 17.3.1 AES Low-Level Programming Models
        1. 17.3.1.1 Global Initialization
        2. 17.3.1.2 Initialization Subsequence
        3. 17.3.1.3 Operational Modes Configuration
        4. 17.3.1.4 AES Events Servicing
    4. 17.4 AES Registers
  20. 18Data Encryption Standard Accelerator (DES)
    1. 18.1 DES Functional Description
    2. 18.2 DES Block Diagram
      1. 18.2.1 µDMA Control
      2. 18.2.2 Interrupt Control
      3. 18.2.3 Register Interface
      4. 18.2.4 DES Enginer
        1. 18.2.4.1 Mode Control FSM
        2. 18.2.4.2 DES Feedback Mode Block
        3. 18.2.4.3 DES Cipher Core
    3. 18.3 DES-Supported Modes of Operation
      1. 18.3.1 ECB Feedback Mode
        1. 18.3.1.1 CBC Feedback Mode
        2. 18.3.1.2 CFB Feedback Mode
    4. 18.4 DES Module Programming Guide – Low-Level Programming Models
      1. 18.4.1 Surrounding Modules Global Initialization
        1. 18.4.1.1 Main Sequence – DES Global Initialization
        2. 18.4.1.2 Subsequence – Configure the DES Algorithm Type
        3. 18.4.1.3 Subsequence – Configure the 3DES Algorithm Type
      2. 18.4.2 Operational Modes Configuration
        1. 18.4.2.1 Main Sequence – DES Polling Mode
        2. 18.4.2.2 DES Interrupt Mode
        3. 18.4.2.3 DES Interrupt DMA Mode
      3. 18.4.3 DES Events Servicing
        1. 18.4.3.1 Interrupt Servicing
        2. 18.4.3.2 Context Input Event Servicing
    5. 18.5 DES Registers
  21. 19SHA/MD5 Accelerator
    1. 19.1 SHA/MD5 Functional Description
      1. 19.1.1 SHA/MD5 Block Diagram
        1. 19.1.1.1 Configuration Registers
        2. 19.1.1.2 Hash/HMAC Engine
        3. 19.1.1.3 Hash Core Control
        4. 19.1.1.4 Host Interface Bank
      2. 19.1.2 µDMA and Interrupt Requests
      3. 19.1.3 Operation Description
        1. 19.1.3.1 SHA Mode
          1. 19.1.3.1.1 Starting a New Hash
          2. 19.1.3.1.2 Outer Digest Registers
          3. 19.1.3.1.3 Inner Digest Registers
          4. 19.1.3.1.4 Closing a Hash
        2. 19.1.3.2 MD5 Mode
          1. 19.1.3.2.1 Starting a New Hash
          2. 19.1.3.2.2 Closing a Hash
        3. 19.1.3.3 Generating a Software Interrupt
      4. 19.1.4 SHA/MD5 Programming Guide
        1. 19.1.4.1 Global Initialization
          1. 19.1.4.1.1 Surrounding Modules Global Initialization
          2. 19.1.4.1.2 Starting a New HMAC using the SHA-1 Hash Function and HMAC Key Processing
          3. 19.1.4.1.3 Subsequence - Continuing a Prior HMAC Using the SHA-1 Hash Function
          4. 19.1.4.1.4 Subsequence - Hashing a Key Bigger than 512 Bits with the SHA-1 Hash Function
          5. 19.1.4.1.5 Operational Modes Configuration
          6. 19.1.4.1.6 SHA/MD5 Event Servicing
            1. 19.1.4.1.6.1 Interrupt Servicing
    2. 19.2 SHA-MD5 Registers
  22. 20Cyclical Redundancy Check (CRC)
    1. 20.1 Functional Description
      1. 20.1.1 CRC Support
        1. 20.1.1.1 CRC Checksum Engine
        2. 20.1.1.2 Data Size
        3. 20.1.1.3 Endian Configuration
    2. 20.2 Initialization and Configuration
      1. 20.2.1 CRC Initialization and Configuration
        1. 20.2.1.1 Data Endian Convention for the CRC Engine
    3. 20.3 CRC Registers
  23. 21On-Chip Parallel Flash
    1. 21.1  Flash Memory Configuration
    2. 21.2  Interrupts
    3. 21.3  Flash Memory Programming
    4. 21.4  32-Word Flash Memory Write Buffer
    5. 21.5  Flash Registers
    6. 21.6  CC323xSF Boot Flow
    7. 21.7  Flash User Application and Memory Partition
    8. 21.8  Programming, Bootstrapping, and Updating the Flash User Application
    9. 21.9  Image Authentication and Integrity Check
    10. 21.10 Debugging Flash User Application Using JTAG
  24. 22Revision History
  25.   A Software Development Kit Examples
  26.   B CC323x Device Miscellaneous Registers
    1. 24.1 DMA_IMR Register (offset = 8Ch) [reset = FF0Fh]
    2. 24.2 DMA_IMS Register (offset = 90h) [reset = 0h]
    3. 24.3 DMA_IMC Register (offset = 94h) [reset = 0h]
    4. 24.4 DMA_ICR Register (offset = 9Ch) [reset = 0h]
    5. 24.5 DMA_MIS Register (offset = A0h) [reset = 0h]
    6. 24.6 DMA_RIS Register (offset = A4h) [reset = 0h]
    7. 24.7 GPTTRIGSEL Register (offset = B0h) [reset = 0h]
19.1.3.1.1 Starting a New Hash

To start a new hash, follow these steps:

  1. Set the ALGO bit field in the SHAMD5_MODE register to 0x1, 0x2, or 0x3 to select SHA-1, SHA-224, or SHA-256, respectively.
  2. Set the ALGO_CONSTANT bit in the SHAMD5_MODE register to 1 to initialize all SHA Inner/Outer Digest n registers from SHAMD5_ODIGEST_A/SHAMD5_IDIGEST_A to SHAMD5_ODIGEST_H/SHAMD5_IDIGEST_H with their default values specified by the algorithm, and set the SHAMD5_DIGESTCOUNT register to 0.
  3. Set the CLOSE_HASH bit of the SHA Mode (SHAMD5_MODE) register to let the SHA engine do the padding. If the hash is computed in one shot, the length of the message can be any value up to 128MB. To process an intermediate hash digest, the CLOSE_HASH bit is set to 0, in which case the packets hashed must be 64 bytes; the last packet must be hashed with the CLOSE_HASH bit set to 1.
  4. Specify the LENGTH field in the SHA Length (SHAMD5_LENGTH) register of the hash data to process in bytes.

When the configuration is complete, the INPUT_READY status bit equals 1 in the SHA Interrupt Status (SHAMD5_IRQSTATUS) register (regardless of whether or not the M_INPUT_READY bit in the SHAMD5_IRQENABLE register is set). When this bit is set, it indicates the SHA engine can receive the data to process. Data must be written to the 16 × 32-bit SHAMD5_DATA_n_IN registers that provide storage for one 64-byte block of data. Unless the CLOSE_HASH bit is set, all of the SHAMD5_DATA_n_IN input buffers must be filled. Data can be written by single write accesses to the 16 registers from a processor or by a DMA transfer.

For µDMA transfers, the PDMA_EN bit must be set in the SHAMD5_SYSCONFIG register, and the appropriate mask bits must be set in the SHAMD5_DMAIM register before starting the new hash. If the µDMA is used for transfers, the SHAMD5_IRQENABLE register should be clear so all interrupts are generated through the µDMA interrupt registers.

The µDMA must be configured to transfer 16 data words of 32 bits each time it is triggered by a µDMA request from the SHA/MD5 module. The 16 data words written are sent to the 16 SHAMD5_DATA_n_IN registers.

The module detects that a 64-byte block is available, then moves the data to a working register space for processing and asserts the INPUT_READY bit in the SHAMD5_IRQSTATUS register to 1. If the PDMA_EN bit in the SHAMD5_SYSCONFIG register has been set to 1, a new µDMA request triggers a new block transfer; otherwise, the processor polls the INPUT_READY bit and writes the 16 data words of 32 bits when it equals 1.

This operation is repeated until the length of the message to hash is reached. The OUPUT_READY bit in the SHAMD5_IRQSTATUS register then indicates that the hash operation is complete. If the PIT_EN bit in the SHAMD5_SYSCONFIG register is set, an interrupt (active low) is also generated to indicate the hash completion.

The processor can then read the eight digest registers A to H that contain the hash or HMAC result. If the hash is an intermediate result of a larger hash, the digest count register must also be read and saved. See Table 19-3 and Table 19-4.

Note:

The number of digest registers used depends on the algorithm selected for the SHA/MD5 module (MD5, SHA-1, SHA-224, or SHA-256).

Table 19-3 Outer Digest Registers
RegisterAddressMD5 (Read/Write)SHA-1 (Read/Write)SHA-2 (Read/Write)HMAC Key Processing (write)
SHAMD5_ODIGEST_A0x000Outer digest [127:96]Outer digest [159:128]Outer digest [255:224]HMAC Key [31:0]
SHAMD5_ODIGEST_B0x004Outer digest [95:64]Outer digest [127:96]Outer digest [223:192]HMAC key [63:32]
SHAMD5_ODIGEST_C0x008Outer digest [63:32]Outer digest [95:64]Outer digest [191:160]HMAC key [95:64]
SHAMD5_ODIGEST_D0x00COuter digest [31:0]Outer digest [63:32]Outer digest [159:128]HMAC key [127:96]
SHAMD5_ODIGEST_E0x010Outer digest [31:0]Outer digest [127:96]HMAC key [159:128]
SHAMD5_ODIGEST_F0x014Outer digest [95:64]HMAC key [191:160]
SHAMD5_ODIGEST_G0x018Outer digest [63:32]HMAC key [223:192]
SHAMD5_ODIGEST_H0x01COuter digest [31:0]HMAC key [255:224]
Table 19-4 Inner Digest Registers
RegisterAddressMD5 (Read/Write)SHA-1 (Read/Write)SHA-2 (Read/Write)SHA-256 (Read/Write)HMAC Key Processing (write)
SHAMD5_IDIGEST_A0x020Inner digest [127:96]Inner digest [159:128]Inner digest [223:192]Inner digest [255:224]HMAC key [287:256]
SHAMD5_IDIGEST_B0x024Inner digest [95:64]Inner digest [127:96]Inner digest [191:160]Inner digest [223:192]HMAC key [319:288]
SHAMD5_IDIGEST_C0x028Inner digest [63:32]Inner digest [95:64]Inner digest [159:128]Inner digest [191:160]HMAC key [351:320]
SHAMD5_IDIGEST_D0x02CInner digest [31:0]Inner digest [63:32]Inner digest [127:96]Inner digest [159:128]HMAC key [383:352]
SHAMD5_IDIGEST_E0x030Inner digest [31:0]Inner digest [95:64]Inner digest [127:96]HMAC key [415:384]
SHAMD5_IDIGEST_F0x034Inner digest [63:32]Inner digest [95:64]HMAC key [447:416]
SHAMD5_IDIGEST_G0x038Inner digest [31:0]Inner digest [63:32]HMAC key [479:448]
SHAMD5_IDIGEST_H0x03CInner digest [31:0]HMAC key [511:480]
Note:

Inner digests are initial, intermediate, and result digests.