SWRU543B January   2019  – June 2025 CC3230S , CC3230SF , CC3235MODS , CC3235MODSF , CC3235S , CC3235SF

 

  1.   1
  2.   Read This First
    1.     Audience
    2.     About This Manual
    3.     Register Bit Conventions
    4.     Glossary
    5.     Related Documentation
    6.     Community Resources
    7.     Trademarks
  3. 1 Architecture Overview
    1. 1.1 Introduction
    2. 1.2 Architecture Overview
    3. 1.3 Functional Overview
      1. 1.3.1  Processor Core
        1. 1.3.1.1 Arm® Cortex®-M4 Processor Core
        2. 1.3.1.2 System Timer (SysTick)
        3. 1.3.1.3 Nested Vector Interrupt Controller (NVIC)
        4. 1.3.1.4 System Control Block
      2. 1.3.2  Memory
        1. 1.3.2.1 On-Chip SRAM
        2. 1.3.2.2 ROM
        3. 1.3.2.3 Flash Memory
      3. 1.3.3  Micro-Direct Memory Access Controller (µDMA)
      4. 1.3.4  General-Purpose Timer (GPT)
      5. 1.3.5  Watchdog Timer (WDT)
      6. 1.3.6  Multichannel Audio Serial Port (McASP)
      7. 1.3.7  Serial Peripheral Interface (SPI)
      8. 1.3.8  Inter-Integrated Circuit (I2C) Interface
      9. 1.3.9  Universal Asynchronous Receiver/Transmitter (UART)
      10. 1.3.10 General-Purpose Input/Output (GPIO)
      11. 1.3.11 Analog-to-Digital Converter (ADC)
      12. 1.3.12 SD Card Host
      13. 1.3.13 Parallel Camera Interface
      14. 1.3.14 Debug Interface
      15. 1.3.15 Hardware Cryptography Accelerator
      16. 1.3.16 Clock, Reset, and Power Management
      17. 1.3.17 SimpleLink™ Subsystem
      18. 1.3.18 I/O Pads and Pin Multiplexing
  4. 2 Cortex®-M4 Processor
    1. 2.1 Overview
      1. 2.1.1 Block Diagram
      2. 2.1.2 System-Level Interface
      3. 2.1.3 Integrated Configurable Debug
      4. 2.1.4 Trace Port Interface Unit (TPIU)
      5. 2.1.5 Cortex®-M4 System Component Details
    2. 2.2 Functional Description
      1. 2.2.1 Programming Model
        1. 2.2.1.1 Processor Mode and Privilege Levels for Software Execution
        2. 2.2.1.2 Stacks
      2. 2.2.2 Register Description
        1. 2.2.2.1 Register Map
        2. 2.2.2.2 Register Descriptions
          1. 2.2.2.2.1 Stack Pointer (SP)
          2. 2.2.2.2.2 Link Register (LR)
          3. 2.2.2.2.3 Program Counter (PC)
          4. 2.2.2.2.4 Program Status Register (PSR)
          5. 2.2.2.2.5 Priority Mask Register (PRIMASK)
          6. 2.2.2.2.6 Fault Mask Register (FAULTMASK)
          7. 2.2.2.2.7 Base Priority Mask Register (BASEPRI)
          8. 2.2.2.2.8 Control Register (CONTROL)
        3. 2.2.2.3 Exceptions and Interrupts
        4. 2.2.2.4 Data Types
      3. 2.2.3 Memory Model
        1. 2.2.3.1 Bit-Banding
          1. 2.2.3.1.1 Directly Accessing an Alias Region
          2. 2.2.3.1.2 Directly Accessing a Bit-Band Region
        2. 2.2.3.2 Data Storage
        3. 2.2.3.3 Synchronization Primitives
      4. 2.2.4 Exception Model
        1. 2.2.4.1 Exception States
        2. 2.2.4.2 Exception Types
        3. 2.2.4.3 Exception Handlers
        4. 2.2.4.4 Vector Table
        5. 2.2.4.5 Exception Priorities
        6. 2.2.4.6 Interrupt Priority Grouping
        7. 2.2.4.7 Exception Entry and Return
          1. 2.2.4.7.1 Exception Entry
      5. 2.2.5 Fault Handling
        1. 2.2.5.1 Fault Types
        2. 2.2.5.2 Fault Escalation and Hard Faults
        3. 2.2.5.3 Fault Status Registers and Fault Address Registers
        4. 2.2.5.4 Lockup State
      6. 2.2.6 Power Management
      7. 2.2.7 Instruction Set Summary
  5. 3 Cortex®-M4 Peripherals
    1. 3.1 Overview
    2. 3.2 Functional Description
      1. 3.2.1 System Timer (SysTick)
      2. 3.2.2 Nested Vectored Interrupt Controller (NVIC)
        1. 3.2.2.1 Level-Sensitive and Pulse Interrupts
        2. 3.2.2.2 Hardware and Software Control of Interrupts
      3. 3.2.3 System Control Block (SCB)
    3. 3.3 Register Map
      1. 3.3.1 Cortex Registers
  6. 4 Direct Memory Access (DMA)
    1. 4.1 Overview
    2. 4.2 Functional Description
      1. 4.2.1 Channel Assignment
      2. 4.2.2 Priority
      3. 4.2.3 Arbitration Size
      4. 4.2.4 Channel Configuration
      5. 4.2.5 Transfer Mode
        1. 4.2.5.1 Stop Mode
        2. 4.2.5.2 Basic Mode
        3. 4.2.5.3 Auto Mode
        4. 4.2.5.4 Ping-Pong Mode
        5. 4.2.5.5 Memory Scatter-Gather Mode
        6. 4.2.5.6 Peripheral Scatter-Gather Mode
      6. 4.2.6 Transfer Size and Increment
      7. 4.2.7 Peripheral Interface
        1. 4.2.7.1 FIFO Peripherals
        2. 4.2.7.2 Trigger Peripherals
        3. 4.2.7.3 Software Request
      8. 4.2.8 Interrupts and Errors
    3. 4.3 Register Description
      1. 4.3.1 DMA Register Map
      2. 4.3.2 µDMA Channel Control Structure
      3. 4.3.3 DMA Registers
      4. 4.3.4 DMA_(OFFSET_FROM_DMA_BASE_ADDRESS) Registers
  7. 5 General-Purpose Input/Outputs (GPIOs)
    1. 5.1 Overview
    2. 5.2 Functional Description
      1. 5.2.1 Data Control
        1. 5.2.1.1 Data Direction Operation
        2. 5.2.1.2 Data Register Operation
    3. 5.3 Interrupt Control
      1. 5.3.1 µDMA Trigger Source
    4. 5.4 Initialization and Configuration
    5. 5.5 GPIO Registers
  8. 6 Universal Asynchronous Receivers/Transmitters (UARTs)
    1. 6.1 Overview
      1. 6.1.1 Block Diagram
    2. 6.2 Functional Description
      1. 6.2.1 Transmit and Receive Logic
      2. 6.2.2 Baud-Rate Generation
      3. 6.2.3 Data Transmission
        1. 6.2.3.1 Flow Control
          1. 6.2.3.1.1 Hardware Flow Control (RTS/CTS)
          2. 6.2.3.1.2 Software Flow Control (Modem Status Interrupts)
        2. 6.2.3.2 FIFO Operation
        3. 6.2.3.3 Interrupts
        4. 6.2.3.4 LoopbackOperation
        5. 6.2.3.5 DMA Operation
      4. 6.2.4 Initialization and Configuration
    3. 6.3 UART Registers
  9. 7 Inter-Integrated Circuit (I2C) Interface
    1. 7.1 Overview
      1. 7.1.1 Block Diagram
      2. 7.1.2 Signal Description
    2. 7.2 Functional Description
      1. 7.2.1 I2C Bus Functional Overview
        1. 7.2.1.1 START and STOP Conditions
        2. 7.2.1.2 Data Format With 7-Bit Address
        3. 7.2.1.3 Data Validity
        4. 7.2.1.4 Acknowledge
        5. 7.2.1.5 Repeated Start
        6. 7.2.1.6 Clock Low Time-out (CLTO)
        7. 7.2.1.7 Dual Address
        8. 7.2.1.8 Arbitration
      2. 7.2.2 Supported Speed Modes
        1. 7.2.2.1 Standard and Fast Modes
      3. 7.2.3 Interrupts
      4. 7.2.4 Loopback Operation
      5. 7.2.5 FIFO and µDMA Operation
        1. 7.2.5.1 Master Module Burst Mode
          1. 7.2.5.1.1 Master Module µDMA Functionality
          2. 7.2.5.1.2 Slave Module
      6. 7.2.6 Command Sequence Flow Charts
        1. 7.2.6.1 I2C Master Command Sequences
        2. 7.2.6.2 I2C Slave Command Sequences
      7. 7.2.7 Initialization and Configuration
    3. 7.3 I2C Registers
  10. 8 SPI (Serial Peripheral Interface)
    1. 8.1 Overview
      1. 8.1.1 Features
    2. 8.2 Functional Description
      1. 8.2.1 SPI
      2. 8.2.2 SPI Transmission
        1. 8.2.2.1 Two Data Pins Interface Mode
        2. 8.2.2.2 Transfer Formats
          1. 8.2.2.2.1 Programmable Word Length
          2. 8.2.2.2.2 Programmable SPI Enable (SPIEN)
          3. 8.2.2.2.3 Programmable SPI Clock (SPICLK)
          4. 8.2.2.2.4 Bit Rate
          5. 8.2.2.2.5 Polarity and Phase
            1. 8.2.2.2.5.1 Transfer Format With PHA = 0
            2. 8.2.2.2.5.2 Transfer Format With PHA = 1
      3. 8.2.3 Master Mode
        1. 8.2.3.1 Interrupt Events in Master Mode
          1. 8.2.3.1.1 TX_empty
          2. 8.2.3.1.2 TX_underflow
          3. 8.2.3.1.3 RX_ full
          4. 8.2.3.1.4 End-of-Word Count
        2. 8.2.3.2 Master Transmit and Receive Mode
        3. 8.2.3.3 SPI Enable Control in Master Mode
          1. 8.2.3.3.1 Keep SPIEN Active Mode (Force SPIEN)
        4. 8.2.3.4 Clock Ratio Granularity
          1. 8.2.3.4.1 FIFO Buffer Management
            1. 8.2.3.4.1.1 Split FIFO
            2. 8.2.3.4.1.2 Buffer Almost Full
            3. 8.2.3.4.1.3 Buffer Almost Empty
            4. 8.2.3.4.1.4 End of Transfer Management
            5. 8.2.3.4.1.5 3- or 4-Pin Mode
      4. 8.2.4 Slave Mode
        1. 8.2.4.1 Interrupts Events in Slave Mode
          1. 8.2.4.1.1 TX_empty
          2. 8.2.4.1.2 TX_underflow
          3. 8.2.4.1.3 RX_ full
          4. 8.2.4.1.4 RX_overflow
          5. 8.2.4.1.5 End-of-Word Count
        2. 8.2.4.2 Slave Transmit and Receive Mode
      5. 8.2.5 Interrupts
        1. 8.2.5.1 Interrupt-Driven Operation
        2. 8.2.5.2 Polling
      6. 8.2.6 DMA Requests
        1. 8.2.6.1 FIFO Buffer Enabled
      7. 8.2.7 Reset
    3. 8.3 Initialization and Configuration
      1. 8.3.1 Basic Initialization
      2. 8.3.2 Master Mode Operation Without Interrupt (Polling)
      3. 8.3.3 Slave Mode Operation With Interrupt
      4. 8.3.4 Generic Interrupt Handler Implementation
    4. 8.4 Access to Data Registers
    5. 8.5 Module Initialization
      1. 8.5.1 Common Transfer Sequence
      2. 8.5.2 End-of-Transfer Sequences
      3. 8.5.3 FIFO Mode
        1. 8.5.3.1 Common Transfer Sequence
        2. 8.5.3.2 Transmit Receive With Word Count
        3. 8.5.3.3 Transmit Receive Without Word Count
    6. 8.6 SPI Registers
  11. 9 General-Purpose Timers
    1. 9.1 Overview
    2. 9.2 Block Diagram
    3. 9.3 Functional Description
      1. 9.3.1 GPTM Reset Conditions
      2. 9.3.2 Timer Modes
        1. 9.3.2.1 One-Shot or Periodic Timer Mode
        2. 9.3.2.2 Input Edge-Count Mode
        3. 9.3.2.3 Input Edge-Time Mode
        4. 9.3.2.4 PWM Mode
      3. 9.3.3 DMA Operation
      4. 9.3.4 Accessing Concatenated 16/32-Bit GPTM Register Values
    4. 9.4 Initialization and Configuration
      1. 9.4.1 One-Shot and Periodic Timer Mode
      2. 9.4.2 Input Edge-Count Mode
      3. 9.4.3 Input Edge-Time Mode
      4. 9.4.4 PWM Mode
    5. 9.5 Timer Registers
  12. 10Watchdog Timer
    1. 10.1 Overview
      1. 10.1.1 Block Diagram
    2. 10.2 Functional Description
      1. 10.2.1 Initialization and Configuration
    3. 10.3 WATCHDOG Registers
    4. 10.4 MCU Watchdog Controller Usage Caveats
      1. 10.4.1 System Watchdog
      2. 10.4.2 System Watchdog Recovery Sequence
  13. 11SD Host Controller Interface
    1. 11.1 Overview
    2. 11.2 SD Host Features
    3. 11.3 1-Bit SD Interface
      1. 11.3.1 Clock and Reset Management
    4. 11.4 Initialization and Configuration Using Peripheral APIs
      1. 11.4.1 Basic Initialization and Configuration
      2. 11.4.2 Sending Command
      3. 11.4.3 Card Detection and Initialization
      4. 11.4.4 Block Read
      5. 11.4.5 Block Write
    5. 11.5 Performance and Testing
    6. 11.6 Peripheral Library APIs
    7. 11.7 SD-HOST Registers
  14. 12Inter-Integrated Sound (I2S) Multichannel Audio Serial Port
    1. 12.1 Overview
      1. 12.1.1 I2S Format
    2. 12.2 Functional Description
    3. 12.3 Programming Model
      1. 12.3.1 Clock and Reset Management
      2. 12.3.2 I2S Data Port Interface
      3. 12.3.3 Initialization and Configuration
    4. 12.4 Peripheral Library APIs for I2S Configuration
      1. 12.4.1 Basic APIs for Enabling and Configuring the Interface
        1. 12.4.1.1 void I2SDisable (unsigned long ulBase)
        2. 12.4.1.2 void I2SEnable (unsigned long ulBase, unsigned long ulMode)
        3. 12.4.1.3 void I2SSerializerConfig (unsigned long ulBase, unsigned long ulDataLine, unsigned long ulSerMode, unsigned long ulInActState)
        4. 12.4.1.4 void I2SConfigSetExpClk (unsigned long ulBase, unsigned long ulI2SClk, unsigned long ulBitClk, unsigned long ulConfig)
      2. 12.4.2 APIs for Data Access if DMA is Not Used
        1. 12.4.2.1 void I2SDataGet (unsigned long ulBase, unsigned long ulDataLine, unsigned long * pulData)
        2. 12.4.2.2 long I2SDataGetNonBlocking (unsigned long ulBase, unsigned long ulDataLine, unsigned long * pulData)
        3. 12.4.2.3 void I2SDataPut (unsigned long ulBase, unsigned long ulDataLine, unsigned long ulData)
        4. 12.4.2.4 void I2SDataPut (unsigned long ulBase, unsigned long ulDataLine, unsigned long ulData)
      3. 12.4.3 APIs for Setting Up, Handling Interrupts, or Getting Status from I2S Peripheral
        1. 12.4.3.1 void I2SIntRegister (unsigned long ulBase, void(*)(void) pfnHandler)
        2. 12.4.3.2 void I2SIntEnable (unsigned long ulBase, unsigned long ulIntFlags)
        3. 12.4.3.3 void I2SIntDisable (unsigned long ulBase, unsigned long ulIntFlags)
        4. 12.4.3.4 unsigned long I2SIntStatus (unsigned long ulBase)
        5. 12.4.3.5 void I2SIntUnregister (unsigned long ulBase)
        6. 12.4.3.6 void I2SIntClear (unsigned long ulBase, unsigned long ulStatFlags)
        7. 12.4.3.7 Values that can be Passed to I2SIntEnable() and I2SIntDisable() as the ulIntFlags Parameter
        8. 12.4.3.8 Values that can be Passed to I2SIntClear() as the ulStatFlags Parameter and Returned from I2SIntStatus()
      4. 12.4.4 APIs to Control FIFO Structures Associated With I2S Peripheral
        1. 12.4.4.1 void I2SRxFIFODisable (unsigned long ulBase)
        2. 12.4.4.2 void I2SRxFIFOEnable (unsigned long ulBase, unsigned long ulRxLevel, unsigned long ulWordsPerTransfer)
        3. 12.4.4.3 unsigned long I2SRxFIFOStatusGet (unsigned long ulBase)
        4. 12.4.4.4 void I2STxFIFODisable (unsigned long ulBase)
        5. 12.4.4.5 void I2STxFIFOEnable (unsigned long ulBase, unsigned long ulTxLevel, unsigned long ulWordsPerTransfer)
        6. 12.4.4.6 unsigned long I2STxFIFOStatusGet (unsigned long ulBase)
    5. 12.5 I2S Registers
  15. 13Analog-to-Digital Converter (ADC)
    1. 13.1 Overview
    2. 13.2 Key Features
    3. 13.3 ADC Register Mapping
    4. 13.4 ADC_MODULE Registers
    5. 13.5 Initialization and Configuration
    6. 13.6 Peripheral Library APIs for ADC Operation
      1. 13.6.1 Overview
      2. 13.6.2 Configuring the ADC Channels
      3. 13.6.3 Basic APIs for Enabling and Configuring the Interface
        1. 13.6.3.1 void ADCEnable (unsigned long ulBase)
        2. 13.6.3.2 void ADCDisable (unsigned long ulBase)
        3. 13.6.3.3 void ADCChannelEnable (unsigned long ulBase, unsigned long ulChannel)
        4. 13.6.3.4 void ADCChannelDisable (unsigned long ulBase, unsigned long ulChannel)
      4. 13.6.4 APIs for Data Transfer [Direct Access to FIFO and DMA Setup]
        1. 13.6.4.1 unsigned char ADCFIFOLvlGet (unsigned long ulBase, unsigned long ulChannel)
        2. 13.6.4.2 unsigned long ADCFIFORead (unsigned long ulBase, unsigned long ulChannel)
        3. 13.6.4.3 void ADCDMAEnable (unsigned long ulBase, unsigned long ulChannel)
        4. 13.6.4.4 void ADCDMADisable (unsigned long ulBase, unsigned long ulChannel)
      5. 13.6.5 APIs for Interrupt Usage
        1. 13.6.5.1 void ADCIntEnable (unsigned long ulBase, unsigned long ulChannel, unsigned long ulIntFlags)
        2. 13.6.5.2 void ADCIntDisable (unsigned long ulBase, unsigned long ulChannel, unsigned long ulIntFlags)
        3. 13.6.5.3 void ADCIntRegister (unsigned long ulBase, unsigned long ulChannel, void(*)(void) pfnHandler)
        4. 13.6.5.4 void ADCIntUnregister (unsigned long ulBase, unsigned long ulChannel)
        5. 13.6.5.5 unsigned long ADCIntStatus (unsigned long ulBase, unsigned long ulChannel)
        6. 13.6.5.6 void ADCIntClear (unsigned long ulBase, unsigned long ulChannel, unsigned long ulIntFlags)
      6. 13.6.6 APIs for Setting Up ADC Timer for Time-Stamping the Samples
        1. 13.6.6.1 void ADCTimerConfig (unsigned long ulBase, unsigned long ulValue)
        2. 13.6.6.2 void ADCTimerDisable (unsigned long ulBase)
        3. 13.6.6.3 void ADCTimerEnable (unsigned long ulBase)
        4. 13.6.6.4 void ADCTimerReset (unsigned long ulBase)
        5. 13.6.6.5 unsigned long ADCTimerValueGet (unsigned long ulBase)
  16. 14Parallel Camera Interface Module
    1. 14.1 Overview
    2. 14.2 Image Sensor Interface
    3. 14.3 Functional Description
      1. 14.3.1 Modes of Operation
      2. 14.3.2 FIFO Buffer
      3. 14.3.3 Reset
      4. 14.3.4 Clock Generation
      5. 14.3.5 Interrupt Generation
      6. 14.3.6 DMA Interface
    4. 14.4 Programming Model
      1. 14.4.1 Camera Core Reset
      2. 14.4.2 Enable the Picture Acquisition
      3. 14.4.3 Disable the Picture Acquisition
    5. 14.5 Interrupt Handling
      1. 14.5.1 FIFO_OF_IRQ (FIFO Overflow)
      2. 14.5.2 FIFO_UF_IRQ (FIFO Underflow)
    6. 14.6 Camera Registers
    7. 14.7 Peripheral Library APIs
    8. 14.8 Developer’s Guide
      1. 14.8.1 Using Peripheral Driver APIs for Capturing an Image
      2. 14.8.2 Using Peripheral Driver APIs for Communicating With Image Sensors
  17. 15Power, Reset, and Clock Management
    1. 15.1 Overview
      1. 15.1.1 Power Management Unit (PMU)
      2. 15.1.2 VBAT Wide-Voltage Connection
      3. 15.1.3 Supply Brownout and Blackout
      4. 15.1.4 Application Processor Power Modes
    2. 15.2 Power Management Control Architecture
      1. 15.2.1 Global Power-Reset-Clock Manager (GPRCM)
      2. 15.2.2 Application Reset-Clock Manager (ARCM)
    3. 15.3 PRCM APIs
      1. 15.3.1  MCU Initialization
      2. 15.3.2  Reset Control
      3. 15.3.3  Peripheral Reset
      4. 15.3.4  Reset Cause
      5. 15.3.5  Clock Control
      6. 15.3.6  Low-Power Modes
      7. 15.3.7  Sleep (SLEEP)
      8. 15.3.8  Low-Power Deep Sleep (LPDS)
      9. 15.3.9  Hibernate (HIB)
      10. 15.3.10 Slow Clock Counter
    4. 15.4 Peripheral Macros
    5. 15.5 Power Management Framework
    6. 15.6 PRCM Registers
  18. 16I/O Pads and Pin Multiplexing
    1. 16.1 Overview
    2. 16.2 I/O Pad Electrical Specifications
    3. 16.3 Analog and Digital Pin Multiplexing
    4. 16.4 Special Analog/Digital Pins
      1. 16.4.1 Pins 45 and 52
      2. 16.4.2 Pins 29 and 30
      3. 16.4.3 Pins 57, 58, 59, and 60
    5. 16.5 Analog Mux Control Registers
    6. 16.6 Pins Available for Applications
    7. 16.7 Functional Pin Mux Configurations
    8. 16.8 Pin Mapping Recommendations
      1. 16.8.1 Pad Configuration Registers for Application Pins
        1. 16.8.1.1 Pad Mux and Electrical Configuration Register Bit Definitions
      2. 16.8.2 PAD Behavior During Reset and Hibernate
      3. 16.8.3 Control Architecture
      4. 16.8.4 CC32xx Pin-mux Examples
      5. 16.8.5 Wake on Pad
      6. 16.8.6 Sense on Power
  19. 17Advance Encryption Standard Accelerator (AES)
    1. 17.1 AES Overview
    2. 17.2 AES Functional Description
      1. 17.2.1 AES Block Diagram
        1. 17.2.1.1 Interfaces
        2. 17.2.1.2 AES Wide-Bus Engine
      2. 17.2.2 AES Algorithm
      3. 17.2.3 AES Operating Modes
        1. 17.2.3.1 Supported Modes of Operation
        2. 17.2.3.2 Extended and Combined Modes of Operations
      4. 17.2.4 Hardware Requests
    3. 17.3 AES Module Programming Guide
      1. 17.3.1 AES Low-Level Programming Models
        1. 17.3.1.1 Global Initialization
        2. 17.3.1.2 Initialization Subsequence
        3. 17.3.1.3 Operational Modes Configuration
        4. 17.3.1.4 AES Events Servicing
    4. 17.4 AES Registers
  20. 18Data Encryption Standard Accelerator (DES)
    1. 18.1 DES Functional Description
    2. 18.2 DES Block Diagram
      1. 18.2.1 µDMA Control
      2. 18.2.2 Interrupt Control
      3. 18.2.3 Register Interface
      4. 18.2.4 DES Enginer
        1. 18.2.4.1 Mode Control FSM
        2. 18.2.4.2 DES Feedback Mode Block
        3. 18.2.4.3 DES Cipher Core
    3. 18.3 DES-Supported Modes of Operation
      1. 18.3.1 ECB Feedback Mode
        1. 18.3.1.1 CBC Feedback Mode
        2. 18.3.1.2 CFB Feedback Mode
    4. 18.4 DES Module Programming Guide – Low-Level Programming Models
      1. 18.4.1 Surrounding Modules Global Initialization
        1. 18.4.1.1 Main Sequence – DES Global Initialization
        2. 18.4.1.2 Subsequence – Configure the DES Algorithm Type
        3. 18.4.1.3 Subsequence – Configure the 3DES Algorithm Type
      2. 18.4.2 Operational Modes Configuration
        1. 18.4.2.1 Main Sequence – DES Polling Mode
        2. 18.4.2.2 DES Interrupt Mode
        3. 18.4.2.3 DES Interrupt DMA Mode
      3. 18.4.3 DES Events Servicing
        1. 18.4.3.1 Interrupt Servicing
        2. 18.4.3.2 Context Input Event Servicing
    5. 18.5 DES Registers
  21. 19SHA/MD5 Accelerator
    1. 19.1 SHA/MD5 Functional Description
      1. 19.1.1 SHA/MD5 Block Diagram
        1. 19.1.1.1 Configuration Registers
        2. 19.1.1.2 Hash/HMAC Engine
        3. 19.1.1.3 Hash Core Control
        4. 19.1.1.4 Host Interface Bank
      2. 19.1.2 µDMA and Interrupt Requests
      3. 19.1.3 Operation Description
        1. 19.1.3.1 SHA Mode
          1. 19.1.3.1.1 Starting a New Hash
          2. 19.1.3.1.2 Outer Digest Registers
          3. 19.1.3.1.3 Inner Digest Registers
          4. 19.1.3.1.4 Closing a Hash
        2. 19.1.3.2 MD5 Mode
          1. 19.1.3.2.1 Starting a New Hash
          2. 19.1.3.2.2 Closing a Hash
        3. 19.1.3.3 Generating a Software Interrupt
      4. 19.1.4 SHA/MD5 Programming Guide
        1. 19.1.4.1 Global Initialization
          1. 19.1.4.1.1 Surrounding Modules Global Initialization
          2. 19.1.4.1.2 Starting a New HMAC using the SHA-1 Hash Function and HMAC Key Processing
          3. 19.1.4.1.3 Subsequence - Continuing a Prior HMAC Using the SHA-1 Hash Function
          4. 19.1.4.1.4 Subsequence - Hashing a Key Bigger than 512 Bits with the SHA-1 Hash Function
          5. 19.1.4.1.5 Operational Modes Configuration
          6. 19.1.4.1.6 SHA/MD5 Event Servicing
            1. 19.1.4.1.6.1 Interrupt Servicing
    2. 19.2 SHA-MD5 Registers
  22. 20Cyclical Redundancy Check (CRC)
    1. 20.1 Functional Description
      1. 20.1.1 CRC Support
        1. 20.1.1.1 CRC Checksum Engine
        2. 20.1.1.2 Data Size
        3. 20.1.1.3 Endian Configuration
    2. 20.2 Initialization and Configuration
      1. 20.2.1 CRC Initialization and Configuration
        1. 20.2.1.1 Data Endian Convention for the CRC Engine
    3. 20.3 CRC Registers
  23. 21On-Chip Parallel Flash
    1. 21.1  Flash Memory Configuration
    2. 21.2  Interrupts
    3. 21.3  Flash Memory Programming
    4. 21.4  32-Word Flash Memory Write Buffer
    5. 21.5  Flash Registers
    6. 21.6  CC323xSF Boot Flow
    7. 21.7  Flash User Application and Memory Partition
    8. 21.8  Programming, Bootstrapping, and Updating the Flash User Application
    9. 21.9  Image Authentication and Integrity Check
    10. 21.10 Debugging Flash User Application Using JTAG
  24. 22Revision History
  25.   A Software Development Kit Examples
  26.   B CC323x Device Miscellaneous Registers
    1. 24.1 DMA_IMR Register (offset = 8Ch) [reset = FF0Fh]
    2. 24.2 DMA_IMS Register (offset = 90h) [reset = 0h]
    3. 24.3 DMA_IMC Register (offset = 94h) [reset = 0h]
    4. 24.4 DMA_ICR Register (offset = 9Ch) [reset = 0h]
    5. 24.5 DMA_MIS Register (offset = A0h) [reset = 0h]
    6. 24.6 DMA_RIS Register (offset = A4h) [reset = 0h]
    7. 24.7 GPTTRIGSEL Register (offset = B0h) [reset = 0h]

6.3 UART Registers

Table 6-2 lists the memory-mapped registers for the UART. All register offset addresses not listed in Table 6-2 should be considered as reserved locations and the register contents should not be modified.

The offset listed is a hexadecimal increment to the register’s address, relative to that UART’s base address:

  • UART0: 0x4000.C000
  • UART1: 0x4000.D000

The UART module clock must be enabled before the registers can be programmed. There must be a delay of 3 system clocks after the UART module clock is enabled before any UART module registers are accessed.

The UART must be disabled (see the UARTEN bit in the UARTCTL register) before any of the control registers are reprogrammed. When the UART is disabled during a TX or RX operation, the current transaction is completed prior to the UART stopping.

Table 6-2 UART Registers
OffsetAcronymRegister NameSection
0hUARTDRUART DataSection 6.3.1
4hUARTRSR_UARTECRUART Receive Status/Error ClearSection 6.3.2
18hUARTFRUART FlagSection 6.3.3
24hUARTIBRDUART Integer Baud-Rate DivisorSection 6.3.4
28hUARTFBRDUART Fractional Baud-Rate DivisorSection 6.3.5
2ChUARTLCRHUART Line ControlSection 6.3.6
30hUARTCTLUART ControlSection 6.3.7
34hUARTIFLSUART Interrupt FIFO Level SelectSection 6.3.8
38hUARTIMUART Interrupt MaskSection 6.3.9
3ChUARTRISUART Raw Interrupt StatusSection 6.3.10
40hUARTMISUART Masked Interrupt StatusSection 6.3.11
44hUARTICRUART Interrupt ClearSection 6.3.12
48hUARTDMACTLUART DMA ControlSection 6.3.13

6.3.1 UARTDR Register (Offset = 0h) [reset = 0h]

UARTDR is shown in Figure 6-3 and described in Table 6-3.

Return to Summary Table.

This register is the data register (the interface to the FIFOs).

For transmitted data, if the FIFO is enabled, data written to this location is pushed onto the transmit FIFO. If the FIFO is disabled, data is stored in the transmitter holding register (the bottom word of the transmit FIFO). A write to this register initiates a transmission from the UART.

For received data, if the FIFO is enabled, the data byte and the 4-bit status (break, frame, parity, and overrun) is pushed onto the 12-bit wide receive FIFO. If the FIFO is disabled, the data byte and status are stored in the receiving holding register (the bottom word of the receive FIFO). The received data can be retrieved by reading this register.

Figure 6-3 UARTDR Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDOEBEPEFEDATA
R-0hR-0hR-0hR-0hR-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 6-3 UARTDR Register Field Descriptions
BitFieldTypeResetDescription
31-12RESERVEDR0h
11OER0h

UART Overrun Error

0h = No data has been lost due to a FIFO overrun.

1h = New data was received when the FIFO was full, resulting in data loss.

10BER0h

UART Break Error

0h = No break condition has occurred

1h = A break condition has been detected, indicating that the receive data input was held Low for longer than a full-word transmission time (defined as start, data, parity, and stop bits).

In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the received data input goes to a 1 (marking state), and the next valid start bit is received.

9PER0h

UART Parity Error

0h = No parity error has occurred

1h = The parity of the received data character does not match the parity defined by bits 2 and 7 of the UARTLCRH register.

In FIFO mode, this error is associated with the character at the top of the FIFO.

8FER0h

UART Framing Error

0h = No framing error has occurred

1h = The received character does not have a valid stop bit (a valid stop bit is 1).

7-0DATAR/W0h

Data Transmitted or Received

Data that is to be transmitted through the UART is written to this field.

When read, this field contains the data that was received by the UART.

6.3.2 UARTRSR_UARTECR Register (Offset = 4h) [reset = 0h]

UARTRSR_UARTECR is shown in Figure 6-4 and described in Table 6-4.

Return to Summary Table.

The UARTRSR/UARTECR register is the receive status register/error clear register.

In addition to the UARTDR register, receive status can also be read from the UARTRSR register. If the status is read from this register, then the status information corresponds to the entry read from UARTDR prior to reading UARTRSR. The status information for overrun is set immediately when an overrun condition occurs.

The UARTRSR register cannot be written.

A write of any value to the UARTECR register clears the framing, parity, break, and overrun errors. All the bits are cleared on reset.

Figure 6-4 UARTRSR_UARTECR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDOE_OR_DATABE_OR_DATAPE_OR_DATAFE_OR_DATA
R-0hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 6-4 UARTRSR_UARTECR Register Field Descriptions
BitFieldTypeResetDescription
7-4DATAW0h

Error Clear

A write to this register of any data clears the framing, parity, break, and overrun flags.

31-4RESERVEDR0h
3OE_OR_DATAR/W0h

UART Overrun Error (R) or Error Clear (W)

This bit is cleared by a write to UARTECR. The FIFO contents remain valid because no further data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must read the data to empty the FIFO.

0h (R) = No data has been lost due to a FIFO overrun.

1h (R) = New data was received when the FIFO was full, resulting in data loss.

2BE_OR_DATAR/W0h

UART Break Error (R) or Error Clear (W)

This bit is cleared to 0 by a write to UARTECR.

0h (R) = No break condition has occurred

1h (R) = A break condition has been detected, indicating that the receive data input was held Low for longer than a full-word transmission time (defined as start, data, parity, and stop bits).

In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received.

1PE_OR_DATAR/W0h

UART Parity Error (R) or Error Clear (W)

This bit is cleared to 0 by a write to UARTECR.

0h (R) = No parity error has occurred

1h (R) = The parity of the received data character does not match the parity defined by bits 2 and 7 of the UARTLCRH register.

0FE_OR_DATAR/W0h

UART Framing Error (R) or Error Clear (W)

This bit is cleared to 0 by a write to UARTECR.

0h (R) = No framing error has occurred

1h (R) = The received character does not have a valid stop bit (a valid stop bit is 1).

In FIFO mode, this error is associated with the character at the top of the FIFO.

6.3.3 UARTFR Register (Offset = 18h) [reset = 90h]

UARTFR is shown in Figure 6-5 and described in Table 6-5.

Return to Summary Table.

The UARTFR register is the flag register. After reset, the TXFF, RXFF, and BUSY bits are 0, and TXFE and RXFE bits are 1. The RI and CTS bits indicate the modem flow control and status. The modem bits are only implemented on UART1 and are reserved on UART0.

Figure 6-5 UARTFR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVEDRI
R-0hR-0h
76543210
TXFERXFFTXFFEXFEBUSYDCDDSRCTS
R-1hR-0hR-0hR-1hR-0hR-0hR-0hR-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 6-5 UARTFR Register Field Descriptions
BitFieldTypeResetDescription
31-9RESERVEDR0h
8RIR0h

Reserved

7TXFER1h

UART Transmit FIFO Empty

The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. If the FIFO is enabled (FEN is 1), the transmit FIFO is empty.

0h = The transmitter has data to transmit.

1h = If the FIFO is disabled (FEN is 0), the transmit holding register is empty.

6RXFFR0h

UART Receive FIFO Full

The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. If the FIFO is enabled (FEN is 1), the receive FIFO is full.

0h = The receiver can receive data.

1h = If the FIFO is disabled (FEN is 0), the receive holding register is full.

5TXFFR0h

UART Transmit FIFO Full

The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register.

0h = The transmitter is not full.

1h = If the FIFO is disabled (FEN is 0), the transmit holding register is full. If the FIFO is enabled (FEN is 1), the transmit FIFO is full.

4EXFER1h

UART Receive FIFO Empty

The meaning of this bit depends on the state of the FEN bit in the UARTLCRH register. If the FIFO is enabled (FEN is 1), the receive FIFO is empty.

0h = The receiver is not empty.

1h = If the FIFO is disabled (FEN is 0), the receive holding register is empty.

3BUSYR0h

UART Busy

This bit is set when the transmit FIFO becomes non-empty (regardless of whether UART is enabled).

0h = The UART is not busy.

1h = The UART is busy transmitting data. This bit remains set until the complete byte, including all stop bits, has been sent from the shift register.

2DCDR0h

Reserved

1DSRR0h

Reserved

0CTSR0h

Clear To Send

This bit is implemented only on UART1 and is reserved for UART0

0h = The U1CTS signal is not asserted.

1h = The U1CTS signal is asserted.

6.3.4 UARTIBRD Register (Offset = 24h) [reset = 0h]

UARTIBRD is shown in Figure 6-6 and described in Table 6-6.

Return to Summary Table.

The UARTIBRD register is the integer part of the baud-rate divisor value. All the bits are cleared on reset. The minimum possible divide ratio is 1 (when UARTIBRD=0), in which case the UARTFBRD register is ignored. When changing the UARTIBRD register, the new value does not take effect until transmission or reception of the current character is complete. Any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register.

Figure 6-6 UARTIBRD Register
313029282726252423222120191817161514131211109876543210
RESERVEDDIVINT
R-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 6-6 UARTIBRD Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0h
15-0DIVINTR/W0h

Integer Baud-Rate Divisor

6.3.5 UARTFBRD Register (Offset = 28h) [reset = 0h]

UARTFBRD is shown in Figure 6-7 and described in Table 6-7.

Return to Summary Table.

The UARTFBRD register is the fractional part of the baud-rate divisor value. All the bits are cleared on reset. When changing the UARTFBRD register, the new value does not take effect until transmission or reception of the current character is complete. Any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register.

Figure 6-7 UARTFBRD Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDDIVFRAC
R-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 6-7 UARTFBRD Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0h
5-0DIVFRACR/W0h

Fractional Baud-Rate Divisor

6.3.6 UARTLCRH Register (Offset = 2Ch) [reset = 0h]

UARTLCRH is shown in Figure 6-8 and described in Table 6-8.

Return to Summary Table.

The UARTLCRH register is the line control register. Serial parameters such as data length, parity, and stop bit selection are implemented in this register.

When updating the baud-rate divisor (UARTIBRD or UARTIFRD), the UARTLCRH register must also be written. The write strobe for the baud-rate divisor registers is tied to the UARTLCRH register.

Figure 6-8 UARTLCRH Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
SPSWLENFENSTP2EPSPENBRK
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 6-8 UARTLCRH Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR0h
7SPSR/W0h

UART Stick Parity Select

When bits 1, 2, and 7 of UARTLCRH are set, the parity bit is transmitted and checked as a 0. When bits 1 and 7 are set and 2 is cleared, the parity bit is transmitted and checked as a 1. When this bit is cleared, stick parity is disabled.

6-5WLENR/W0h

UART Word Length

The bits indicate the number of data bits transmitted or received in a frame as follows:

0h = 5 bits (default)

1h = 6 bits

2h = 7 bits

3h = 8 bits

4FENR/W0h

UART Enable FIFOs

0h = The FIFOs are disabled (Character mode). The FIFOs become 1-byte-deep holding registers.

1h = The transmit and receive FIFO buffers are enabled (FIFO mode).

3STP2R/W0h

UART Two Stop Bits Select

When in 7816 smartcard mode (the SMART bit is set in the UARTCTL register), the number of stop bits is forced to 2.

0h = One stop bit is transmitted at the end of a frame.

1h = Two stop bits are transmitted at the end of a frame. The receive logic does not check for two stop bits being received.

2EPSR/W0h

UART Even Parity Select

This bit has no effect when parity is disabled by the PEN bit.

0h = Odd parity is performed, which checks for an odd number of 1s.

1h = Even parity generation and checking is performed during transmission and reception, which checks for an even number of 1s in data and parity bits.

1PENR/W0h

UART Parity Enable

0h = Parity is disabled and no parity bit is added to the data frame.

1h = Parity checking and generation is enabled.

0BRKR/W0h

UART Send Break

A low level is continually output on the UnTx signal, after completing transmission of the current character. For the proper execution of the break command, software must set this bit for at least two frames (character periods).

6.3.7 UARTCTL Register (Offset = 30h) [reset = 300h]

UARTCTL is shown in Figure 6-9 and described in Table 6-9.

Return to Summary Table.

The UARTCTL register is the control register. All the bits are cleared on reset except for the Transmit Enable (TXE) and Receive Enable (RXE) bits, which are set.

To enable the UART module, the UARTEN bit must be set. If software requires a configuration change in the module, the UARTEN bit must be cleared before the configuration changes are written. If the UART is disabled during a transmit or receive operation, the current transaction is completed prior to the UART stopping.

Note:

The UARTCTL register should not be changed while the UART is enabled or else the results are unpredictable. The following sequence is recommended for making changes to the UARTCTL register.

  1. Disable the UART.
  2. Wait for the end of transmission or reception of the current character.
  3. Flush the transmit FIFO by clearing bit 4 (FEN) in the line control register (UARTLCRH).
  4. Reprogram the control register.
  5. Enable the UART.

Figure 6-9 UARTCTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
CTSENRTSENRESERVEDRTSDTRRXETXE
R/W-0hR/W-0hR-0hR/W-0hR/W-0hR/W-1hR/W-1h
76543210
LBERESERVEDHSEEOTRESERVEDRESERVEDSIRENUARTEN
R/W-0hR-0hR/W-0hR/W-0hR-0hR-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 6-9 UARTCTL Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0h
15CTSENR/W0h

Enable Clear To Send

0h = CTS hardware flow control is disabled.

1h = CTS hardware flow control is enabled. Data is only transmitted when the U1CTS signal is asserted.

14RTSENR/W0h

Enable Request to Send

0h = RTS hardware flow control is disabled.

1h = RTS hardware flow control is enabled. Data is only requested (by asserting U1RTS) when the receive FIFO has available entries.

13-12RESERVEDR0h
11RTSR/W0h

Request to Send

When RTSEN is clear, the status of this bit is reflected on the U1RTS signal. If RTSEN is set, this bit is ignored on a write and should be ignored on read.

10DTRR/W0h

Reserved

9RXER/W1h

UART Receive Enable

0h = The receive section of the UART is disabled.

1h = The receive section of the UART is enabled. If the UART is disabled in the middle of a receive, it completes the current character before stopping.

Note: To enable reception, the UARTEN bit must also be set.

8TXER/W1h

UART Transmit Enable

If the UART is disabled in the middle of a transmission, it completes the current character before stopping.

0h = The transmit section of the UART is disabled.

1h = The transmit section of the UART is enabled.

Note: To enable transmission, the UARTEN bit must also be set.

7LBER/W0h

UART Loop Back Enable

0h = Normal operation.

1h = The UnTx path is fed through the UnRx path.

6RESERVEDR0h
5HSER/W0h

High-Speed Enable

0h = The UART is clocked using the system clock divided by 16.

1h = The UART is clocked using the system clock divided by 8.

Note: System clock used is also dependent on the baud-rate divisor configuration. The state of this bit has no effect on clock generation in ISO 7816 smart card mode (the SMART bit is set).

4EOTR/W0h

End of Transmission

This bit determines the behavior of the TXRIS bit in the UARTRIS register.

0h = The TXRIS bit is set when the transmit FIFO condition specified in UARTIFLS is met.

1h = The TXRIS bit is set only after all transmitted data, including stop bits, have cleared the serializer.

3RESERVEDR0h
2RESERVEDR0h
1SIRENR/W0h

RESERVED

0UARTENR/W0h

UART Enable

If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping.

0h = The UART is disabled.

1h = The UART is enabled.

6.3.8 UARTIFLS Register (Offset = 34h) [reset = 12h]

UARTIFLS is shown in Figure 6-10 and described in Table 6-10.

Return to Summary Table.

The UARTIFLS register is the interrupt FIFO level select register. You can use this register to define the FIFO level at which the TXRIS and RXRIS bits in the UARTRIS register are triggered.

The interrupts are generated based on a transition through a level rather than being based on the level. That is, the interrupts are generated when the fill level progresses through the trigger level. For example, if the receive trigger level is set to the half-way mark, the interrupt is triggered as the module is receiving the 9th character.

Out of reset, the TXIFLSEL and RXIFLSEL bits are configured so that the FIFOs trigger an interrupt at the half-way mark.

Figure 6-10 UARTIFLS Register
31302928272625242322212019181716
RESERVED
R-0h
1514131211109876543210
RESERVEDRXIFLSELTXIFSEL
R-0hR/W-2hR/W-2h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 6-10 UARTIFLS Register Field Descriptions
BitFieldTypeResetDescription
31-6RESERVEDR0h
5-3RXIFLSELR/W2h

UART Receive Interrupt FIFO Level Select

The trigger points for the receive interrupt are as follows:

0h = Reserved

1h = RX FIFO full

2h = RX FIFO full (default)

3h = RX FIFO full

4h = RX FIFO full

2-0TXIFSELR/W2h

UART Transmit Interrupt FIFO Level Select

The trigger points for the transmit interrupt are as follows:

0h = Reserved

1h = TX FIFO empty

2h = TX FIFO empty (default)

3h = TX FIFO empty

4h = TX FIFO empty

Note: If the EOT bit in UARTCTL is set, the transmit interrupt is generated once the FIFO is completely empty and all data including stop bits have left the transmit serializer. In this case, the setting of TXIFLSEL is ignored.

6.3.9 UARTIM Register (Offset = 38h) [reset = 0h]

UARTIM is shown in Figure 6-11 and described in Table 6-11.

Return to Summary Table.

The UARTIM register is the interrupt mask set/clear register.

On a read, this register gives the current value of the mask on the relevant interrupt. Setting a bit allows the corresponding raw interrupt signal to be routed to the interrupt controller. Clearing a bit prevents the raw interrupt signal from being sent to the interrupt controller.

Figure 6-11 UARTIM Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDDMATXIMDMARXIM
R-0hR/W-0hR/W-0h
15141312111098
RESERVED9BITIMRESERVEDOEIMBEIMPEIM
R-0hR/W-0hR-0hR/W-0hR/W-0hR/W-0h
76543210
FEIMRTIMTXIMRXIMDSRIMDCDIMCTSIMRIIM
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 6-11 UARTIM Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0h
17DMATXIMR/W0h

Transmit DMA Interrupt Mask

0h = The DMATXRIS interrupt is suppressed and not sent to the interrupt controller.

1h = An interrupt is sent to the interrupt controller when the DMATXRIS bit in the UARTRIS register is set.

16DMARXIMR/W0h

Receive DMA Interrupt Mask

0h = The DMARXRIS interrupt is suppressed and not sent to the interrupt controller.

1h = An interrupt is sent to the interrupt controller when the DMARXRIS bit in the UARTRIS register is set.

15-13RESERVEDR0h
129BITIMR/W0h

Reserved

11RESERVEDR0h
10OEIMR/W0h

UART Overrun Error Interrupt Mask

0h = The OERIS interrupt is suppressed and not sent to the interrupt controller.

1h = An interrupt is sent to the interrupt controller when the OERIS bit in the UARTRIS register is set.

9BEIMR/W0h

UART Break Error Interrupt Mask

0h = The BERIS interrupt is suppressed and not sent to the interrupt controller.

1h = An interrupt is sent to the interrupt controller when the BERIS bit in the UARTRIS register is set.

8PEIMR/W0h

UART Parity Error Interrupt Mask

0h = The PERIS interrupt is suppressed and not sent to the interrupt controller.

1h = An interrupt is sent to the interrupt controller when the PERIS bit in the UARTRIS register is set.

7FEIMR/W0h

UART Framing Error Interrupt Mask

0h = The FERIS interrupt is suppressed and not sent to the interrupt controller.

1h = An interrupt is sent to the interrupt controller when the FERIS bit in the UARTRIS register is set.

6RTIMR/W0h

UART Receive Time-Out Interrupt Mask

0h = The RTRIS interrupt is suppressed and not sent to the interrupt controller.

1h = An interrupt is sent to the interrupt controller when the RTRIS bit in the UARTRIS register is set.

5TXIMR/W0h

UART Transmit Interrupt Mask

0h = The TXRIS interrupt is suppressed and not sent to the interrupt controller.

1h = An interrupt is sent to the interrupt controller when the TXRIS bit in the UARTRIS register is set.

4RXIMR/W0h

UART Receive Interrupt Mask

0h = The RXRIS interrupt is suppressed and not sent to the interrupt controller.

1h = An interrupt is sent to the interrupt controller when the RXRIS bit in the UARTRIS register is set.

3DSRIMR/W0h

Reserved

2DCDIMR/W0h

Reserved

1CTSIMR/W0h

UART Clear to Send Modem Interrupt Mask

0h = The CTSRIS interrupt is suppressed and not sent to the interrupt controller.

1h = An interrupt is sent to the interrupt controller when the CTSRIS bit in the UARTRIS register is set.

0RIIMR/W0h

Reserved

6.3.10 UARTRIS Register (Offset = 3Ch) [reset = 0h]

UARTRIS is shown in Figure 6-12 and described in Table 6-12.

Return to Summary Table.

The UARTRIS register is the raw interrupt status register. On a read, this register gives the current raw status value of the corresponding interrupt. A write has no effect.

Figure 6-12 UARTRIS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDDMATXRISDMARXRIS
R-0hR-0hR-0h
15141312111098
RESERVEDRESERVEDOERISBERISPERIS
R-0hR-0hR-0hR-0hR-0h
76543210
FERISRTRISTXRISRXRISDSRRISDCDRISCTSRISRIRIS
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 6-12 UARTRIS Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0h
17DMATXRISR0h

Transmit DMA Raw Interrupt Status

This bit is cleared by writing a 1 to the DMATXIC bit in the UARTICR register.

0h = No interrupt

1h = The transmit DMA has completed.

16DMARXRISR0h

Receive DMA Raw Interrupt Status

This bit is cleared by writing a 1 to the DMARXIC bit in the UARTICR register.

0h = No interrupt

1h = The receive DMA has completed.

15-11RESERVEDR0h
10OERISR0h

UART Overrun Error Raw Interrupt Status

This bit is cleared by writing a 1 to the OEIC bit in the UARTICR register.

0h = No interrupt

1h = An overrun error has occurred.

9BERISR0h

UART Break Error Raw Interrupt Status

This bit is cleared by writing a 1 to the BEIC bit in the UARTICR register.

0h = No interrupt

1h = A break error has occurred.

8PERISR0h

UART Parity Error Raw Interrupt Status

This bit is cleared by writing a 1 to the PEIC bit in the UARTICR register.

0h = No interrupt

1h = A parity error has occurred.

7FERISR0h

UART Framing Error Raw Interrupt Status

This bit is cleared by writing a 1 to the FEIC bit in the UARTICR register.

0h = No interrupt

1h = A framing error has occurred.

6RTRISR0h

UART Receive Time-Out Raw Interrupt Status

This bit is cleared by writing a 1 to the RTIC bit in the UARTICR register.

0h = No interrupt

1h = A receive time out has occurred.

5TXRISR0h

UART Transmit Raw Interrupt Status

If the EOT bit is set, the last bit of all transmitted data and flags has left the serializer. This bit is cleared by writing a 1 to the TXIC bit in the UARTICR register or by writing data to the transmit FIFO until it becomes greater than the trigger level, if the FIFO is enabled, or by writing a single byte if the FIFO is disabled.

0h = No interrupt

1h = If the EOT bit in the UARTCTL register is clear, the transmit FIFO level has passed through the condition defined in the UARTIFLS register.

4RXRISR0h

UART Receive Raw Interrupt Status

This bit is cleared by writing a 1 to the RXIC bit in the UARTICR register or by reading data from the receive FIFO until it becomes less than the trigger level, if the FIFO is enabled, or by reading a single byte if the FIFO is disabled.

0h = No interrupt

1h = The receive FIFO level has passed through the condition defined in the UARTIFLS register.

3DSRRISR0h

Reserved

2DCDRISR0h

Reserved

1CTSRISR0h

UART Clear to Send Modem Raw Interrupt Status

This bit is cleared by writing a 1 to the CTSIC bit in the UARTICR register.

0h = No interrupt

1h = Clear to Send used for software flow control.

0RIRISR0h

Reserved

6.3.11 UARTMIS Register (Offset = 40h) [reset = 0h]

UARTMIS is shown in Figure 6-13 and described in Table 6-13.

Return to Summary Table.

The UARTMIS register is the masked interrupt status register. On a read, this register gives the current masked status value of the corresponding interrupt. A write has no effect.

Figure 6-13 UARTMIS Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDDMATXMISDMARXMIS
R-0hR-0hR-0h
15141312111098
RESERVEDRESERVEDOEMISBEMISPEMIS
R-0hR-0hR-0hR-0hR-0h
76543210
FEMISRTMISTXMISRXMISDSRMISDCDMISCTSMISRIMIS
R-0hR-0hR-0hR-0hR-0hR-0hR-0hR-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 6-13 UARTMIS Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0h
17DMATXMISR0h

Transmit DMA Masked Interrupt Status

This bit is cleared by writing a 1 to the DMATXIC bit in the UARTICR register.

0h = An interrupt has not occurred or is masked.

1h = An unmasked interrupt was signaled due to the completion of the transmit DMA.

16DMARXMISR0h

Receive DMA Masked Interrupt Status

This bit is cleared by writing a 1 to the DMARXIC bit in the UARTICR register.

0h = An interrupt has not occurred or is masked.

1h = An unmasked interrupt was signaled due to the completion of the receive DMA.

15-11RESERVEDR0h
10OEMISR0h

UART Overrun Error Masked Interrupt Status

This bit is cleared by writing a 1 to the OEIC bit in the UARTICR register.

0h = An interrupt has not occurred or is masked.

1h = An unmasked interrupt was signaled due to an overrun error.

9BEMISR0h

UART Break Error Masked Interrupt Status

This bit is cleared by writing a 1 to the BEIC bit in the UARTICR register.

0h = An interrupt has not occurred or is masked.

1h = An unmasked interrupt was signaled due to a break error.

8PEMISR0h

UART Parity Error Masked Interrupt Status

This bit is cleared by writing a 1 to the PEIC bit in the UARTICR register.

0h = An interrupt has not occurred or is masked.

1h = An unmasked interrupt was signaled due to a parity error.

7FEMISR0h

UART Framing Error Masked Interrupt Status

This bit is cleared by writing a 1 to the FEIC bit in the UARTICR register.

0h = An interrupt has not occurred or is masked.

1h = An unmasked interrupt was signaled due to a framing error.

6RTMISR0h

UART Receive Time-Out Masked Interrupt Status

This bit is cleared by writing a 1 to the RTIC bit in the UARTICR register.

0h = An interrupt has not occurred or is masked.

1h = An unmasked interrupt was signaled due to a receive time out.

5TXMISR0h

UART Transmit Masked Interrupt Status

This bit is cleared by writing a 1 to the TXIC bit in the UARTICR register or by writing data to the transmit FIFO until it becomes greater than the trigger level, if the FIFO is enabled, or by writing a single byte if the FIFO is disabled.

0h = An interrupt has not occurred or is masked.

1h = An unmasked interrupt was signaled due to passing through the specified transmit FIFO level (if the EOT bit is clear) or due to the transmission of the last data bit (if the EOT bit is set).

4RXMISR0h

UART Receive Masked Interrupt Status

This bit is cleared by writing a 1 to the RXIC bit in the UARTICR register or by reading data from the receive FIFO until it becomes less than the trigger level, if the FIFO is enabled, or by reading a single byte if the FIFO is disabled.

0h = An interrupt has not occurred or is masked.

1h = An unmasked interrupt was signaled due to passing through the specified receive FIFO level.

3DSRMISR0h

Reserved

2DCDMISR0h

Reserved

1CTSMISR0h

UART Clear to Send Modem Masked Interrupt Status

This bit is cleared by writing a 1 to the CTSIC bit in the UARTICR register.

0h = An interrupt has not occurred or is masked.

1h = An unmasked interrupt was signaled due to Clear to Send.

0RIMISR0h

Reserved

6.3.12 UARTICR Register (Offset = 44h) [reset = 0h]

UARTICR is shown in Figure 6-14 and described in Table 6-14.

Return to Summary Table.

The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt (both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect.

Figure 6-14 UARTICR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDDMATXICDMARXIC
R-0hW1C-0hW1C-0h
15141312111098
RESERVEDRESERVEDOEICBEICPEIC
R-0hW1C-0hW1C-0hW1C-0hW1C-0h
76543210
FEICRTICTXICRXICDSRMICDCDMICCTSMICRIMIC
W1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0hW1C-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 6-14 UARTICR Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR0h
17DMATXICW1C0h

Transmit DMA Interrupt Clear

Writing a 1 to this bit clears the DMATXRIS bit in the UARTRIS register and the DMATXMIS bit in the UARTMIS register.

16DMARXICW1C0h

Receive DMA Interrupt Clear

Writing a 1 to this bit clears the DMARXRIS bit in the UARTRIS register and the DMARXMIS bit in the UARTMIS register.

15-11RESERVEDR0h
10OEICW1C0h

Overrun Error Interrupt Clear

Writing a 1 to this bit clears the OERIS bit in the UARTRIS register and the OEMIS bit in the UARTMIS register.

9BEICW1C0h

Break Error Interrupt Clear

Writing a 1 to this bit clears the BERIS bit in the UARTRIS register and the BEMIS bit in the UARTMIS register.

8PEICW1C0h

Parity Error Interrupt Clear

Writing a 1 to this bit clears the PERIS bit in the UARTRIS register and the PEMIS bit in the UARTMIS register.

7FEICW1C0h

Framing Error Interrupt Clear

Writing a 1 to this bit clears the FERIS bit in the UARTRIS register and the FEMIS bit in the UARTMIS register.

6RTICW1C0h

Receive Time-Out Interrupt Clear

Writing a 1 to this bit clears the RTRIS bit in the UARTRIS register and the RTMIS bit in the UARTMIS register.

5TXICW1C0h

Receive Time-Out Interrupt Clear

Writing a 1 to this bit clears the RTRIS bit in the UARTRIS register and the RTMIS bit in the UARTMIS register.

4RXICW1C0h

Receive Interrupt Clear

Writing a 1 to this bit clears the RXRIS bit in the UARTRIS register and the RXMIS bit in the UARTMIS register.

3DSRMICW1C0h

Reserved

2DCDMICW1C0h

Reserved

1CTSMICW1C0h

UART Clear to Send Modem Interrupt Clear

Writing a 1 to this bit clears the CTSRIS bit in the UARTRIS register and the CTSMIS bit in the UARTMIS register.

0RIMICW1C0h

Reserved

6.3.13 UARTDMACTL Register (Offset = 48h) [reset = 0h]

UARTDMACTL is shown in Figure 6-15 and described in Table 6-15.

Return to Summary Table.

The UARTDMACTL register is the DMA control register.

Figure 6-15 UARTDMACTL Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDDMAERRTXDMAERXDMAE
R-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 6-15 UARTDMACTL Register Field Descriptions
BitFieldTypeResetDescription
31-3RESERVEDR0h
2DMAERRR/W0h

DMA on Error

0h = DMA receive requests are unaffected when a receive error occurs.

1h = DMA receive requests are automatically disabled when a receive error occurs.

1TXDMAER/W0h

Transmit DMA Enable

0h = DMA for the receive FIFO is disabled.

1h = DMA for the receive FIFO is enabled.

0RXDMAER/W0h

Receive DMA Enable

0h = DMA for the receive FIFO is disabled.

1h = DMA for the receive FIFO is enabled.