SWRU543B January   2019  – June 2025 CC3230S , CC3230SF , CC3235MODS , CC3235MODSF , CC3235S , CC3235SF

 

  1.   1
  2.   Read This First
    1.     Audience
    2.     About This Manual
    3.     Register Bit Conventions
    4.     Glossary
    5.     Related Documentation
    6.     Community Resources
    7.     Trademarks
  3. 1 Architecture Overview
    1. 1.1 Introduction
    2. 1.2 Architecture Overview
    3. 1.3 Functional Overview
      1. 1.3.1  Processor Core
        1. 1.3.1.1 Arm® Cortex®-M4 Processor Core
        2. 1.3.1.2 System Timer (SysTick)
        3. 1.3.1.3 Nested Vector Interrupt Controller (NVIC)
        4. 1.3.1.4 System Control Block
      2. 1.3.2  Memory
        1. 1.3.2.1 On-Chip SRAM
        2. 1.3.2.2 ROM
        3. 1.3.2.3 Flash Memory
      3. 1.3.3  Micro-Direct Memory Access Controller (µDMA)
      4. 1.3.4  General-Purpose Timer (GPT)
      5. 1.3.5  Watchdog Timer (WDT)
      6. 1.3.6  Multichannel Audio Serial Port (McASP)
      7. 1.3.7  Serial Peripheral Interface (SPI)
      8. 1.3.8  Inter-Integrated Circuit (I2C) Interface
      9. 1.3.9  Universal Asynchronous Receiver/Transmitter (UART)
      10. 1.3.10 General-Purpose Input/Output (GPIO)
      11. 1.3.11 Analog-to-Digital Converter (ADC)
      12. 1.3.12 SD Card Host
      13. 1.3.13 Parallel Camera Interface
      14. 1.3.14 Debug Interface
      15. 1.3.15 Hardware Cryptography Accelerator
      16. 1.3.16 Clock, Reset, and Power Management
      17. 1.3.17 SimpleLink™ Subsystem
      18. 1.3.18 I/O Pads and Pin Multiplexing
  4. 2 Cortex®-M4 Processor
    1. 2.1 Overview
      1. 2.1.1 Block Diagram
      2. 2.1.2 System-Level Interface
      3. 2.1.3 Integrated Configurable Debug
      4. 2.1.4 Trace Port Interface Unit (TPIU)
      5. 2.1.5 Cortex®-M4 System Component Details
    2. 2.2 Functional Description
      1. 2.2.1 Programming Model
        1. 2.2.1.1 Processor Mode and Privilege Levels for Software Execution
        2. 2.2.1.2 Stacks
      2. 2.2.2 Register Description
        1. 2.2.2.1 Register Map
        2. 2.2.2.2 Register Descriptions
          1. 2.2.2.2.1 Stack Pointer (SP)
          2. 2.2.2.2.2 Link Register (LR)
          3. 2.2.2.2.3 Program Counter (PC)
          4. 2.2.2.2.4 Program Status Register (PSR)
          5. 2.2.2.2.5 Priority Mask Register (PRIMASK)
          6. 2.2.2.2.6 Fault Mask Register (FAULTMASK)
          7. 2.2.2.2.7 Base Priority Mask Register (BASEPRI)
          8. 2.2.2.2.8 Control Register (CONTROL)
        3. 2.2.2.3 Exceptions and Interrupts
        4. 2.2.2.4 Data Types
      3. 2.2.3 Memory Model
        1. 2.2.3.1 Bit-Banding
          1. 2.2.3.1.1 Directly Accessing an Alias Region
          2. 2.2.3.1.2 Directly Accessing a Bit-Band Region
        2. 2.2.3.2 Data Storage
        3. 2.2.3.3 Synchronization Primitives
      4. 2.2.4 Exception Model
        1. 2.2.4.1 Exception States
        2. 2.2.4.2 Exception Types
        3. 2.2.4.3 Exception Handlers
        4. 2.2.4.4 Vector Table
        5. 2.2.4.5 Exception Priorities
        6. 2.2.4.6 Interrupt Priority Grouping
        7. 2.2.4.7 Exception Entry and Return
          1. 2.2.4.7.1 Exception Entry
      5. 2.2.5 Fault Handling
        1. 2.2.5.1 Fault Types
        2. 2.2.5.2 Fault Escalation and Hard Faults
        3. 2.2.5.3 Fault Status Registers and Fault Address Registers
        4. 2.2.5.4 Lockup State
      6. 2.2.6 Power Management
      7. 2.2.7 Instruction Set Summary
  5. 3 Cortex®-M4 Peripherals
    1. 3.1 Overview
    2. 3.2 Functional Description
      1. 3.2.1 System Timer (SysTick)
      2. 3.2.2 Nested Vectored Interrupt Controller (NVIC)
        1. 3.2.2.1 Level-Sensitive and Pulse Interrupts
        2. 3.2.2.2 Hardware and Software Control of Interrupts
      3. 3.2.3 System Control Block (SCB)
    3. 3.3 Register Map
      1. 3.3.1 Cortex Registers
  6. 4 Direct Memory Access (DMA)
    1. 4.1 Overview
    2. 4.2 Functional Description
      1. 4.2.1 Channel Assignment
      2. 4.2.2 Priority
      3. 4.2.3 Arbitration Size
      4. 4.2.4 Channel Configuration
      5. 4.2.5 Transfer Mode
        1. 4.2.5.1 Stop Mode
        2. 4.2.5.2 Basic Mode
        3. 4.2.5.3 Auto Mode
        4. 4.2.5.4 Ping-Pong Mode
        5. 4.2.5.5 Memory Scatter-Gather Mode
        6. 4.2.5.6 Peripheral Scatter-Gather Mode
      6. 4.2.6 Transfer Size and Increment
      7. 4.2.7 Peripheral Interface
        1. 4.2.7.1 FIFO Peripherals
        2. 4.2.7.2 Trigger Peripherals
        3. 4.2.7.3 Software Request
      8. 4.2.8 Interrupts and Errors
    3. 4.3 Register Description
      1. 4.3.1 DMA Register Map
      2. 4.3.2 µDMA Channel Control Structure
      3. 4.3.3 DMA Registers
      4. 4.3.4 DMA_(OFFSET_FROM_DMA_BASE_ADDRESS) Registers
  7. 5 General-Purpose Input/Outputs (GPIOs)
    1. 5.1 Overview
    2. 5.2 Functional Description
      1. 5.2.1 Data Control
        1. 5.2.1.1 Data Direction Operation
        2. 5.2.1.2 Data Register Operation
    3. 5.3 Interrupt Control
      1. 5.3.1 µDMA Trigger Source
    4. 5.4 Initialization and Configuration
    5. 5.5 GPIO Registers
  8. 6 Universal Asynchronous Receivers/Transmitters (UARTs)
    1. 6.1 Overview
      1. 6.1.1 Block Diagram
    2. 6.2 Functional Description
      1. 6.2.1 Transmit and Receive Logic
      2. 6.2.2 Baud-Rate Generation
      3. 6.2.3 Data Transmission
        1. 6.2.3.1 Flow Control
          1. 6.2.3.1.1 Hardware Flow Control (RTS/CTS)
          2. 6.2.3.1.2 Software Flow Control (Modem Status Interrupts)
        2. 6.2.3.2 FIFO Operation
        3. 6.2.3.3 Interrupts
        4. 6.2.3.4 LoopbackOperation
        5. 6.2.3.5 DMA Operation
      4. 6.2.4 Initialization and Configuration
    3. 6.3 UART Registers
  9. 7 Inter-Integrated Circuit (I2C) Interface
    1. 7.1 Overview
      1. 7.1.1 Block Diagram
      2. 7.1.2 Signal Description
    2. 7.2 Functional Description
      1. 7.2.1 I2C Bus Functional Overview
        1. 7.2.1.1 START and STOP Conditions
        2. 7.2.1.2 Data Format With 7-Bit Address
        3. 7.2.1.3 Data Validity
        4. 7.2.1.4 Acknowledge
        5. 7.2.1.5 Repeated Start
        6. 7.2.1.6 Clock Low Time-out (CLTO)
        7. 7.2.1.7 Dual Address
        8. 7.2.1.8 Arbitration
      2. 7.2.2 Supported Speed Modes
        1. 7.2.2.1 Standard and Fast Modes
      3. 7.2.3 Interrupts
      4. 7.2.4 Loopback Operation
      5. 7.2.5 FIFO and µDMA Operation
        1. 7.2.5.1 Master Module Burst Mode
          1. 7.2.5.1.1 Master Module µDMA Functionality
          2. 7.2.5.1.2 Slave Module
      6. 7.2.6 Command Sequence Flow Charts
        1. 7.2.6.1 I2C Master Command Sequences
        2. 7.2.6.2 I2C Slave Command Sequences
      7. 7.2.7 Initialization and Configuration
    3. 7.3 I2C Registers
  10. 8 SPI (Serial Peripheral Interface)
    1. 8.1 Overview
      1. 8.1.1 Features
    2. 8.2 Functional Description
      1. 8.2.1 SPI
      2. 8.2.2 SPI Transmission
        1. 8.2.2.1 Two Data Pins Interface Mode
        2. 8.2.2.2 Transfer Formats
          1. 8.2.2.2.1 Programmable Word Length
          2. 8.2.2.2.2 Programmable SPI Enable (SPIEN)
          3. 8.2.2.2.3 Programmable SPI Clock (SPICLK)
          4. 8.2.2.2.4 Bit Rate
          5. 8.2.2.2.5 Polarity and Phase
            1. 8.2.2.2.5.1 Transfer Format With PHA = 0
            2. 8.2.2.2.5.2 Transfer Format With PHA = 1
      3. 8.2.3 Master Mode
        1. 8.2.3.1 Interrupt Events in Master Mode
          1. 8.2.3.1.1 TX_empty
          2. 8.2.3.1.2 TX_underflow
          3. 8.2.3.1.3 RX_ full
          4. 8.2.3.1.4 End-of-Word Count
        2. 8.2.3.2 Master Transmit and Receive Mode
        3. 8.2.3.3 SPI Enable Control in Master Mode
          1. 8.2.3.3.1 Keep SPIEN Active Mode (Force SPIEN)
        4. 8.2.3.4 Clock Ratio Granularity
          1. 8.2.3.4.1 FIFO Buffer Management
            1. 8.2.3.4.1.1 Split FIFO
            2. 8.2.3.4.1.2 Buffer Almost Full
            3. 8.2.3.4.1.3 Buffer Almost Empty
            4. 8.2.3.4.1.4 End of Transfer Management
            5. 8.2.3.4.1.5 3- or 4-Pin Mode
      4. 8.2.4 Slave Mode
        1. 8.2.4.1 Interrupts Events in Slave Mode
          1. 8.2.4.1.1 TX_empty
          2. 8.2.4.1.2 TX_underflow
          3. 8.2.4.1.3 RX_ full
          4. 8.2.4.1.4 RX_overflow
          5. 8.2.4.1.5 End-of-Word Count
        2. 8.2.4.2 Slave Transmit and Receive Mode
      5. 8.2.5 Interrupts
        1. 8.2.5.1 Interrupt-Driven Operation
        2. 8.2.5.2 Polling
      6. 8.2.6 DMA Requests
        1. 8.2.6.1 FIFO Buffer Enabled
      7. 8.2.7 Reset
    3. 8.3 Initialization and Configuration
      1. 8.3.1 Basic Initialization
      2. 8.3.2 Master Mode Operation Without Interrupt (Polling)
      3. 8.3.3 Slave Mode Operation With Interrupt
      4. 8.3.4 Generic Interrupt Handler Implementation
    4. 8.4 Access to Data Registers
    5. 8.5 Module Initialization
      1. 8.5.1 Common Transfer Sequence
      2. 8.5.2 End-of-Transfer Sequences
      3. 8.5.3 FIFO Mode
        1. 8.5.3.1 Common Transfer Sequence
        2. 8.5.3.2 Transmit Receive With Word Count
        3. 8.5.3.3 Transmit Receive Without Word Count
    6. 8.6 SPI Registers
  11. 9 General-Purpose Timers
    1. 9.1 Overview
    2. 9.2 Block Diagram
    3. 9.3 Functional Description
      1. 9.3.1 GPTM Reset Conditions
      2. 9.3.2 Timer Modes
        1. 9.3.2.1 One-Shot or Periodic Timer Mode
        2. 9.3.2.2 Input Edge-Count Mode
        3. 9.3.2.3 Input Edge-Time Mode
        4. 9.3.2.4 PWM Mode
      3. 9.3.3 DMA Operation
      4. 9.3.4 Accessing Concatenated 16/32-Bit GPTM Register Values
    4. 9.4 Initialization and Configuration
      1. 9.4.1 One-Shot and Periodic Timer Mode
      2. 9.4.2 Input Edge-Count Mode
      3. 9.4.3 Input Edge-Time Mode
      4. 9.4.4 PWM Mode
    5. 9.5 Timer Registers
  12. 10Watchdog Timer
    1. 10.1 Overview
      1. 10.1.1 Block Diagram
    2. 10.2 Functional Description
      1. 10.2.1 Initialization and Configuration
    3. 10.3 WATCHDOG Registers
    4. 10.4 MCU Watchdog Controller Usage Caveats
      1. 10.4.1 System Watchdog
      2. 10.4.2 System Watchdog Recovery Sequence
  13. 11SD Host Controller Interface
    1. 11.1 Overview
    2. 11.2 SD Host Features
    3. 11.3 1-Bit SD Interface
      1. 11.3.1 Clock and Reset Management
    4. 11.4 Initialization and Configuration Using Peripheral APIs
      1. 11.4.1 Basic Initialization and Configuration
      2. 11.4.2 Sending Command
      3. 11.4.3 Card Detection and Initialization
      4. 11.4.4 Block Read
      5. 11.4.5 Block Write
    5. 11.5 Performance and Testing
    6. 11.6 Peripheral Library APIs
    7. 11.7 SD-HOST Registers
  14. 12Inter-Integrated Sound (I2S) Multichannel Audio Serial Port
    1. 12.1 Overview
      1. 12.1.1 I2S Format
    2. 12.2 Functional Description
    3. 12.3 Programming Model
      1. 12.3.1 Clock and Reset Management
      2. 12.3.2 I2S Data Port Interface
      3. 12.3.3 Initialization and Configuration
    4. 12.4 Peripheral Library APIs for I2S Configuration
      1. 12.4.1 Basic APIs for Enabling and Configuring the Interface
        1. 12.4.1.1 void I2SDisable (unsigned long ulBase)
        2. 12.4.1.2 void I2SEnable (unsigned long ulBase, unsigned long ulMode)
        3. 12.4.1.3 void I2SSerializerConfig (unsigned long ulBase, unsigned long ulDataLine, unsigned long ulSerMode, unsigned long ulInActState)
        4. 12.4.1.4 void I2SConfigSetExpClk (unsigned long ulBase, unsigned long ulI2SClk, unsigned long ulBitClk, unsigned long ulConfig)
      2. 12.4.2 APIs for Data Access if DMA is Not Used
        1. 12.4.2.1 void I2SDataGet (unsigned long ulBase, unsigned long ulDataLine, unsigned long * pulData)
        2. 12.4.2.2 long I2SDataGetNonBlocking (unsigned long ulBase, unsigned long ulDataLine, unsigned long * pulData)
        3. 12.4.2.3 void I2SDataPut (unsigned long ulBase, unsigned long ulDataLine, unsigned long ulData)
        4. 12.4.2.4 void I2SDataPut (unsigned long ulBase, unsigned long ulDataLine, unsigned long ulData)
      3. 12.4.3 APIs for Setting Up, Handling Interrupts, or Getting Status from I2S Peripheral
        1. 12.4.3.1 void I2SIntRegister (unsigned long ulBase, void(*)(void) pfnHandler)
        2. 12.4.3.2 void I2SIntEnable (unsigned long ulBase, unsigned long ulIntFlags)
        3. 12.4.3.3 void I2SIntDisable (unsigned long ulBase, unsigned long ulIntFlags)
        4. 12.4.3.4 unsigned long I2SIntStatus (unsigned long ulBase)
        5. 12.4.3.5 void I2SIntUnregister (unsigned long ulBase)
        6. 12.4.3.6 void I2SIntClear (unsigned long ulBase, unsigned long ulStatFlags)
        7. 12.4.3.7 Values that can be Passed to I2SIntEnable() and I2SIntDisable() as the ulIntFlags Parameter
        8. 12.4.3.8 Values that can be Passed to I2SIntClear() as the ulStatFlags Parameter and Returned from I2SIntStatus()
      4. 12.4.4 APIs to Control FIFO Structures Associated With I2S Peripheral
        1. 12.4.4.1 void I2SRxFIFODisable (unsigned long ulBase)
        2. 12.4.4.2 void I2SRxFIFOEnable (unsigned long ulBase, unsigned long ulRxLevel, unsigned long ulWordsPerTransfer)
        3. 12.4.4.3 unsigned long I2SRxFIFOStatusGet (unsigned long ulBase)
        4. 12.4.4.4 void I2STxFIFODisable (unsigned long ulBase)
        5. 12.4.4.5 void I2STxFIFOEnable (unsigned long ulBase, unsigned long ulTxLevel, unsigned long ulWordsPerTransfer)
        6. 12.4.4.6 unsigned long I2STxFIFOStatusGet (unsigned long ulBase)
    5. 12.5 I2S Registers
  15. 13Analog-to-Digital Converter (ADC)
    1. 13.1 Overview
    2. 13.2 Key Features
    3. 13.3 ADC Register Mapping
    4. 13.4 ADC_MODULE Registers
    5. 13.5 Initialization and Configuration
    6. 13.6 Peripheral Library APIs for ADC Operation
      1. 13.6.1 Overview
      2. 13.6.2 Configuring the ADC Channels
      3. 13.6.3 Basic APIs for Enabling and Configuring the Interface
        1. 13.6.3.1 void ADCEnable (unsigned long ulBase)
        2. 13.6.3.2 void ADCDisable (unsigned long ulBase)
        3. 13.6.3.3 void ADCChannelEnable (unsigned long ulBase, unsigned long ulChannel)
        4. 13.6.3.4 void ADCChannelDisable (unsigned long ulBase, unsigned long ulChannel)
      4. 13.6.4 APIs for Data Transfer [Direct Access to FIFO and DMA Setup]
        1. 13.6.4.1 unsigned char ADCFIFOLvlGet (unsigned long ulBase, unsigned long ulChannel)
        2. 13.6.4.2 unsigned long ADCFIFORead (unsigned long ulBase, unsigned long ulChannel)
        3. 13.6.4.3 void ADCDMAEnable (unsigned long ulBase, unsigned long ulChannel)
        4. 13.6.4.4 void ADCDMADisable (unsigned long ulBase, unsigned long ulChannel)
      5. 13.6.5 APIs for Interrupt Usage
        1. 13.6.5.1 void ADCIntEnable (unsigned long ulBase, unsigned long ulChannel, unsigned long ulIntFlags)
        2. 13.6.5.2 void ADCIntDisable (unsigned long ulBase, unsigned long ulChannel, unsigned long ulIntFlags)
        3. 13.6.5.3 void ADCIntRegister (unsigned long ulBase, unsigned long ulChannel, void(*)(void) pfnHandler)
        4. 13.6.5.4 void ADCIntUnregister (unsigned long ulBase, unsigned long ulChannel)
        5. 13.6.5.5 unsigned long ADCIntStatus (unsigned long ulBase, unsigned long ulChannel)
        6. 13.6.5.6 void ADCIntClear (unsigned long ulBase, unsigned long ulChannel, unsigned long ulIntFlags)
      6. 13.6.6 APIs for Setting Up ADC Timer for Time-Stamping the Samples
        1. 13.6.6.1 void ADCTimerConfig (unsigned long ulBase, unsigned long ulValue)
        2. 13.6.6.2 void ADCTimerDisable (unsigned long ulBase)
        3. 13.6.6.3 void ADCTimerEnable (unsigned long ulBase)
        4. 13.6.6.4 void ADCTimerReset (unsigned long ulBase)
        5. 13.6.6.5 unsigned long ADCTimerValueGet (unsigned long ulBase)
  16. 14Parallel Camera Interface Module
    1. 14.1 Overview
    2. 14.2 Image Sensor Interface
    3. 14.3 Functional Description
      1. 14.3.1 Modes of Operation
      2. 14.3.2 FIFO Buffer
      3. 14.3.3 Reset
      4. 14.3.4 Clock Generation
      5. 14.3.5 Interrupt Generation
      6. 14.3.6 DMA Interface
    4. 14.4 Programming Model
      1. 14.4.1 Camera Core Reset
      2. 14.4.2 Enable the Picture Acquisition
      3. 14.4.3 Disable the Picture Acquisition
    5. 14.5 Interrupt Handling
      1. 14.5.1 FIFO_OF_IRQ (FIFO Overflow)
      2. 14.5.2 FIFO_UF_IRQ (FIFO Underflow)
    6. 14.6 Camera Registers
    7. 14.7 Peripheral Library APIs
    8. 14.8 Developer’s Guide
      1. 14.8.1 Using Peripheral Driver APIs for Capturing an Image
      2. 14.8.2 Using Peripheral Driver APIs for Communicating With Image Sensors
  17. 15Power, Reset, and Clock Management
    1. 15.1 Overview
      1. 15.1.1 Power Management Unit (PMU)
      2. 15.1.2 VBAT Wide-Voltage Connection
      3. 15.1.3 Supply Brownout and Blackout
      4. 15.1.4 Application Processor Power Modes
    2. 15.2 Power Management Control Architecture
      1. 15.2.1 Global Power-Reset-Clock Manager (GPRCM)
      2. 15.2.2 Application Reset-Clock Manager (ARCM)
    3. 15.3 PRCM APIs
      1. 15.3.1  MCU Initialization
      2. 15.3.2  Reset Control
      3. 15.3.3  Peripheral Reset
      4. 15.3.4  Reset Cause
      5. 15.3.5  Clock Control
      6. 15.3.6  Low-Power Modes
      7. 15.3.7  Sleep (SLEEP)
      8. 15.3.8  Low-Power Deep Sleep (LPDS)
      9. 15.3.9  Hibernate (HIB)
      10. 15.3.10 Slow Clock Counter
    4. 15.4 Peripheral Macros
    5. 15.5 Power Management Framework
    6. 15.6 PRCM Registers
  18. 16I/O Pads and Pin Multiplexing
    1. 16.1 Overview
    2. 16.2 I/O Pad Electrical Specifications
    3. 16.3 Analog and Digital Pin Multiplexing
    4. 16.4 Special Analog/Digital Pins
      1. 16.4.1 Pins 45 and 52
      2. 16.4.2 Pins 29 and 30
      3. 16.4.3 Pins 57, 58, 59, and 60
    5. 16.5 Analog Mux Control Registers
    6. 16.6 Pins Available for Applications
    7. 16.7 Functional Pin Mux Configurations
    8. 16.8 Pin Mapping Recommendations
      1. 16.8.1 Pad Configuration Registers for Application Pins
        1. 16.8.1.1 Pad Mux and Electrical Configuration Register Bit Definitions
      2. 16.8.2 PAD Behavior During Reset and Hibernate
      3. 16.8.3 Control Architecture
      4. 16.8.4 CC32xx Pin-mux Examples
      5. 16.8.5 Wake on Pad
      6. 16.8.6 Sense on Power
  19. 17Advance Encryption Standard Accelerator (AES)
    1. 17.1 AES Overview
    2. 17.2 AES Functional Description
      1. 17.2.1 AES Block Diagram
        1. 17.2.1.1 Interfaces
        2. 17.2.1.2 AES Wide-Bus Engine
      2. 17.2.2 AES Algorithm
      3. 17.2.3 AES Operating Modes
        1. 17.2.3.1 Supported Modes of Operation
        2. 17.2.3.2 Extended and Combined Modes of Operations
      4. 17.2.4 Hardware Requests
    3. 17.3 AES Module Programming Guide
      1. 17.3.1 AES Low-Level Programming Models
        1. 17.3.1.1 Global Initialization
        2. 17.3.1.2 Initialization Subsequence
        3. 17.3.1.3 Operational Modes Configuration
        4. 17.3.1.4 AES Events Servicing
    4. 17.4 AES Registers
  20. 18Data Encryption Standard Accelerator (DES)
    1. 18.1 DES Functional Description
    2. 18.2 DES Block Diagram
      1. 18.2.1 µDMA Control
      2. 18.2.2 Interrupt Control
      3. 18.2.3 Register Interface
      4. 18.2.4 DES Enginer
        1. 18.2.4.1 Mode Control FSM
        2. 18.2.4.2 DES Feedback Mode Block
        3. 18.2.4.3 DES Cipher Core
    3. 18.3 DES-Supported Modes of Operation
      1. 18.3.1 ECB Feedback Mode
        1. 18.3.1.1 CBC Feedback Mode
        2. 18.3.1.2 CFB Feedback Mode
    4. 18.4 DES Module Programming Guide – Low-Level Programming Models
      1. 18.4.1 Surrounding Modules Global Initialization
        1. 18.4.1.1 Main Sequence – DES Global Initialization
        2. 18.4.1.2 Subsequence – Configure the DES Algorithm Type
        3. 18.4.1.3 Subsequence – Configure the 3DES Algorithm Type
      2. 18.4.2 Operational Modes Configuration
        1. 18.4.2.1 Main Sequence – DES Polling Mode
        2. 18.4.2.2 DES Interrupt Mode
        3. 18.4.2.3 DES Interrupt DMA Mode
      3. 18.4.3 DES Events Servicing
        1. 18.4.3.1 Interrupt Servicing
        2. 18.4.3.2 Context Input Event Servicing
    5. 18.5 DES Registers
  21. 19SHA/MD5 Accelerator
    1. 19.1 SHA/MD5 Functional Description
      1. 19.1.1 SHA/MD5 Block Diagram
        1. 19.1.1.1 Configuration Registers
        2. 19.1.1.2 Hash/HMAC Engine
        3. 19.1.1.3 Hash Core Control
        4. 19.1.1.4 Host Interface Bank
      2. 19.1.2 µDMA and Interrupt Requests
      3. 19.1.3 Operation Description
        1. 19.1.3.1 SHA Mode
          1. 19.1.3.1.1 Starting a New Hash
          2. 19.1.3.1.2 Outer Digest Registers
          3. 19.1.3.1.3 Inner Digest Registers
          4. 19.1.3.1.4 Closing a Hash
        2. 19.1.3.2 MD5 Mode
          1. 19.1.3.2.1 Starting a New Hash
          2. 19.1.3.2.2 Closing a Hash
        3. 19.1.3.3 Generating a Software Interrupt
      4. 19.1.4 SHA/MD5 Programming Guide
        1. 19.1.4.1 Global Initialization
          1. 19.1.4.1.1 Surrounding Modules Global Initialization
          2. 19.1.4.1.2 Starting a New HMAC using the SHA-1 Hash Function and HMAC Key Processing
          3. 19.1.4.1.3 Subsequence - Continuing a Prior HMAC Using the SHA-1 Hash Function
          4. 19.1.4.1.4 Subsequence - Hashing a Key Bigger than 512 Bits with the SHA-1 Hash Function
          5. 19.1.4.1.5 Operational Modes Configuration
          6. 19.1.4.1.6 SHA/MD5 Event Servicing
            1. 19.1.4.1.6.1 Interrupt Servicing
    2. 19.2 SHA-MD5 Registers
  22. 20Cyclical Redundancy Check (CRC)
    1. 20.1 Functional Description
      1. 20.1.1 CRC Support
        1. 20.1.1.1 CRC Checksum Engine
        2. 20.1.1.2 Data Size
        3. 20.1.1.3 Endian Configuration
    2. 20.2 Initialization and Configuration
      1. 20.2.1 CRC Initialization and Configuration
        1. 20.2.1.1 Data Endian Convention for the CRC Engine
    3. 20.3 CRC Registers
  23. 21On-Chip Parallel Flash
    1. 21.1  Flash Memory Configuration
    2. 21.2  Interrupts
    3. 21.3  Flash Memory Programming
    4. 21.4  32-Word Flash Memory Write Buffer
    5. 21.5  Flash Registers
    6. 21.6  CC323xSF Boot Flow
    7. 21.7  Flash User Application and Memory Partition
    8. 21.8  Programming, Bootstrapping, and Updating the Flash User Application
    9. 21.9  Image Authentication and Integrity Check
    10. 21.10 Debugging Flash User Application Using JTAG
  24. 22Revision History
  25.   A Software Development Kit Examples
  26.   B CC323x Device Miscellaneous Registers
    1. 24.1 DMA_IMR Register (offset = 8Ch) [reset = FF0Fh]
    2. 24.2 DMA_IMS Register (offset = 90h) [reset = 0h]
    3. 24.3 DMA_IMC Register (offset = 94h) [reset = 0h]
    4. 24.4 DMA_ICR Register (offset = 9Ch) [reset = 0h]
    5. 24.5 DMA_MIS Register (offset = A0h) [reset = 0h]
    6. 24.6 DMA_RIS Register (offset = A4h) [reset = 0h]
    7. 24.7 GPTTRIGSEL Register (offset = B0h) [reset = 0h]

4.3.4 DMA_(OFFSET_FROM_DMA_BASE_ADDRESS) Registers

Section 4.3.4 lists the memory-mapped registers for the DMA_(OFFSET_FROM_DMA_BASE_ADDRESS). All register offset addresses not listed in Table 4-10 should be considered as reserved locations and the register contents should not be modified.

Table below lists the DMA channel control structures and registers. The channel control structure shows the layout of one entry in the channel control table. The channel control table is located in system memory, and the location is determined by the application, thus, the base address is n/a (not applicable) and noted as so above the register descriptions. In the table below, the offset for the channel control structures is the offset from the entry in the channel control table. See Channel Configuration table for description of how the entries in the channel control table are located in memory. The DMA register addresses are given as a hexadecimal increment, relative to the DMA base address of 0x400F.F000. Note that the DMA module clock must be enabled before the registers can be programmed. There must be a delay of 3 system clocks after the DMA module clock is enabled before any DMA module registers are accessed.

Table 4-10 DMA_(OFFSET_FROM_DMA_BASE_ADDRESS) Registers
OffsetAcronymRegister NameSection
0hDMA_STATDMA_STATSection 4.3.4.1
4hDMA_CFGDMA ConfigurationSection 4.3.4.2
8hDMA_CTLBASEDMA Channel Control Base PointerSection 4.3.4.3
ChDMA_ALTBASEDMA Alternate Channel Control Base PointerSection 4.3.4.4
10hDMA_WAITSTATDMA Channel Wait-on Request StatusSection 4.3.4.5
14hDMA_SWREQDMA Channel Software RequestSection 4.3.4.6
18hDMA_USEBURSTSETDMA Channel Useburst SetSection 4.3.4.7
1ChDMA_USEBURSTCLRDMA Channel Useburst ClearSection 4.3.4.8
20hDMA_REQMASKSETDMA Channel Request Mask SetSection 4.3.4.9
24hDMA_REQMASKCLRDMA Channel Request Mask ClearSection 4.3.4.10
28hDMA_ENASETDMA Channel Enable SetSection 4.3.4.11
2ChDMA_ENACLRDMA Channel Enable ClearSection 4.3.4.12
30hDMA_ALTSETDMA Channel Primary Alternate SetSection 4.3.4.13
34hDMA_ALTCLRDMA Channel Primary Alternate ClearSection 4.3.4.14
38hDMA_PRIOSETDMA Channel Priority SetSection 4.3.4.15
3ChDMA_PRIOCLRDMA Channel Priority ClearSection 4.3.4.16
4ChDMA_ERRCLRDMA Bus Error ClearSection 4.3.4.17
500hDMA_CHASGNDMA Channel AssignmentSection 4.3.4.18
510hDMA_CHMAP0DMA Channel Map Select 0Section 4.3.4.19
514hDMA_CHMAP1DMA Channel Map Select 1Section 4.3.4.20
518hDMA_CHMAP2DMA Channel Map Select 2Section 4.3.4.21
51ChDMA_CHMAP3DMA Channel Map Select 3Section 4.3.4.22
FB0hDMA_PVDMA Peripheral VersionSection 4.3.4.23

4.3.4.1 DMA_STAT Register (offset = 0h) [reset = 0h]

Register mask: FFE0FFFFh

DMA_STAT is shown in Figure 4-7 and described in Table 4-11.

This register return the status of DMA controller.

Figure 4-7 DMA_STAT Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVEDDMACHANS
R-0hR-X
15141312111098
RESERVED
R-0h
76543210
STATERESERVEDMASTEN
R-0hR-0hR-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 4-11 DMA_STAT Register Field Descriptions
BitFieldTypeResetDescription
31-21RESERVEDR0h
20-16DMACHANSRXAvailable DMA channels minus 1.
This field contains a value equal to the number of DMA channels the DMA controller is configured to use, minus one.
The value of 0x1F corresponds to 32 DMA channels.
15-8RESERVEDR0h
7-4STATER0hControl State Machine Status.
This field shows the current status of the control state machine.
Status can be one of the following 0xA-0xF undefined

0h = Idle

1h = Reading channel controller Data

2h = Reading source end pointer

3h = Reading destination end pointer

4h = Reading source data

5h = Writing destination data

6h = Waiting for DMA request to clear

7h = Writing channel controller data

8h = Stalled

9h = Done

3-1RESERVEDR0h
0MASTENR0h

Master enable status.

0h = DMA controller is disabled

1h = DMA controller is enabled

4.3.4.2 DMA_CFG Register (offset = 4h) [reset = 0h]

DMA_CFG is shown in Figure 4-8 and described in Table 4-12.

This register contain configuration for DMA controller.

Figure 4-8 DMA_CFG Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDMASTEN
R-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 4-12 DMA_CFG Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h
0MASTENR/W0h

Controller Master enable

0h = Disables DMA controller

1h = Enables DMA controller

4.3.4.3 DMA_CTLBASE Register (offset = 8h) [reset = 0h]

DMA_CTLBASE is shown in Figure 4-9 and described in Table 4-13.

Contain the base address of control table. The base address must be aligned to 1024 byte boundary.

Figure 4-9 DMA_CTLBASE Register
313029282726252423222120191817161514131211109876543210
ADDRRESERVED
R/W-0hR-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 4-13 DMA_CTLBASE Register Field Descriptions
BitFieldTypeResetDescription
31-10ADDRR/W0hChannel Control Base Address.

This field contains the pointer to the base address of the channel control table.

The base address must be

1024-byte aligned.
9-0RESERVEDR0h

4.3.4.4 DMA_ALTBASE Register (offset = Ch) [reset = C8h]

DMA_ALTBASE is shown in Figure 4-10 and described in Table 4-14.

This register returns the base address of the alternate channel control data. This register removes the necessity for application software to calculate the base address of the alternate channel control structures..

Figure 4-10 DMA_ALTBASE Register
313029282726252423222120191817161514131211109876543210
ADDR
R/W-C8h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 4-14 DMA_ALTBASE Register Field Descriptions
BitFieldTypeResetDescription
31-0ADDRR/WC8hAlternate Channel Address.

This field provides the base address of the alternate channel control structures

4.3.4.5 DMA_WAITSTAT Register (offset = 10h) [reset = 0h]

DMA_WAITSTAT is shown in Figure 4-11 and described in Table 4-15.

This Register indicates that the DMA channel is waiting on a request. A peripheral can hold off the DMA from performing a single request until the peripheral is ready for a burst request to enhance the DMA performance. The use of this feature is dependent on the design of the peripheral and is not controllable by software in any way. This register cannot be read when the DMA controller is in the reset state.

Figure 4-11 DMA_WAITSTAT Register
313029282726252423222120191817161514131211109876543210
WAITREQ_n
R-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 4-15 DMA_WAITSTAT Register Field Descriptions
BitFieldTypeResetDescription
31-0WAITREQ_nR0hChannel [n] Wait Status These bits provide the channel wait-on-request status.

Bit 0 corresponds to channel 0.

0h = The corresponding channel is not waiting on a request.

1h = The corresponding channel is waiting on a request.

4.3.4.6 DMA_SWREQ Register (offset = 14h) [reset = 0h]

DMA_SWREQ is shown in Figure 4-12 and described in Table 4-16.

Each bit in this register represents the corresponding DMA channel. Setting a bit generates a request for the specified DMA channel.

Figure 4-12 DMA_SWREQ Register
313029282726252423222120191817161514131211109876543210
SWREQ_n
W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 4-16 DMA_SWREQ Register Field Descriptions
BitFieldTypeResetDescription
31-0SWREQ_nW0hChannel [n] Software Request These bits generate software requests.

Bit 0 corresponds to channel 0.

These bits are automatically cleared when the software request has been completed.

0h = No request generated

1h = Generate a software request for the corresponding channel.

4.3.4.7 DMA_USEBURSTSET Register (offset = 18h) [reset = 0h]

DMA_USEBURSTSET is shown in Figure 4-13 and described in Table 4-17.

Each bit of this register represents the corresponding DMA channel. Setting a bit disables the channel's single request input from generating requests, configuring the channel to only accept burst requests. Reading the register returns the status of USEBURST. If the amount of data to transfer is a multiple of the arbitration (burst) size, the corresponding SET[n] bit is cleared after completing the final transfer. If there are fewer items remaining to transfer than the arbitration (burst) size, the DMA controller automatically clears the corresponding SET[n ] bit, allowing the remaining items to transfer using single requests. In order to resume transfers using burst requests, the corresponding bit must be set again. A bit should not be set if the corresponding peripheral does not support the burst request model.

Figure 4-13 DMA_USEBURSTSET Register
313029282726252423222120191817161514131211109876543210
SET_n
W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 4-17 DMA_USEBURSTSET Register Field Descriptions
BitFieldTypeResetDescription
31-0SET_nW0hChannel [n] Useburst Set Bit 0 corresponds to channel 0.

This bit is automatically cleared as described above.

A bit can also be manually cleared by setting the corresponding CLR[n] bit in the DMAUSEBURSTCLR register.

0h = DMA channel [n] responds to single or burst requests.

1h = DMA channel [n] responds only to burst requests

4.3.4.8 DMA_USEBURSTCLR Register (offset = 1Ch) [reset = 0h]

DMA_USEBURSTCLR is shown in Figure 4-14 and described in Table 4-18.

Each bit of this register represents the corresponding DMA channel. Setting a bit clears the corresponding SET[n] bit in the DMAUSEBURSTSET register.

Figure 4-14 DMA_USEBURSTCLR Register
313029282726252423222120191817161514131211109876543210
CLR_n
W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 4-18 DMA_USEBURSTCLR Register Field Descriptions
BitFieldTypeResetDescription
31-0CLR_nW0h

Channel [n] Useburst Clear

0h = No Effect

1h = Setting a bit clears the corresponding SET[n] bit in the DMAUSEBURSTSET register meaning that DMA channel [n] responds to single and burst requests

4.3.4.9 DMA_REQMASKSET Register (offset = 20h) [reset = 0h]

DMA_REQMASKSET is shown in Figure 4-15 and described in Table 4-19.

Each bit of this register represents the corresponding DMA channel. Setting a bit disables DMA requests for the channel. Reading the register returns the request mask status. When a DMA channel's request is masked, that means the peripheral can no longer request DMA transfers. The channel can then be used for software-initiated transfers.

Figure 4-15 DMA_REQMASKSET Register
313029282726252423222120191817161514131211109876543210
SET_n
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 4-19 DMA_REQMASKSET Register Field Descriptions
BitFieldTypeResetDescription
31-0SET_nR/W0hChannel [n] Request Mask.
Set Bit 0 corresponds to channel 0.

A bit can only be cleared by setting the corresponding CLR[n] bit in the DMAREQMASKCLR register.

0h = The peripheral associated with channel [n] is enabled to request DMA transfers

1h = The peripheral associated with channel [n] is not able to request DMA transfers. Channel [n] may be used for software-initiated transfers.

4.3.4.10 DMA_REQMASKCLR Register (offset = 24h) [reset = 0h]

DMA_REQMASKCLR is shown in Figure 4-16 and described in Table 4-20.

Each bit of this register represents the corresponding DMA channel. Setting a bit clears the corresponding SET[n] bit in the DMAREQMASKSET register.

Figure 4-16 DMA_REQMASKCLR Register
313029282726252423222120191817161514131211109876543210
CLR_n
W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 4-20 DMA_REQMASKCLR Register Field Descriptions
BitFieldTypeResetDescription
31-0CLR_nW0hChannel [n] Request Mask Clear Bit 0 corresponds to channel 0.

A bit can only be cleared by setting the corresponding CLR[n] bit in the DMAREQMASKCLR register.

0h = No Effect

1h = Setting a bit clears the corresponding SET[n] bit in the DMAREQMASKSET register meaning that the peripheral associated with channel [n] is enabled to request DMA transfers.

4.3.4.11 DMA_ENASET Register (offset = 28h) [reset = 0h]

DMA_ENASET is shown in Figure 4-17 and described in Table 4-21.

Each bit of the DMAENASET register represents the corresponding DMA channel. Setting a bit enables the corresponding DMA channel. Reading the register returns the enable status of the channels. If a channel is enabled but the request mask is set (DMAREQMASKSET), then the channel can be used for software-initiated transfers.

Figure 4-17 DMA_ENASET Register
313029282726252423222120191817161514131211109876543210
CLR_n
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 4-21 DMA_ENASET Register Field Descriptions
BitFieldTypeResetDescription
31-0CLR_nR/W0hChannel [n] Enable Set.
Bit 0 corresponds to channel 0.

A bit can only be cleared by setting the corresponding CLR[n] bit in the DMAENACLR register or when the end of a DMA transfer occurs.

0h = DMA Channel [n] is disabled.

1h = DMA Channel [n] is enabled.

4.3.4.12 DMA_ENACLR Register (offset = 2Ch) [reset = 0h]

DMA_ENACLR is shown in Figure 4-18 and described in Table 4-22.

Each bit of this register represents the corresponding DMA channel. Setting a bit clears the corresponding SET[n] bit in the DMAENASET register.

Figure 4-18 DMA_ENACLR Register
313029282726252423222120191817161514131211109876543210
CLR_n
W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 4-22 DMA_ENACLR Register Field Descriptions
BitFieldTypeResetDescription
31-0CLR_nW0h

Clear Channel [n] Enable Clear

0h = No effect

1h = Setting a bit clears the corresponding SET[n] bit in the DMAENASET register meaning that channel [n] is disabled for DMA transfers

4.3.4.13 DMA_ALTSET Register (offset = 30h) [reset = 0h]

DMA_ALTSET is shown in Figure 4-19 and described in Table 4-23.

Each bit of this register represents the corresponding DMA channel. Setting a bit configures the DMA channel to use the alternate control data structure. Reading the register returns the status of which control data structure is in use for the corresponding DMA channel. For Ping-Pong and Scatter-Gather cycle types, the DMA controller automatically sets these bits to select the alternate channel control data structure.

Figure 4-19 DMA_ALTSET Register
313029282726252423222120191817161514131211109876543210
SET_n
W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 4-23 DMA_ALTSET Register Field Descriptions
BitFieldTypeResetDescription
31-0SET_nW0h

Channel [n] Alternate Set

0h = DMA channel [n] is using the primary control structure

1h = DMA channel [n] is using the alternate control structure

4.3.4.14 DMA_ALTCLR Register (offset = 34h) [reset = 0h]

DMA_ALTCLR is shown in Figure 4-20 and described in Table 4-24.

Each bit of this register represents the corresponding DMA channel. Setting a bit clears the corresponding SET[n] bit in the DMAALTSET register. For Ping-Pong and Scatter-Gather cycle types, the DMA controller automatically sets these bits to select the alternate channel control data structure.

Figure 4-20 DMA_ALTCLR Register
313029282726252423222120191817161514131211109876543210
CLR_n
W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 4-24 DMA_ALTCLR Register Field Descriptions
BitFieldTypeResetDescription
31-0CLR_nW0h

Channel [n] Alternate Clear

0h = No effect

1h = Setting a bit clears the corresponding SET[n] bit in the DMAALTSET register meaning that channel [n] is using the primary control structure

4.3.4.15 DMA_PRIOSET Register (offset = 38h) [reset = 0h]

DMA_PRIOSET is shown in Figure 4-21 and described in Table 4-25.

Each bit of this register represents the corresponding DMA channel. Setting a bit configures the DMA channel to have a high priority level. Reading the register returns the status of the channel priority mask.

Figure 4-21 DMA_PRIOSET Register
313029282726252423222120191817161514131211109876543210
SET_n
W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 4-25 DMA_PRIOSET Register Field Descriptions
BitFieldTypeResetDescription
31-0SET_nW0h

Channel [n] Priority Set

0h = DMA channel [n] is using the default priority level

1h = DMA channel [n] is using the high priority level

4.3.4.16 DMA_PRIOCLR Register (offset = 3Ch) [reset = 0h]

DMA_PRIOCLR is shown in Figure 4-22 and described in Table 4-26.

Each bit of this register represents the corresponding DMA channel. Setting a bit clears the corresponding SET[n] bit in the DMAPRIOSET register.

Figure 4-22 DMA_PRIOCLR Register
313029282726252423222120191817161514131211109876543210
CLR_n
W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 4-26 DMA_PRIOCLR Register Field Descriptions
BitFieldTypeResetDescription
31-0CLR_nW0h

Channel [n] Priority Clear

0h = No effect

1h = Setting a bit clears the corresponding SET[n] bit in the DMAPRIOSET register meaning that channel [n] is using the default priority level

4.3.4.17 DMA_ERRCLR Register (offset = 4Ch) [reset = 0h]

DMA_ERRCLR is shown in Figure 4-23 and described in Table 4-27.

This register is used to read and clear the DMA bus error status. The error status is set if the DMA controller encountered a bus error while performing a transfer. If a bus error occurs on a channel, that channel is automatically disabled by the DMA controller. The other channels are unaffected.

Figure 4-23 DMA_ERRCLR Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDERRCLR
R-0hR/W1C-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 4-27 DMA_ERRCLR Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR0h
0ERRCLRR/W1C0h

DMA Bus Error Status

0h = No bus error is pending.

1h = A bus error is pending.

4.3.4.18 DMA_CHASGN Register (offset = 500h) [reset = 0h]

DMA_CHASGN is shown in Figure 4-24 and described in Table 4-28.

Each bit of this register represents the corresponding DMA channel. Setting a bit selects the secondary channel assignment.

Figure 4-24 DMA_CHASGN Register
313029282726252423222120191817161514131211109876543210
CHASGN_n
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 4-28 DMA_CHASGN Register Field Descriptions
BitFieldTypeResetDescription
31-0CHASGN_nR/W0h

Channel [n] Assignment Select

0h = Use the primary channel assignment.

1h = Use the secondary channel assignment.

4.3.4.19 DMA_CHMAP0 Register (offset = 510h) [reset = 0h]

DMA_CHMAP0 is shown in Figure 4-25 and described in Table 4-29.

Each 4-bit field of the DMACHMAP0 register configures the DMA channel assignment.

Figure 4-25 DMA_CHMAP0 Register
31302928272625242322212019181716
CH7SEL_nCH6SEL_nCH5SEL_nCH4SEL_n
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
CH3SEL_nCH2SEL_nCH1SEL_nCH0SEL_n
R/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 4-29 DMA_CHMAP0 Register Field Descriptions
BitFieldTypeResetDescription
31-28CH7SEL_nR/W0h

DMA channel 7 source select

27-24CH6SEL_nR/W0h

DMA channel 6 source select

23-20CH5SEL_nR/W0h

DMA channel 5 source select

19-16CH4SEL_nR/W0h

DMA channel 4 source select

15-12CH3SEL_nR/W0h

DMA channel 3 source select

11-8CH2SEL_nR/W0h

DMA channel 2 source select

7-4CH1SEL_nR/W0h

DMA channel 1 source select

3-0CH0SEL_nR/W0h

DMA channel 0 source select

4.3.4.20 DMA_CHMAP1 Register (offset = 514h) [reset = 0h]

DMA_CHMAP1 is shown in Figure 4-26 and described in Table 4-30.

Each 4-bit field of this register configures the DMA channel assignment.

Figure 4-26 DMA_CHMAP1 Register
31302928272625242322212019181716
CH15SEL_nCH14SEL_nCH13SEL_nCH12SEL_n
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
CH11SEL_nCH10SEL_nCH9SEL_nCH8SEL_n
R/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 4-30 DMA_CHMAP1 Register Field Descriptions
BitFieldTypeResetDescription
31-28CH15SEL_nR/W0h

DMA channel 15 source select

27-24CH14SEL_nR/W0h

DMA channel 14 source select

23-20CH13SEL_nR/W0h

DMA channel 13 source select

19-16CH12SEL_nR/W0h

DMA channel 12 source select

15-12CH11SEL_nR/W0h

DMA channel 11 source select

11-8CH10SEL_nR/W0h

DMA channel 10 source select

7-4CH9SEL_nR/W0h

DMA channel 9 source select

3-0CH8SEL_nR/W0h

DMA channel 8 source select

4.3.4.21 DMA_CHMAP2 Register (offset = 518h) [reset = 0h]

DMA_CHMAP2 is shown in Figure 4-27 and described in Table 4-31.

Each 4-bit field of this register configures the DMA channel assignment.

Figure 4-27 DMA_CHMAP2 Register
31302928272625242322212019181716
CH23SEL_nCH22SEL_nCH21SEL_nCH20SEL_n
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
CH19SEL_nCH18SEL_nCH17SEL_nCH16SEL_n
R/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 4-31 DMA_CHMAP2 Register Field Descriptions
BitFieldTypeResetDescription
31-28CH23SEL_nR/W0h

DMA channel 23 source select

27-24CH22SEL_nR/W0h

DMA channel 22 source select

23-20CH21SEL_nR/W0h

DMA channel 21 source select

19-16CH20SEL_nR/W0h

DMA channel 20 source select

15-12CH19SEL_nR/W0h

DMA channel 19 source select

11-8CH18SEL_nR/W0h

DMA channel 18 source select

7-4CH17SEL_nR/W0h

DMA channel 17 source select

3-0CH16SEL_nR/W0h

DMA channel 16 source select

4.3.4.22 DMA_CHMAP3 Register (offset = 51Ch) [reset = 0h]

DMA_CHMAP3 is shown in Figure 4-28 and described in Table 4-32.

Each 4-bit field of this register configures the DMA channel assignment.

Figure 4-28 DMA_CHMAP3 Register
31302928272625242322212019181716
CH31SEL_nCH30SEL_nCH29SEL_nCH28SEL_n
R/W-0hR/W-0hR/W-0hR/W-0h
1514131211109876543210
CH27SEL_nCH26SEL_nCH25SEL_nCH24SEL_n
R/W-0hR/W-0hR/W-0hR/W-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 4-32 DMA_CHMAP3 Register Field Descriptions
BitFieldTypeResetDescription
31-28CH31SEL_nR/W0h

DMA channel 31 source select

27-24CH30SEL_nR/W0h

DMA channel 30 source select

23-20CH29SEL_nR/W0h

DMA channel 29 source select

19-16CH28SEL_nR/W0h

DMA channel 28 source select

15-12CH27SEL_nR/W0h

DMA channel 27 source select

11-8CH26SEL_nR/W0h

DMA channel 26 source select

7-4CH25SEL_nR/W0h

DMA channel 25 source select

3-0CH24SEL_nR/W0h

DMA channel 24 source select

4.3.4.23 DMA_PV Register (offset = FB0h) [reset = 200h]

DMA_PV is shown in Figure 4-29 and described in Table 4-33.

Indicate the version number of peripheral.

Figure 4-29 DMA_PV Register
313029282726252423222120191817161514131211109876543210
RESERVEDMAJVERMINVER
R-0hR-2hR-0h
LEGEND: R/W = Read/Write; R = Read only; W1toCl = Write 1 to clear bit; -n = value after reset
Table 4-33 DMA_PV Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR0h
15-8MAJVERR2h

Major Version

7-0MINVERR0h

Minor Version