ZHCSEA4C May   2015  – December 2020 ADS54J40

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. ADS54J40 Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 AC Characteristics
    7. 7.7 Digital Characteristics
    8. 7.8 Timing Requirements
    9. 7.9 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Inputs
      2. 8.3.2 DDC Block
        1. 8.3.2.1 Decimate-by-2 Filter
        2. 8.3.2.2 Decimate-by-4 Filter Using a Digital Mixer
        3. 8.3.2.3 Decimate-by-4 Filter with IQ Outputs
      3. 8.3.3 SYSREF Signal
        1. 8.3.3.1 SYSREF Not Present (Subclass 0, 2)
      4. 8.3.4 Overrange Indication
        1. 8.3.4.1 Fast OVR
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Mode
      2. 8.4.2 Device Configuration
        1. 8.4.2.1 Serial Interface
        2. 8.4.2.2 Serial Register Write: Analog Bank
        3. 8.4.2.3 Serial Register Readout: Analog Bank
        4. 8.4.2.4 JESD Bank SPI Page Selection
        5. 8.4.2.5 Serial Register Write: JESD Bank
          1. 8.4.2.5.1 Individual Channel Programming
        6. 8.4.2.6 Serial Register Readout: JESD Bank
      3. 8.4.3 JESD204B Interface
        1. 8.4.3.1 JESD204B Initial Lane Alignment (ILA)
        2. 8.4.3.2 JESD204B Test Patterns
        3. 8.4.3.3 JESD204B Frame
        4. 8.4.3.4 JESD204B Frame Assembly with Decimation
          1. 8.4.3.4.1 JESD Transmitter Interface
          2. 8.4.3.4.2 Eye Diagrams
    5. 8.5 Register Maps
      1. 8.5.1 Example Register Writes
      2. 8.5.2 Register Descriptions
        1. 8.5.2.1 General Registers
          1. 8.5.2.1.1 Register 0h (address = 0h)
          2. 8.5.2.1.2 Register 1h (address = 1h)
          3. 8.5.2.1.3 Register 2h (address = 2h)
          4. 8.5.2.1.4 Register 3h (address = 3h)
          5. 8.5.2.1.5 Register 4h (address = 4h)
          6. 8.5.2.1.6 Register 5h (address = 5h)
          7. 8.5.2.1.7 Register 11h (address = 11h)
        2. 8.5.2.2 Master Page (080h) Registers
          1. 8.5.2.2.1  Register 20h (address = 20h), Master Page (080h)
          2. 8.5.2.2.2  Register 21h (address = 21h), Master Page (080h)
          3. 8.5.2.2.3  Register 23h (address = 23h), Master Page (080h)
          4. 8.5.2.2.4  Register 24h (address = 24h), Master Page (080h)
          5. 8.5.2.2.5  Register 26h (address = 26h), Master Page (080h)
          6. 8.5.2.2.6  Register 4Fh (address = 4Fh), Master Page (080h)
          7. 8.5.2.2.7  Register 53h (address = 53h), Master Page (080h)
          8. 8.5.2.2.8  Register 54h (address = 54h), Master Page (080h)
          9. 8.5.2.2.9  Register 55h (address = 55h), Master Page (080h)
          10. 8.5.2.2.10 Register 59h (address = 59h), Master Page (080h)
        3. 8.5.2.3 ADC Page (0Fh) Register
          1. 8.5.2.3.1 Register 5F (addresses = 5F), ADC Page (0Fh)
        4. 8.5.2.4 Main Digital Page (6800h) Registers
          1. 8.5.2.4.1  Register 0h (address = 0h), Main Digital Page (6800h)
          2. 8.5.2.4.2  Register 40h (address = 40h), Main Digital Page (6800h)
          3. 8.5.2.4.3  Register 41h (address = 41h), Main Digital Page (6800h)
          4. 8.5.2.4.4  Register 42h (address = 42h), Main Digital Page (6800h)
          5. 8.5.2.4.5  Register 43h (address = 43h), Main Digital Page (6800h)
          6. 8.5.2.4.6  Register 44h (address = 44h), Main Digital Page (6800h)
          7. 8.5.2.4.7  Register 4Bh (address = 4Bh), Main Digital Page (6800h)
          8. 8.5.2.4.8  Register 4Dh (address = 4Dh), Main Digital Page (6800h)
          9. 8.5.2.4.9  Register 4Eh (address = 4Eh), Main Digital Page (6800h)
          10. 8.5.2.4.10 Register 52h (address = 52h), Main Digital Page (6800h)
          11. 8.5.2.4.11 Register 68h (address = 68h), Main Digital Page (6800h)
          12. 8.5.2.4.12 Register 72h (address = 72h), Main Digital Page (6800h)
          13. 8.5.2.4.13 Register ABh (address = ABh), Main Digital Page (6800h)
          14. 8.5.2.4.14 Register ADh (address = ADh), Main Digital Page (6800h)
          15. 8.5.2.4.15 Register F7h (address = F7h), Main Digital Page (6800h)
        5. 8.5.2.5 JESD Digital Page (6900h) Registers
          1. 8.5.2.5.1  Register 0h (address = 0h), JESD Digital Page (6900h)
          2. 8.5.2.5.2  Register 1h (address = 1h), JESD Digital Page (6900h)
          3. 8.5.2.5.3  Register 2h (address = 2h), JESD Digital Page (6900h)
          4. 8.5.2.5.4  Register 3h (address = 3h), JESD Digital Page (6900h)
          5. 8.5.2.5.5  Register 5h (address = 5h), JESD Digital Page (6900h)
          6. 8.5.2.5.6  Register 6h (address = 6h), JESD Digital Page (6900h)
          7. 8.5.2.5.7  Register 7h (address = 7h), JESD Digital Page (6900h)
          8. 8.5.2.5.8  Register 16h (address = 16h), JESD Digital Page (6900h)
          9. 8.5.2.5.9  Register 31h (address = 31h), JESD Digital Page (6900h)
          10. 8.5.2.5.10 Register 32h (address = 32h), JESD Digital Page (6900h)
        6. 8.5.2.6 JESD Analog Page (6A00h) Registers
          1. 8.5.2.6.1 Register 12h (address = 12h), JESD Analog Page (6A00h)
          2. 8.5.2.6.2 Registers 13h-15h (addresses = 13h-5h), JESD Analog Page (6A00h)
          3. 8.5.2.6.3 Register 16h (address = 16h), JESD Analog Page (6A00h)
          4. 8.5.2.6.4 Register 17h (address = 17h), JESD Analog Page (6A00h)
          5. 8.5.2.6.5 Register 1Ah (address = 1Ah), JESD Analog Page (6A00h)
          6. 8.5.2.6.6 Register 1Bh (address = 1Bh), JESD Analog Page (6A00h)
        7. 8.5.2.7 Offset Read Page (JESD BANK PAGE SEL = 6100h, JESD BANK PAGE SEL1 = 0000h) Registers
          1. 8.5.2.7.1 Register 068h (address = 068h), Offset Read Page
          2. 8.5.2.7.2 Register 069h (address = 069h), Offset Read Page
          3. 8.5.2.7.3 Registers 074h, 076h, 078h, 7Ah (address = 074h, 076h, 078h, 7Ah), Offset Read Page
          4. 8.5.2.7.4 Registers 075h, 077h, 079h, 7Bh (address = 075h, 077h, 079h, 7Bh), Offset Read Page
        8. 8.5.2.8 Offset Load Page (JESD BANK PAGE SEL= 6100h, JESD BANK PAGE SEL1 = 0500h) Registers
          1. 8.5.2.8.1 Registers 00h, 04h, 08h, 0Ch (address = 00h, 04h, 08h, 0Ch), Offset Load Page
          2. 8.5.2.8.2 Registers 01h, 05h, 09h, 0Dh (address = 01h, 05h, 09h, 0Dh), Offset Load Page
          3. 8.5.2.8.3 Registers 78h (address = 78h), Offset Load Page
  9. Application Information Disclaimer
    1. 9.1 Application Information
      1. 9.1.1 Start-Up Sequence
      2. 9.1.2 Hardware Reset
      3. 9.1.3 SNR and Clock Jitter
      4. 9.1.4 DC Offset Correction Block in the ADS54J40
        1. 9.1.4.1 Freezing the DC Offset Correction Block
        2. 9.1.4.2 Effect of Temperature
      5. 9.1.5 Idle Channel Histogram
      6. 9.1.6 Interleaving (IL) Mismatch Compensation
        1. 9.1.6.1 Introduction
        2. 9.1.6.2 Features
        3. 9.1.6.3 Temperature variation
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Transformer-Coupled Circuits
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Sequencing and Initialization
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

AC Characteristics

Typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 1 GSPS, 50% clock duty cycle, AVDD3V = 3 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, –1-dBFS differential input, and 0-dB digital gain (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SNR Signal-to-noise ratio fIN = 10 MHz, AIN = –1 dBFS 69.7 dBFS
fIN = 100 MHz, AIN = –1 dBFS 69.5
fIN = 170 MHz, AIN = –1 dBFS 66.2 68.9
fIN = 230 MHz, AIN = –1 dBFS 68.4
fIN = 270 MHz, AIN = –1 dBFS 67.9
fIN = 300 MHz, AIN = –1 dBFS 67.5
fIN = 370 MHz, AIN = –1 dBFS 66.5
fIN = 470 MHz, AIN = –3 dBFS 66.5
fIN = 720 MHz, AIN = –6 dBFS 64.9
fIN = 720 MHz, AIN = –6 dBFS,
gain = 5 dB
63.3
NSD Noise spectral density fIN = 10 MHz, AIN = -1 dBFS 156.7 dBFS/Hz
fIN = 100 MHz, AIN = –1 dBFS 156.5
fIN = 170 MHz, AIN = –1 dBFS 153.2 155.9
fIN = 230 MHz, AIN = –1 dBFS 155.4
fIN = 270 MHz, AIN = –1 dBFS 154.9
fIN = 300 MHz, AIN = –1 dBFS 154.5
fIN = 370 MHz, AIN = –1 dBFS 153.5
fIN = 470 MHz, AIN = –3 dBFS 153.5
fIN = 720 MHz, AIN = –6 dBFS 151.9
fIN = 720 MHz, AIN = –6 dBFS,
gain = 5 dB
150.3
SINAD Signal-to-noise and distortion ratio fIN = 10 MHz, AIN = –1 dBFS 69.6 dBFS
fIN = 100 MHz, AIN = –1 dBFS 69.3
fIN = 170 MHz, AIN = –1 dBFS 65.2 68.8
fIN = 230 MHz, AIN = –1 dBFS 68.3
fIN = 270 MHz, AIN = –1 dBFS 67.6
fIN = 300 MHz, AIN = –1 dBFS 67
fIN = 370 MHz, AIN = –1 dBFS 65.5
fIN = 470 MHz, AIN = –3 dBFS 65.7
fIN = 720 MHz, AIN = –6 dBFS 64.1
fIN = 720 MHz, AIN = –6 dBFS,
gain = 5 dB
63.2
SFDR Spurious free dynamic range (excluding IL spurs fIN = 100 MHz, AIN = –1 dBFS 83 dBc
fIN = 170 MHz, AIN = –1 dBFS 76 86
fIN = 230 MHz, AIN = –1 dBFS 85
fIN = 270 MHz, AIN = –1 dBFS 81
fIN = 300 MHz, AIN = –1 dBFS 78
fIN = 370 MHz, AIN = –1 dBFS 73
fIN = 470 MHz, AIN = –3 dBFS 71
fIN = 720 MHz, AIN = –6 dBFS 67
fIN = 720 MHz, AIN = –6 dBFS,
gain = 5 dB
71
HD2 Second-order harmonic distortion fIN = 10 MHz, AIN = –1 dBFS 85 dBc
fIN = 100 MHz, AIN = –1 dBFS 90
fIN = 170 MHz, AIN = –1 dBFS 76 92
fIN = 230 MHz, AIN = –1 dBFS 85
fIN = 270 MHz, AIN = –1 dBFS 81
fIN = 300 MHz, AIN = –1 dBFS 81
fIN = 370 MHz, AIN = –1 dBFS 76
fIN = 470 MHz, AIN = –3 dBFS 71
fIN = 720 MHz, AIN = –6 dBFS 67
fIN = 720 MHz, AIN = –6 dBFS,
gain = 5 dB
71
HD3 Third-order harmonic distortio fIN = 10 MHz, AIN = –1 dBFS 85 dBc
fIN = 100 MHz, AIN = –1 dBFS 83
fIN = 170 MHz, AIN = –1 dBFS 76 86
fIN = 230 MHz, AIN = –1 dBFS 87
fIN = 270 MHz, AIN = –1 dBFS 81
fIN = 300 MHz, AIN = –1 dBFS 78
fIN = 370 MHz, AIN = –1 dBFS 73
fIN = 470 MHz, AIN = –3 dBFS 71
fIN = 720 MHz, AIN = –6 dBFS 74
fIN = 720 MHz, AIN = –6 dBFS,
gain = 5 dB
83
Non
HD2, HD3
Spurious-free dynamic range
(excluding HD2, HD3, and IL spur)
fIN = 10 MHz, AIN = –1 dBFS 94 dBFS
fIN = 100 MHz, AIN = –1 dBFS 97
fIN = 170 MHz, AIN = –1 dBFS 79 93
fIN = 230 MHz, AIN = –1 dBFS 95
fIN = 270 MHz, AIN = –1 dBFS 95
fIN = 300 MHz, AIN = –1 dBFS 91
fIN = 370 MHz, AIN = –1 dBFS 85
fIN = 470 MHz, AIN = –3 dBFS 89
fIN = 720 MHz, AIN = –6 dBFS 89
fIN = 720 MHz, AIN = –6 dBFS,
gain = 5 dB
93
ENOB Effective number of bits fIN = 10 MHz, AIN = –1 dBFS 11.3 Bits
fIN = 100 MHz, AIN = –1 dBFS 11.2
fIN = 170 MHz, AIN = –1 dBFS 10.5 11.1
fIN = 230 MHz, AIN = –1 dBFS 11.1
fIN = 270 MHz, AIN = –1 dBFS 10.9
fIN = 300 MHz, AIN = –1 dBFS 10.8
fIN = 370 MHz, AIN = –1 dBFS 10.6
fIN = 470 MHz, AIN = –3 dBFS 10.6
fIN = 720 MHz, AIN = –6 dBFS 10.4
fIN = 720 MHz, AIN = –6 dBFS,
gain = 5 dB
10.2
THD Total harmonic distortion fIN = 10 MHz, AIN = –1 dBFS 82 dBc
fIN = 100 MHz, AIN = –1 dBFS 80
fIN = 170 MHz, AIN = –1 dBFS 73 83
fIN = 230 MHz, AIN = –1 dBFS 82
fIN = 270 MHz, AIN = –1 dBFS 78
fIN = 300 MHz, AIN = –1 dBFS 75
fIN = 370 MHz, AIN = –1 dBFS 70
fIN = 470 MHz, AIN = –3 dBFS 70
fIN = 720 MHz, AIN = –6 dBFS 66
fIN = 720 MHz, AIN = –6 dBFS,
gain = 5 dB
70
SFDR_IL Interleaving spur fIN = 10 MHz, AIN = –1 dBFS 85 dBc
fIN = 100 MHz, AIN = –1 dBFS 84
fIN = 170 MHz, AIN = –1 dBFS 69 83
fIN = 230 MHz, AIN = –1 dBFS 82
fIN = 270 MHz, AIN = –1 dBFS 81
fIN = 300 MHz, AIN = –1 dBFS 81
fIN = 370 MHz, AIN = –1 dBFS 77
fIN = 470 MHz, AIN = –3 dBFS 78
fIN = 720 MHz, AIN = –6 dBFS 78
fIN = 720 MHz, AIN = –6 dBFS,
gain = 5 dB
74
IMD3 Two-tone, third-order intermodulation distortion fIN1 = 185 MHz, fIN2 = 190 MHz,
AIN = –7 dBFS
–89 dBFS
fIN1 = 365 MHz, fIN2 = 370 MHz,
AIN = –7 dBFS
–79
fIN1 = 465 MHz, fIN2 = 470 MHz,
AIN = –7 dBFS
–75
Crosstalk Isolation between channel A and B Full-scale, 170-MHz signal on aggressor; idle channel is victim 100 dB