ZHCSEA4C May 2015 – December 2020 ADS54J40
PRODUCTION DATA
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
LINK LAYER TESTMODE | LINK LAYER RPAT | LMFC MASK RESET | 0 | 0 | 0 | ||
R/W-0h | R/W-0h | R/W-0h | W-0h | W-0h | W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7-5 | LINK LAYER TESTMODE | R/W | 0h | These bits generate a pattern as per section 5.3.3.8.2 of the JESD204B document. 000 = Normal ADC data 001 = D21.5 (high-frequency jitter pattern) 010 = K28.5 (mixed-frequency jitter pattern) 011 = Repeat initial lane alignment (generates a K28.5 character and continuously repeats lane alignment sequences) 100 = 12-octet RPAT jitter pattern All others = Not used |
4 | LINK LAYER RPAT | R/W | 0h | This bit changes the running disparity in the modified RPAT pattern test mode (only when the link layer test mode = 100). 0 = Normal operation 1 = Changes disparity |
3 | LMFC MASK RESET | R/W | 0h | This bit masks the LMFC reset coming to the digital block. 0 = LMFC reset is not masked 1 = Ignore the LMFC reset request |
2-0 | 0 | W | 0h | Must write 0 |