ZHCSEA4C May   2015  – December 2020 ADS54J40

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5  ADS54J40 Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 AC Characteristics
    7. 7.7 Digital Characteristics
    8. 7.8 Timing Requirements
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Inputs
      2. 8.3.2 DDC Block
        1. 8.3.2.1 Decimate-by-2 Filter
        2. 8.3.2.2 Decimate-by-4 Filter Using a Digital Mixer
        3. 8.3.2.3 Decimate-by-4 Filter with IQ Outputs
      3. 8.3.3 SYSREF Signal
        1. 8.3.3.1 SYSREF Not Present (Subclass 0, 2)
      4. 8.3.4 Overrange Indication
        1. 8.3.4.1 Fast OVR
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Mode
      2. 8.4.2 Device Configuration
        1. 8.4.2.1 Serial Interface
        2. 8.4.2.2 Serial Register Write: Analog Bank
        3. 8.4.2.3 Serial Register Readout: Analog Bank
        4. 8.4.2.4 JESD Bank SPI Page Selection
        5. 8.4.2.5 Serial Register Write: JESD Bank
          1. 8.4.2.5.1 Individual Channel Programming
        6. 8.4.2.6 Serial Register Readout: JESD Bank
      3. 8.4.3 JESD204B Interface
        1. 8.4.3.1 JESD204B Initial Lane Alignment (ILA)
        2. 8.4.3.2 JESD204B Test Patterns
        3. 8.4.3.3 JESD204B Frame
        4. 8.4.3.4 JESD204B Frame Assembly with Decimation
          1. 8.4.3.4.1 JESD Transmitter Interface
          2. 8.4.3.4.2 Eye Diagrams
    5. 8.5 Register Maps
      1. 8.5.1 Example Register Writes
      2. 8.5.2 Register Descriptions
        1. 8.5.2.1 General Registers
          1. 8.5.2.1.1 Register 0h (address = 0h)
          2. 8.5.2.1.2 Register 1h (address = 1h)
          3. 8.5.2.1.3 Register 2h (address = 2h)
          4. 8.5.2.1.4 Register 3h (address = 3h)
          5. 8.5.2.1.5 Register 4h (address = 4h)
          6. 8.5.2.1.6 Register 5h (address = 5h)
          7. 8.5.2.1.7 Register 11h (address = 11h)
        2. 8.5.2.2 Master Page (080h) Registers
          1. 8.5.2.2.1  Register 20h (address = 20h), Master Page (080h)
          2. 8.5.2.2.2  Register 21h (address = 21h), Master Page (080h)
          3. 8.5.2.2.3  Register 23h (address = 23h), Master Page (080h)
          4. 8.5.2.2.4  Register 24h (address = 24h), Master Page (080h)
          5. 8.5.2.2.5  Register 26h (address = 26h), Master Page (080h)
          6. 8.5.2.2.6  Register 4Fh (address = 4Fh), Master Page (080h)
          7. 8.5.2.2.7  Register 53h (address = 53h), Master Page (080h)
          8. 8.5.2.2.8  Register 54h (address = 54h), Master Page (080h)
          9. 8.5.2.2.9  Register 55h (address = 55h), Master Page (080h)
          10. 8.5.2.2.10 Register 59h (address = 59h), Master Page (080h)
        3. 8.5.2.3 ADC Page (0Fh) Register
          1. 8.5.2.3.1 Register 5F (addresses = 5F), ADC Page (0Fh)
        4. 8.5.2.4 Main Digital Page (6800h) Registers
          1. 8.5.2.4.1  Register 0h (address = 0h), Main Digital Page (6800h)
          2. 8.5.2.4.2  Register 40h (address = 40h), Main Digital Page (6800h)
          3. 8.5.2.4.3  Register 41h (address = 41h), Main Digital Page (6800h)
          4. 8.5.2.4.4  Register 42h (address = 42h), Main Digital Page (6800h)
          5. 8.5.2.4.5  Register 43h (address = 43h), Main Digital Page (6800h)
          6. 8.5.2.4.6  Register 44h (address = 44h), Main Digital Page (6800h)
          7. 8.5.2.4.7  Register 4Bh (address = 4Bh), Main Digital Page (6800h)
          8. 8.5.2.4.8  Register 4Dh (address = 4Dh), Main Digital Page (6800h)
          9. 8.5.2.4.9  Register 4Eh (address = 4Eh), Main Digital Page (6800h)
          10. 8.5.2.4.10 Register 52h (address = 52h), Main Digital Page (6800h)
          11. 8.5.2.4.11 Register 68h (address = 68h), Main Digital Page (6800h)
          12. 8.5.2.4.12 Register 72h (address = 72h), Main Digital Page (6800h)
          13. 8.5.2.4.13 Register ABh (address = ABh), Main Digital Page (6800h)
          14. 8.5.2.4.14 Register ADh (address = ADh), Main Digital Page (6800h)
          15. 8.5.2.4.15 Register F7h (address = F7h), Main Digital Page (6800h)
        5. 8.5.2.5 JESD Digital Page (6900h) Registers
          1. 8.5.2.5.1  Register 0h (address = 0h), JESD Digital Page (6900h)
          2. 8.5.2.5.2  Register 1h (address = 1h), JESD Digital Page (6900h)
          3. 8.5.2.5.3  Register 2h (address = 2h), JESD Digital Page (6900h)
          4. 8.5.2.5.4  Register 3h (address = 3h), JESD Digital Page (6900h)
          5. 8.5.2.5.5  Register 5h (address = 5h), JESD Digital Page (6900h)
          6. 8.5.2.5.6  Register 6h (address = 6h), JESD Digital Page (6900h)
          7. 8.5.2.5.7  Register 7h (address = 7h), JESD Digital Page (6900h)
          8. 8.5.2.5.8  Register 16h (address = 16h), JESD Digital Page (6900h)
          9. 8.5.2.5.9  Register 31h (address = 31h), JESD Digital Page (6900h)
          10. 8.5.2.5.10 Register 32h (address = 32h), JESD Digital Page (6900h)
        6. 8.5.2.6 JESD Analog Page (6A00h) Registers
          1. 8.5.2.6.1 Register 12h (address = 12h), JESD Analog Page (6A00h)
          2. 8.5.2.6.2 Registers 13h-15h (addresses = 13h-5h), JESD Analog Page (6A00h)
          3. 8.5.2.6.3 Register 16h (address = 16h), JESD Analog Page (6A00h)
          4. 8.5.2.6.4 Register 17h (address = 17h), JESD Analog Page (6A00h)
          5. 8.5.2.6.5 Register 1Ah (address = 1Ah), JESD Analog Page (6A00h)
          6. 8.5.2.6.6 Register 1Bh (address = 1Bh), JESD Analog Page (6A00h)
        7. 8.5.2.7 Offset Read Page (JESD BANK PAGE SEL = 6100h, JESD BANK PAGE SEL1 = 0000h) Registers
          1. 8.5.2.7.1 Register 068h (address = 068h), Offset Read Page
          2. 8.5.2.7.2 Register 069h (address = 069h), Offset Read Page
          3. 8.5.2.7.3 Registers 074h, 076h, 078h, 7Ah (address = 074h, 076h, 078h, 7Ah), Offset Read Page
          4. 8.5.2.7.4 Registers 075h, 077h, 079h, 7Bh (address = 075h, 077h, 079h, 7Bh), Offset Read Page
        8. 8.5.2.8 Offset Load Page (JESD BANK PAGE SEL= 6100h, JESD BANK PAGE SEL1 = 0500h) Registers
          1. 8.5.2.8.1 Registers 00h, 04h, 08h, 0Ch (address = 00h, 04h, 08h, 0Ch), Offset Load Page
          2. 8.5.2.8.2 Registers 01h, 05h, 09h, 0Dh (address = 01h, 05h, 09h, 0Dh), Offset Load Page
          3. 8.5.2.8.3 Registers 78h (address = 78h), Offset Load Page
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
      1. 9.1.1 Start-Up Sequence
      2. 9.1.2 Hardware Reset
      3. 9.1.3 SNR and Clock Jitter
      4. 9.1.4 DC Offset Correction Block in the ADS54J40
        1. 9.1.4.1 Freezing the DC Offset Correction Block
        2. 9.1.4.2 Effect of Temperature
      5. 9.1.5 Idle Channel Histogram
      6. 9.1.6 Interleaving (IL) Mismatch Compensation
        1. 9.1.6.1 Introduction
        2. 9.1.6.2 Features
        3. 9.1.6.3 Temperature variation
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Transformer-Coupled Circuits
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Sequencing and Initialization
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

9.1.6.2 Features

  1. IL mismatch correction has 2 components – Analog Correction component and Digital Correction component. The correction parameters are provided by the ‘IL Mismatch Parameters Estimator’ block shown in Fig 1.
  2. Tracking of IL mismatch parameters happens continuously in the background, based on incoming data (except under certain specific conditions listed in item 5).
  3. IL mismatch estimation uses Nyquist band information programmed by the user, for proper estimation from the input signals. Note that for higher Nyquist signals, the IL spurs are at Fin_alias + kFs/4 (k = 1,2,3) where Fin_alias is the aliased input frequency between [-Fs/2,Fs/2]. This effectively gives the location of IL spurs at the ADC output.
    1. Any change in Nyquist band should be succeeded by a “pulse reset”. A pulse reset signal resets the internal IL mismatch estimation and correction and the JESD link. However; all other registers written into the IL engine or the status of the rest of the system is unaffected by a pulse reset. The IL mismatch parameters would be reestimated for the new Nyquist band after a pulse reset
    2. In typical use cases, signals would be present only within one Nyquist band. However, if there are signals across multiple Nyquist bands (for eg the desired bands in multiple Nyquist bands may not alias after sampling enabling them to be separated later), it is possible that IL performance may be degraded. So it is advisable to disable IL engine to get raw IL performance. The typical raw IL performance is shown in Figure 9-10.
      GUID-20201029-CA0I-2MMC-2DV9-SHRXL7WDB0HB-low.gifFigure 9-10 Typical raw IL Performance.

      Typical raw IL Performance

  4. IL image performance starts to degrade gracefully for signal frequency components > 0.9 x Fs/2, for 1st Nyquist signals, as digital correction cannot accurately correct for signals very close to Nyquist band edge .
    1. For signals in higher Nyquist bands, the performance degrades gracefully for aliased frequency components <0.1Fs/2 or >0.9Fs/2
  5. IL correction accuracy will continue to be maintained unless any of the following conditions are hit:
    1. Persistent Signal absence: The IL estimator works on the input signals to estimate and track IL mismatch parameters over time. So if no input signal is present, then IL mismatch estimation is not possible. See item 5f for further details.GUID-20201023-CA0I-ZXN7-CVSQ-S7BF144C0RBM-low.gif
    2. Persistent very weak signal only: As IL estimator works on input signals, it needs reasonable-powered signals present for some continuous period of time to get IL estimates properly. The signal power in atleast one frequency band of width Fs/256 has to be > -35 dBFs for proper IL estimation. Further such signal needs to be present in chunks of atleast 100 µs for an integrated ON period of at least 10 ms over a total time of 100 ms for proper IL estimation. See item 5f for further details.GUID-20201023-CA0I-Z7TW-XKZ8-PNJFXL9S5802-low.gif
    3. Consistent Signal saturation: Whenever signal is saturated, signal gets distorted and IL estimation is no longer possible. IL estimation is possible if signal amplitude is < -0.5 dBFs for more than 100 µs in one chunk and such chunks make up atleast 10 ms in a 100 ms window. See item 5f for further details.GUID-20201023-CA0I-N6C3-BNSS-PHGT4L2X0D4T-low.gif
    4. Signal presence in a very small band only around kfs/8: If input signal is present only within 5e-7 x Fs of kFs/8 (k = 0,1,2,3), then no IL estimation is possible as the IL signal and IL image are not separable. See item 5f for further details.GUID-20201023-CA0I-RXDK-P6Q9-RWP9LBNJPRHP-low.gif
    5. Presence of high power signal component in the IL image band: In some cases, the signal component (such as Sig1) may be present in the IL image band of other components of the signal (such as Sig0). This signal component in IL image band (Sig1) acts as an interferer for IL estimation of the first component (Sig0). If the ratio of the power of the signal component causing IL mismatch (power of Sig0) to the power of the signal component in the IL image band (power of Sig1) is less than 25 dB, then IL estimation cannot be done for that signal component (Sig0). See item 5f for further detailsGUID-20201023-CA0I-M5H4-R70J-0WJJXLBKTR1B-low.gif
    6. In the normal course of operation, old IL mismatch estimates are retained and used for correction even if there are no current IL mismatch estimates due to any of the conditions listed in 5a – 5e. This enables good performance when any of the conditions in 5a-5e are present for a short duration. However if any of the conditions that prevent estimation listed in 5a – 5e persist for a large time (>40s), then the estimated digital IL mismatch parameters are reset and the digital IL mismatch parameters are re-estimated when the conditions for estimation becomes favorable again.
      • If the user knows apriori that such a condition will occur and would like the old IL correction to be retained, then a good option is to freeze the IL engine as in item 6. This freeze stops the IL engine and so the old IL estimates are not discarded.
      GUID-20201023-CA0I-8L4W-W7QH-QCBGD4NSGHXH-low.gif
    7. Signal and IL image overlap: If signal component is present around kfs/8 (k = 0,1,2,3), then the IL image band will also overlap with the signal making it difficult to estimate IL mismatch parameters. Overlap of signal and IL image bands around kfs/8 should be < Fs/256 MHz for 90% of the time for proper IL estimation. Note that if this condition cannot be ensured, then IL performance will be degraded. If this condition is violated in a known period, then the user can freeze IL engine when this condition occurs as described in section 6. Otherwise, user has to switch to options in items 6 or 7 to avoid performance degradationGUID-20201023-CA0I-DRQD-GHCF-LRRNCH6MZP3T-low.gif
  6. Freezing the IL Engine: If the user knows apriori that any of the conditions in item 5f occurs and would like the old IL correction to be retained, then a good option is to freeze the IL engine. Or, if the user knows that condition in 5g is violated at a known time, then also freezing the IL engine is a good option. Once IL engine is frozen, all past IL estimates/correction are retained and no updates are done to the IL estimates. Once the conditions described above are no longer present, then the IL engine can be unfrozen. The IL engine then starts updating the estimates as though the entire period for which it was frozen did not exist at all.
    Table 9-4 IL Freeze
    SPI AddressSPI DataComments
    0x40050x1Enable per channel writes
    0x40040x68Page Select
    0x40030x00Page Select
    0x40020x00Page Select
    0x40010x00Page Select
    0x604D0x01Validity for IL Freeze/Unfreeze for CHA
    0x704D0x01Validity for IL Freeze/Unfreeze for CHB
    0x60680x04Freeze IL Engine for CHA
    0x70680x04Freeze IL Engine for CHB
    0x40040x61Page Select
    0x40030x00Page Select
    0x40020x05Page Select
    0x40010x00Page Select
    0x60780x00IL Engine Freeze Secondary Control for CHA
    0x70780x00IL Engine Freeze Secondary Control for CHB
    0x40040x68Page Select
    0x40030x00Page Select
    0x40020x00Page Select
    0x40010x00Page Select
    Table 9-5 IL Unfreeze
    SPI AddressSPI DataComments
    0x40050x00Enable per channel writes
    0x40040x68Page Select
    0x40030x00Page Select
    0x40020x00Page Select
    0x40010x00Page Select
    0x604D0x01Validity for IL Freeze/Unfreeze for CHA
    0x704D0x01Validity for IL Freeze/Unfreeze for CHB
    0x60680x00Unfreeze IL Engine for CHA
    0x70680x00Unfreeze IL Engine for CHB
  7. In case the limitations in items 5 cannot be worked around in the user system and the limitations are permanent (eg a system where the entire band from [0,fs/2) is nearly fully occupied or signals present around kfs/8 with overlap < Fs/256), then there are 2 options
    1. Power up/Temp based IL calibration - Do calibration using a single tone (single tone frequency in [0.77fs/2, 0.9 x fs/2], single tone power in [-0.5, -25] dBFs), either one-time or whenever temperature changes by more than a desired threshold, and then freeze IL estimation module. During calibration, the normal input should be bypassed and the calibration signal should be input to ADS54J40 for 100 ms for high power signals (≥ - 3 dBFs) and 500 ms for lower powered signals. Once the calibration time is complete, IL estimation should be frozen and normal signal may be input to ADS54J40. To determine the temperature change for which calibration needs to be done, the user can refer to typical variation of IL spur with temperature, under freeze conditions, as shown in Figure 9-11 .
      GUID-20201023-CA0I-5JTG-8RQ7-FLZW7JKHTHML-low.gifFigure 9-11 Flowchart for Powerup IL Calibratuion
      GUID-20201023-CA0I-BRVG-6SG3-3V7S0XHMJ8HF-low.gifFigure 9-12 Flow chart for intermittent IL calibration
    2. Disable IL correction – IL performance would be limited to raw IL performance as shown in figure in the data sheet. Note that the disable IL correction sequence includes “pulse reset”. A pulse reset signal resets the internal IL mismatch estimation and correction and the JESD link. Therefore, in case IL correction disable is desired, it is preferable to insert this sequence within the device bring up sequence, just before the final pulse reset is issued.
      Table 9-6 IL Disable
      SPI AddressSPI DataComments
      0x40050x0Enable single channel writes
      0x40040x68Selecting page
      0x40030x00Selecting page
      0x40020x00Selecting page
      0x40010x00Selecting page
      0x604B0x04Validity for IL Correction Disable for CHA
      0x704B0x04Validity for IL Correction Disable for CHB
      0x60400x08Disable IL Correction for CHA
      0x70400x08Disable IL Correction for CHB
      0x60000x01Pulse reset assert
      0x60000x00Pulse reset de-assert