ZHCSEA4C May   2015  – December 2020 ADS54J40

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. ADS54J40 Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 AC Characteristics
    7. 7.7 Digital Characteristics
    8. 7.8 Timing Requirements
    9. 7.9 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Inputs
      2. 8.3.2 DDC Block
        1. 8.3.2.1 Decimate-by-2 Filter
        2. 8.3.2.2 Decimate-by-4 Filter Using a Digital Mixer
        3. 8.3.2.3 Decimate-by-4 Filter with IQ Outputs
      3. 8.3.3 SYSREF Signal
        1. 8.3.3.1 SYSREF Not Present (Subclass 0, 2)
      4. 8.3.4 Overrange Indication
        1. 8.3.4.1 Fast OVR
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Mode
      2. 8.4.2 Device Configuration
        1. 8.4.2.1 Serial Interface
        2. 8.4.2.2 Serial Register Write: Analog Bank
        3. 8.4.2.3 Serial Register Readout: Analog Bank
        4. 8.4.2.4 JESD Bank SPI Page Selection
        5. 8.4.2.5 Serial Register Write: JESD Bank
          1. 8.4.2.5.1 Individual Channel Programming
        6. 8.4.2.6 Serial Register Readout: JESD Bank
      3. 8.4.3 JESD204B Interface
        1. 8.4.3.1 JESD204B Initial Lane Alignment (ILA)
        2. 8.4.3.2 JESD204B Test Patterns
        3. 8.4.3.3 JESD204B Frame
        4. 8.4.3.4 JESD204B Frame Assembly with Decimation
          1. 8.4.3.4.1 JESD Transmitter Interface
          2. 8.4.3.4.2 Eye Diagrams
    5. 8.5 Register Maps
      1. 8.5.1 Example Register Writes
      2. 8.5.2 Register Descriptions
        1. 8.5.2.1 General Registers
          1. 8.5.2.1.1 Register 0h (address = 0h)
          2. 8.5.2.1.2 Register 1h (address = 1h)
          3. 8.5.2.1.3 Register 2h (address = 2h)
          4. 8.5.2.1.4 Register 3h (address = 3h)
          5. 8.5.2.1.5 Register 4h (address = 4h)
          6. 8.5.2.1.6 Register 5h (address = 5h)
          7. 8.5.2.1.7 Register 11h (address = 11h)
        2. 8.5.2.2 Master Page (080h) Registers
          1. 8.5.2.2.1  Register 20h (address = 20h), Master Page (080h)
          2. 8.5.2.2.2  Register 21h (address = 21h), Master Page (080h)
          3. 8.5.2.2.3  Register 23h (address = 23h), Master Page (080h)
          4. 8.5.2.2.4  Register 24h (address = 24h), Master Page (080h)
          5. 8.5.2.2.5  Register 26h (address = 26h), Master Page (080h)
          6. 8.5.2.2.6  Register 4Fh (address = 4Fh), Master Page (080h)
          7. 8.5.2.2.7  Register 53h (address = 53h), Master Page (080h)
          8. 8.5.2.2.8  Register 54h (address = 54h), Master Page (080h)
          9. 8.5.2.2.9  Register 55h (address = 55h), Master Page (080h)
          10. 8.5.2.2.10 Register 59h (address = 59h), Master Page (080h)
        3. 8.5.2.3 ADC Page (0Fh) Register
          1. 8.5.2.3.1 Register 5F (addresses = 5F), ADC Page (0Fh)
        4. 8.5.2.4 Main Digital Page (6800h) Registers
          1. 8.5.2.4.1  Register 0h (address = 0h), Main Digital Page (6800h)
          2. 8.5.2.4.2  Register 40h (address = 40h), Main Digital Page (6800h)
          3. 8.5.2.4.3  Register 41h (address = 41h), Main Digital Page (6800h)
          4. 8.5.2.4.4  Register 42h (address = 42h), Main Digital Page (6800h)
          5. 8.5.2.4.5  Register 43h (address = 43h), Main Digital Page (6800h)
          6. 8.5.2.4.6  Register 44h (address = 44h), Main Digital Page (6800h)
          7. 8.5.2.4.7  Register 4Bh (address = 4Bh), Main Digital Page (6800h)
          8. 8.5.2.4.8  Register 4Dh (address = 4Dh), Main Digital Page (6800h)
          9. 8.5.2.4.9  Register 4Eh (address = 4Eh), Main Digital Page (6800h)
          10. 8.5.2.4.10 Register 52h (address = 52h), Main Digital Page (6800h)
          11. 8.5.2.4.11 Register 68h (address = 68h), Main Digital Page (6800h)
          12. 8.5.2.4.12 Register 72h (address = 72h), Main Digital Page (6800h)
          13. 8.5.2.4.13 Register ABh (address = ABh), Main Digital Page (6800h)
          14. 8.5.2.4.14 Register ADh (address = ADh), Main Digital Page (6800h)
          15. 8.5.2.4.15 Register F7h (address = F7h), Main Digital Page (6800h)
        5. 8.5.2.5 JESD Digital Page (6900h) Registers
          1. 8.5.2.5.1  Register 0h (address = 0h), JESD Digital Page (6900h)
          2. 8.5.2.5.2  Register 1h (address = 1h), JESD Digital Page (6900h)
          3. 8.5.2.5.3  Register 2h (address = 2h), JESD Digital Page (6900h)
          4. 8.5.2.5.4  Register 3h (address = 3h), JESD Digital Page (6900h)
          5. 8.5.2.5.5  Register 5h (address = 5h), JESD Digital Page (6900h)
          6. 8.5.2.5.6  Register 6h (address = 6h), JESD Digital Page (6900h)
          7. 8.5.2.5.7  Register 7h (address = 7h), JESD Digital Page (6900h)
          8. 8.5.2.5.8  Register 16h (address = 16h), JESD Digital Page (6900h)
          9. 8.5.2.5.9  Register 31h (address = 31h), JESD Digital Page (6900h)
          10. 8.5.2.5.10 Register 32h (address = 32h), JESD Digital Page (6900h)
        6. 8.5.2.6 JESD Analog Page (6A00h) Registers
          1. 8.5.2.6.1 Register 12h (address = 12h), JESD Analog Page (6A00h)
          2. 8.5.2.6.2 Registers 13h-15h (addresses = 13h-5h), JESD Analog Page (6A00h)
          3. 8.5.2.6.3 Register 16h (address = 16h), JESD Analog Page (6A00h)
          4. 8.5.2.6.4 Register 17h (address = 17h), JESD Analog Page (6A00h)
          5. 8.5.2.6.5 Register 1Ah (address = 1Ah), JESD Analog Page (6A00h)
          6. 8.5.2.6.6 Register 1Bh (address = 1Bh), JESD Analog Page (6A00h)
        7. 8.5.2.7 Offset Read Page (JESD BANK PAGE SEL = 6100h, JESD BANK PAGE SEL1 = 0000h) Registers
          1. 8.5.2.7.1 Register 068h (address = 068h), Offset Read Page
          2. 8.5.2.7.2 Register 069h (address = 069h), Offset Read Page
          3. 8.5.2.7.3 Registers 074h, 076h, 078h, 7Ah (address = 074h, 076h, 078h, 7Ah), Offset Read Page
          4. 8.5.2.7.4 Registers 075h, 077h, 079h, 7Bh (address = 075h, 077h, 079h, 7Bh), Offset Read Page
        8. 8.5.2.8 Offset Load Page (JESD BANK PAGE SEL= 6100h, JESD BANK PAGE SEL1 = 0500h) Registers
          1. 8.5.2.8.1 Registers 00h, 04h, 08h, 0Ch (address = 00h, 04h, 08h, 0Ch), Offset Load Page
          2. 8.5.2.8.2 Registers 01h, 05h, 09h, 0Dh (address = 01h, 05h, 09h, 0Dh), Offset Load Page
          3. 8.5.2.8.3 Registers 78h (address = 78h), Offset Load Page
  9. Application Information Disclaimer
    1. 9.1 Application Information
      1. 9.1.1 Start-Up Sequence
      2. 9.1.2 Hardware Reset
      3. 9.1.3 SNR and Clock Jitter
      4. 9.1.4 DC Offset Correction Block in the ADS54J40
        1. 9.1.4.1 Freezing the DC Offset Correction Block
        2. 9.1.4.2 Effect of Temperature
      5. 9.1.5 Idle Channel Histogram
      6. 9.1.6 Interleaving (IL) Mismatch Compensation
        1. 9.1.6.1 Introduction
        2. 9.1.6.2 Features
        3. 9.1.6.3 Temperature variation
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Transformer-Coupled Circuits
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Sequencing and Initialization
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Typical Characteristics

Typical values are at TA = 25°C, full temperature range is from TMIN = –40°C to TMAX = 85°C, ADC sampling rate = 1.0 GSPS, 50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input, unless otherwise noted.

GUID-4652BF64-7194-4EFE-AA47-5475F848DC1A-low.gif
SNR = 69.7 dBFS; SFDR = 85 dBc; IL spur = 86 dBc; non HD2, HD3 spur = 89 dBc
Figure 7-3 FFT for 10-MHz Input Signal
GUID-D1E5D703-C098-4FB5-8E4A-FE202C4D9D23-low.gif
SNR = 68.9 dBFS; SFDR = 86 dBc; IL spur = 84 dBc; non HD2, HD3 spur = 89 dBc
Figure 7-5 FFT for 170-MHz Input Signal
GUID-2CB12EB6-D917-48D0-B733-5007FE03E081-low.gif
SNR = 67.4 dBFS; SFDR = 77 dBc; IL spur = 83 dBc; non HD2, HD3 spur = 85 dBc
Figure 7-7 FFT for 300-MHz Input Signal
GUID-B0823818-9E70-4C48-AFC4-0557F76E73F9-low.gif
SNR = 66.5 dBFS; SFDR = 73 dBc; IL spur = 81 dBc; non HD2, HD3 spur = 88 dBc
Figure 7-9 FFT for 470-MHz Input Signal at –3 dBFS
GUID-86CA2EEC-DC1D-49A7-B10F-CB7B076317FD-low.gif
fIN1 = 185 MHz, fIN2 = 190 MHz, each tone at –7 dBFS, IMD3 = 85 dBFS
Figure 7-11 FFT for Two-Tone Input Signal (–7 dBFS)
GUID-FE7BAEE8-4B4E-4469-8591-4651B6F325BD-low.gif
fIN1 = 370 MHz, fIN2 = 365 MHz, each tone at –7 dBFS, IMD3 = 80 dBFS
Figure 7-13 FFT for Two-Tone Input Signal (–7 dBFS)
GUID-139D9BB0-D932-406A-ADD9-7D867396BC8C-low.gif
fIN1 = 470 MHz, fIN2 = 465 MHz, each tone at –7 dBFS, IMD3 = 74.9 dBFS
Figure 7-15 FFT for Two-Tone Input Signal (–7 dBFS)
GUID-9FC0D3A9-027A-4CB7-B826-A2CA6673DD8A-low.gif
fIN1 = 185 MHz, fIN2 = 190 MHz
Figure 7-17 Intermodulation Distortion vs Input Tone Amplitude
GUID-C1A2699E-AA75-4A6E-A087-CD0E61CBB1AC-low.gif
fIN1 = 465 MHz, fIN2 = 470 MHz
Figure 7-19 Intermodulation Distortion vs Input Tone Amplitude
GUID-20201029-CA0I-2MMC-2DV9-SHRXL7WDB0HB-low.gifFigure 7-21 IL Spur vs Input Frequency
GUID-F920390A-F6A1-4B68-B292-56C5B6027590-low.gif
fIN = 170 MHz
Figure 7-23 Signal-to-Noise Ratio vs AVDD Supply and Temperature
GUID-3ABA551F-F294-49FF-9BD5-FED7C960A402-low.gif
fIN = 350 MHz
Figure 7-25 Signal-to-Noise Ratio vs AVDD Supply and Temperature
GUID-76DFE804-96CD-4D96-8EC9-1D8289B7F62A-low.gif
fIN = 170 MHz
Figure 7-27 Signal-to-Noise Ratio vs DVDD Supply and Temperature
GUID-B361D6F7-311B-4DD7-AB4A-BBB5B7A6764E-low.gif
fIN = 350 MHz
Figure 7-29 Signal-to-Noise Ratio vs DVDD Supply and Temperature
GUID-A1A923C4-9453-41E1-877D-864BFFFDD2C2-low.gif
fIN = 170 MHz
Figure 7-31 Signal-to-Noise Ratio vs AVDD3V Supply and Temperature
GUID-28E9983F-1880-4CAC-A83D-BB164D322CB7-low.gif
fIN = 350 MHz
Figure 7-33 Signal-to-Noise Ratio vs AVDD3V Supply and Temperature
GUID-7F90F4F5-0F69-4CAC-B237-5EE65818287E-low.gifFigure 7-35 Signal-to-Noise Ratio vs Gain and Input Frequency
GUID-EEA0D1FB-596F-42C2-8C66-0CC34F97BFF5-low.gifFigure 7-37 Maximum Supported Amplitude vs Frequency
GUID-D16C1F24-8882-40CF-BF41-2B87E45606EE-low.gif
fIN = 350 MHz
Figure 7-39 Performance vs Input Amplitude
GUID-6ABD2897-2F32-42D5-A7AE-79C6AA36E25D-low.gif
fIN = 350 MHz
Figure 7-41 Performance vs Sampling Clock Amplitude
GUID-F1C88B33-26DC-4D6C-B166-18886AD80B33-low.gif
fIN = 350 MHz
Figure 7-43 Performance vs Input Clock Duty Cycle
GUID-0B4C9881-5A54-460A-9C7F-B00DD85215EF-low.gif
fIN = 170 MHz , AIN = –1 dBFS, SINAD = 65.7 dBFS, SFDR = 79 dBc, fPSRR = 5 MHz, APSRR = 25 mVPP, amplitude of fIN – fPSRR = –74 dBFS, amplitude of fIN + fPSRR = –76 dBFS
Figure 7-45 Power-Supply Rejection Ratio FFT for Test Signals on the AVDD Supply
GUID-D9904C87-EA09-44FB-93BE-22C5B2D4F03B-low.gif
fIN = 170.1 MHz , AIN = –1 dBFS, fCMRR = 5 MHz, ACMRR = 50 mVPP, SINAD = 67.3 dBFS, SFDR = 85 dBc, amplitude of fIN ± fCMRR= –80 dBFS
Figure 7-47 Common-Mode Rejection Ratio FFT
GUID-1F0431FE-6CD5-4280-B581-6D6A476AFCA2-low.gifFigure 7-49 Power vs Temperature
GUID-BF6F1025-CEC0-4B47-9AFF-223F6EBBFE7F-low.gif
SNR = 72.5 dBFS, SFDR = 87 dBc
Figure 7-51 FFT for 170-MHz Input Signal in Decimate-by-4 Mode
GUID-7AF2E03B-E336-4769-8FC7-EE80EAEBCEE2-low.gif
SNR = 68.7 dBFS, SFDR = 83 dBc
Figure 7-53 FFT for 450-MHz Input Signal in Decimate-by-4 Mode
GUID-23FBBD19-AAFF-41C2-9862-00C7461338F6-low.gif
SNR = 67.6 dBFS, SFDR = 80 dBc
Figure 7-55 FFT for 350-MHz Input Signal in Decimate-by-2 Mode
GUID-F5F1FB8E-B8A2-4B34-B1CE-A33B461FCF96-low.gif
SNR = 69.2 dBFS; SFDR = 86 dBc; IL spur = 85 dBc; non HD2, HD3 spur = 94 dBc
Figure 7-4 FFT for 140-MHz Input Signal
GUID-DE6423AF-9125-416E-974E-7974C99BE579-low.gif
SNR = 68.1 dBFS; SFDR = 84 dBc; IL spur = 86 dBc; non HD2, HD3 spur = 86 dBc
Figure 7-6 FFT for 230-MHz Input Signal
GUID-93C05910-1DE1-4765-AF0D-BE1DBC658175-low.gif
SNR = 66.2 dBFS; SFDR = 72 dBc; IL spur = 84 dBc; non HD2, HD3 spur = 78 dBc
Figure 7-8 FFT for 370-MHz Input Signal
GUID-C2B3C2E9-8191-49FF-A5E4-0870C2ED510F-low.gif
SNR = 65.3 dBFS; SFDR = 71 dBc; IL spur = 83 dBc; non HD2, HD3 spur = 89 dBFS
Figure 7-10 FFT for 720-MHz Input Signal at –6 dBFS
GUID-DECD49CC-9F43-4FA2-880A-B5D96C7098B2-low.gif
fIN1 = 185 MHz, fIN2 = 190 MHz, each tone at –36 dBFS, IMD3 = 103 dBFS
Figure 7-12 FFT for Two-Tone Input Signal (–36 dBFS)
GUID-65AC4AB1-3BD4-4414-B11C-37DED2C44519-low.gif
fIN1 = 370 MHz, fIN2 = 365 MHz, each tone at –36 dBFS, IMD3 = 109 dBFS
Figure 7-14 FFT for Two-Tone Input Signal (–36 dBFS)
GUID-8530DBFF-A118-48D5-88F9-6723378BB106-low.gif
fIN1 = 470 MHz, fIN2 = 465 MHz, each tone at –36 dBFS, IMD3 = 109.2 dBFS
Figure 7-16 FFT for Two-Tone Input Signal (–36 dBFS)
GUID-DC0A5BBB-C85C-4454-B444-6166461F83EA-low.gif
fIN1 = 365 MHz, fIN2 = 370 MHz
Figure 7-18 Intermodulation Distortion vs Input Tone Amplitude
GUID-8894D306-5499-424B-9E8C-4B8702B323B6-low.gifFigure 7-20 Spurious-Free Dynamic Range vs Input Frequency
GUID-9E42BE5D-B068-4C9A-8DA4-29AAE0D787EE-low.gifFigure 7-22 Signal-to-Noise Ratio vs Input Frequency
GUID-FA460644-B773-4214-84A1-97A747C9FBC0-low.gif
fIN = 170 MHz
Figure 7-24 Spurious-Free Dynamic Range vs AVDD Supply and Temperature
GUID-1B98C607-D667-456F-BA69-B25E54A1FD61-low.gif
fIN = 350 MHz
Figure 7-26 Spurious-Free Dynamic Range vs AVDD Supply and Temperature
GUID-55488CD7-F23D-4209-AE65-58644B66B4BB-low.gif
fIN = 170 MHz
Figure 7-28 Spurious-Free Dynamic Range vs DVDD Supply and Temperature
GUID-67D3EF6B-5E7A-4934-B1A6-B998CF555AEA-low.gif
fIN = 350 MHz
Figure 7-30 Spurious-Free Dynamic Range vs DVDD Supply and Temperature
GUID-CD87918E-8ABB-4283-A95A-7E55519F8444-low.gif
fIN = 170 MHz
Figure 7-32 Spurious-Free Dynamic Range vs AVDD3V Supply and Temperature
GUID-E28159C3-D3C9-4716-BE50-376C06008B63-low.gif
fIN = 350 MHz
Figure 7-34 Spurious-Free Dynamic Range vs AVDD3V Supply and Temperature
GUID-142633FB-F909-4E25-B4F1-5F12ED6826F7-low.gifFigure 7-36 Spurious-Free Dynamic Range vs Gain and Input Frequency
GUID-7CBDDCBB-18C3-437F-8F78-EA90DBC4C248-low.gif
fIN = 170 MHz
Figure 7-38 Performance vs Input Amplitude
GUID-4A4CF536-FFC3-47CF-B38B-0D540D0B6D4E-low.gif
fIN = 170 MHz
Figure 7-40 Performance vs Sampling Clock Amplitude
GUID-6B339B2A-EEA9-41C8-9B82-34C97FF91635-low.gif
fIN = 170 MHz
Figure 7-42 Performance vs Input Clock Duty Cycle
GUID-7F103B3F-4BFA-4578-AC4D-15680F6921A0-low.gif
fIN = 170 MHz
Figure 7-44 Power-Supply Rejection Ratio vs Test Signal Frequency
GUID-36373ED9-534F-4A59-81E5-3D3158BE4418-low.gif
fIN = 170 MHz
Figure 7-46 Common-Mode Rejection Ratio vs Test Signal Frequency
GUID-BE61DA95-2859-4AF2-9EC8-BC892B728516-low.gifFigure 7-48 Power Consumption vs Sampling Speed
GUID-12E2977C-634B-4677-9179-E8B15CDB592D-low.gif
SNR = 73.1 dBFS, SFDR = 88.6 dBc
Figure 7-50 FFT for 60-MHz Input Signal in Decimate-by-4 Mode
GUID-31D26261-204F-42A7-9BF2-C82AC8BD335C-low.gif
SNR = 71.1 dBFS, SFDR = 86 dBc
Figure 7-52 FFT for 300-MHz Input Signal in Decimate-by-4 Mode
GUID-08728E5C-1796-4ACD-959C-84FE95EBE2F2-low.gif
SNR = 70.5 dBFS, SFDR = 86 dBc
Figure 7-54 FFT for 170-MHz Input Signal in Decimate-by-2 Mode