ZHCSEA4 数据表 | 德州仪器 TI.com.cn

ZHCSEA4C May 2015 – December 2020 ADS54J40

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RMP|72
- MPQF396A

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7.8 Timing Requirements

Typical values are at T_A = 25°C, full temperature range is from T_MIN = –40°C to T_MAX = 85°C, ADC sampling rate = 1.0 GSPS, 50% clock duty cycle, AVDD3V = 3.0 V, AVDD = DVDD = 1.9 V, IOVDD = 1.15 V, and –1-dBFS differential input, unless otherwise noted.

		MIN	TYP	MAX	UNITS
SAMPLE TIMING (TBD are any of these Switching Characteristics?TBD: No)
	Aperture delay	0.75		1.6	ns
	Aperture delay matching between two channels on the same device		±70		ps
	Aperture delay matching between two devices at the same temperature and supply voltage		±270		ps
	Aperture jitter		120		f_S rms
WAKE-UP TIMING
	Wake-up time to valid data after coming out of global power-down		150		µs
LATENCY⁽¹⁾
	Data latency: ADC sample to digital output		134		Input clock cycles
	OVR latency: ADC sample to OVR bit		62		Input clock cycles
	FOVR latency: ADC sample to FOVR signal on pin		18		Input clock cycles
t_PDI	Propagation delay: logic gates and output buffers delay (does not change with f_S)		4		ns
SYSREF TIMING
t_{SU_SYSREF}	Setup time for SYSREF, referenced to the input clock falling edge	300		900	ps
t_{H_SYSREF}	Hold time for SYSREF, referenced to the input clock falling edge	100			ps
JESD OUTPUT INTERFACE TIMING CHARACTERISTICS
	Unit interval	100		400	ps
	Serial output data rate	2.5		10	Gbps
	Total jitter for BER of 1E-15 and lane rate = 10 Gbps		26		ps
	Random jitter for BER of 1E-15 and lane rate = 10 Gbps		0.75		ps rms
	Deterministic jitter for BER of 1E-15 and lane rate = 10 Gbps		12		ps, pk-pk
t_R, t_F	Data rise time, data fall time: rise and fall times are measured from 20% to 80%, differential output waveform, 2.5 Gbps ≤ bit rate ≤ 10 Gbps		35		ps

(1) Overall latency = latency + t_PDI.

Figure 7-1 SYSREF Timing

Figure 7-2 Sample Timing Requirements