ZHCSEA4C May 2015 – December 2020 ADS54J40
PRODUCTION DATA
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | PLL RESET | LANE PDN 1 | 0 | LANE PDN 0 | 0 | 0 | 0 |
W-0h | R/W-0h | R/W-0h | W-0h | R/W-0h | W-0h | W-0h | W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | 0 | W | 0h | Must write 0 |
6 | PLL RESET | R/W | 0h | Pulse this bit after powering up the device; see Table 9-1. 0 = Default 0 → 1 → 0 = The PLL RESET bit is pulsed. |
5 | LANE PDN 1 | R/W | 0h | This bit powers down unused SERDES
lanes DA0, DA3, DB0, and DB3 in certain LMFS settings (applicable
for LMFS = 4244, 2242, 2441, 4211, and 2221). Powering down unused
lanes puts the SERDES buffers in tri-state moe and saves
approximately 15-mA current on the IOVDD supply. This bit must be
used with LANE PDN 0 to take effect. 0 = Default 1 = DA0, DB0, DA3 and DB3 are powered down4 |
4 | 0 | W | 0h | Must write 0 |
3 | LANE PDN 0 | R/W | 0h | This bit powers down unused SERDES
lanes DA0, DA3, DB0, and DB3 in certain LMFS settings (applicable
for LMFS = 4244, 2242, 2441, 4211, and 2221). Powering down unused
lanes puts the SERDES buffers in tri-state moe and saves
approximately 15-mA current on the IOVDD supply.This bit must be
used with LANE PDN 1 to take effect. 0 = Dafult 1 = DA0, DB0, DA3 and DB3 are powered down4 |
2-0 | 0 | W | 0h | Must write 0 |