ZHCSEA4C May   2015  – December 2020 ADS54J40

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5  ADS54J40 Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 AC Characteristics
    7. 7.7 Digital Characteristics
    8. 7.8 Timing Requirements
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Inputs
      2. 8.3.2 DDC Block
        1. 8.3.2.1 Decimate-by-2 Filter
        2. 8.3.2.2 Decimate-by-4 Filter Using a Digital Mixer
        3. 8.3.2.3 Decimate-by-4 Filter with IQ Outputs
      3. 8.3.3 SYSREF Signal
        1. 8.3.3.1 SYSREF Not Present (Subclass 0, 2)
      4. 8.3.4 Overrange Indication
        1. 8.3.4.1 Fast OVR
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Mode
      2. 8.4.2 Device Configuration
        1. 8.4.2.1 Serial Interface
        2. 8.4.2.2 Serial Register Write: Analog Bank
        3. 8.4.2.3 Serial Register Readout: Analog Bank
        4. 8.4.2.4 JESD Bank SPI Page Selection
        5. 8.4.2.5 Serial Register Write: JESD Bank
          1. 8.4.2.5.1 Individual Channel Programming
        6. 8.4.2.6 Serial Register Readout: JESD Bank
      3. 8.4.3 JESD204B Interface
        1. 8.4.3.1 JESD204B Initial Lane Alignment (ILA)
        2. 8.4.3.2 JESD204B Test Patterns
        3. 8.4.3.3 JESD204B Frame
        4. 8.4.3.4 JESD204B Frame Assembly with Decimation
          1. 8.4.3.4.1 JESD Transmitter Interface
          2. 8.4.3.4.2 Eye Diagrams
    5. 8.5 Register Maps
      1. 8.5.1 Example Register Writes
      2. 8.5.2 Register Descriptions
        1. 8.5.2.1 General Registers
          1. 8.5.2.1.1 Register 0h (address = 0h)
          2. 8.5.2.1.2 Register 1h (address = 1h)
          3. 8.5.2.1.3 Register 2h (address = 2h)
          4. 8.5.2.1.4 Register 3h (address = 3h)
          5. 8.5.2.1.5 Register 4h (address = 4h)
          6. 8.5.2.1.6 Register 5h (address = 5h)
          7. 8.5.2.1.7 Register 11h (address = 11h)
        2. 8.5.2.2 Master Page (080h) Registers
          1. 8.5.2.2.1  Register 20h (address = 20h), Master Page (080h)
          2. 8.5.2.2.2  Register 21h (address = 21h), Master Page (080h)
          3. 8.5.2.2.3  Register 23h (address = 23h), Master Page (080h)
          4. 8.5.2.2.4  Register 24h (address = 24h), Master Page (080h)
          5. 8.5.2.2.5  Register 26h (address = 26h), Master Page (080h)
          6. 8.5.2.2.6  Register 4Fh (address = 4Fh), Master Page (080h)
          7. 8.5.2.2.7  Register 53h (address = 53h), Master Page (080h)
          8. 8.5.2.2.8  Register 54h (address = 54h), Master Page (080h)
          9. 8.5.2.2.9  Register 55h (address = 55h), Master Page (080h)
          10. 8.5.2.2.10 Register 59h (address = 59h), Master Page (080h)
        3. 8.5.2.3 ADC Page (0Fh) Register
          1. 8.5.2.3.1 Register 5F (addresses = 5F), ADC Page (0Fh)
        4. 8.5.2.4 Main Digital Page (6800h) Registers
          1. 8.5.2.4.1  Register 0h (address = 0h), Main Digital Page (6800h)
          2. 8.5.2.4.2  Register 40h (address = 40h), Main Digital Page (6800h)
          3. 8.5.2.4.3  Register 41h (address = 41h), Main Digital Page (6800h)
          4. 8.5.2.4.4  Register 42h (address = 42h), Main Digital Page (6800h)
          5. 8.5.2.4.5  Register 43h (address = 43h), Main Digital Page (6800h)
          6. 8.5.2.4.6  Register 44h (address = 44h), Main Digital Page (6800h)
          7. 8.5.2.4.7  Register 4Bh (address = 4Bh), Main Digital Page (6800h)
          8. 8.5.2.4.8  Register 4Dh (address = 4Dh), Main Digital Page (6800h)
          9. 8.5.2.4.9  Register 4Eh (address = 4Eh), Main Digital Page (6800h)
          10. 8.5.2.4.10 Register 52h (address = 52h), Main Digital Page (6800h)
          11. 8.5.2.4.11 Register 68h (address = 68h), Main Digital Page (6800h)
          12. 8.5.2.4.12 Register 72h (address = 72h), Main Digital Page (6800h)
          13. 8.5.2.4.13 Register ABh (address = ABh), Main Digital Page (6800h)
          14. 8.5.2.4.14 Register ADh (address = ADh), Main Digital Page (6800h)
          15. 8.5.2.4.15 Register F7h (address = F7h), Main Digital Page (6800h)
        5. 8.5.2.5 JESD Digital Page (6900h) Registers
          1. 8.5.2.5.1  Register 0h (address = 0h), JESD Digital Page (6900h)
          2. 8.5.2.5.2  Register 1h (address = 1h), JESD Digital Page (6900h)
          3. 8.5.2.5.3  Register 2h (address = 2h), JESD Digital Page (6900h)
          4. 8.5.2.5.4  Register 3h (address = 3h), JESD Digital Page (6900h)
          5. 8.5.2.5.5  Register 5h (address = 5h), JESD Digital Page (6900h)
          6. 8.5.2.5.6  Register 6h (address = 6h), JESD Digital Page (6900h)
          7. 8.5.2.5.7  Register 7h (address = 7h), JESD Digital Page (6900h)
          8. 8.5.2.5.8  Register 16h (address = 16h), JESD Digital Page (6900h)
          9. 8.5.2.5.9  Register 31h (address = 31h), JESD Digital Page (6900h)
          10. 8.5.2.5.10 Register 32h (address = 32h), JESD Digital Page (6900h)
        6. 8.5.2.6 JESD Analog Page (6A00h) Registers
          1. 8.5.2.6.1 Register 12h (address = 12h), JESD Analog Page (6A00h)
          2. 8.5.2.6.2 Registers 13h-15h (addresses = 13h-5h), JESD Analog Page (6A00h)
          3. 8.5.2.6.3 Register 16h (address = 16h), JESD Analog Page (6A00h)
          4. 8.5.2.6.4 Register 17h (address = 17h), JESD Analog Page (6A00h)
          5. 8.5.2.6.5 Register 1Ah (address = 1Ah), JESD Analog Page (6A00h)
          6. 8.5.2.6.6 Register 1Bh (address = 1Bh), JESD Analog Page (6A00h)
        7. 8.5.2.7 Offset Read Page (JESD BANK PAGE SEL = 6100h, JESD BANK PAGE SEL1 = 0000h) Registers
          1. 8.5.2.7.1 Register 068h (address = 068h), Offset Read Page
          2. 8.5.2.7.2 Register 069h (address = 069h), Offset Read Page
          3. 8.5.2.7.3 Registers 074h, 076h, 078h, 7Ah (address = 074h, 076h, 078h, 7Ah), Offset Read Page
          4. 8.5.2.7.4 Registers 075h, 077h, 079h, 7Bh (address = 075h, 077h, 079h, 7Bh), Offset Read Page
        8. 8.5.2.8 Offset Load Page (JESD BANK PAGE SEL= 6100h, JESD BANK PAGE SEL1 = 0500h) Registers
          1. 8.5.2.8.1 Registers 00h, 04h, 08h, 0Ch (address = 00h, 04h, 08h, 0Ch), Offset Load Page
          2. 8.5.2.8.2 Registers 01h, 05h, 09h, 0Dh (address = 01h, 05h, 09h, 0Dh), Offset Load Page
          3. 8.5.2.8.3 Registers 78h (address = 78h), Offset Load Page
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
      1. 9.1.1 Start-Up Sequence
      2. 9.1.2 Hardware Reset
      3. 9.1.3 SNR and Clock Jitter
      4. 9.1.4 DC Offset Correction Block in the ADS54J40
        1. 9.1.4.1 Freezing the DC Offset Correction Block
        2. 9.1.4.2 Effect of Temperature
      5. 9.1.5 Idle Channel Histogram
      6. 9.1.6 Interleaving (IL) Mismatch Compensation
        1. 9.1.6.1 Introduction
        2. 9.1.6.2 Features
        3. 9.1.6.3 Temperature variation
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Transformer-Coupled Circuits
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Sequencing and Initialization
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表

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订购信息

8.5 Register Maps

Figure 8-27 shows a conceptual diagram of the serial registers.

GUID-413FBF26-8257-41F4-9E47-796B712459D6-low.gif Figure 8-27 Serial Interface Registers

The ADS54J40 contains two main SPI banks. The analog SPI bank gives access to the ADC analog blocks and the digital SPI bank controls the interleaving engine and anything related to the JESD204B serial interface. The analog SPI bank is divided into two pages (master and ADC) and the digital SPI bank is divided into three pages (main digital, JESD digital, and JESD analog). Table 8-15 lists a register map for the ADS54J40.

Table 8-15 Register Map
REGISTER ADDRESS REGISTER DATA(1)
A[11:0] (Hex) 7 6 5 4 3 2 1 0
GENERAL REGISTERS
0 RESET 0 0 0 0 0 0 RESET
1 JESD BANK PAGE SEL1[7:0]
2 JESD BANK PAGE SEL1[15:8]
3 JESD BANK PAGE SEL[7:0]
4 JESD BANK PAGE SEL[15:8]
5 0 0 0 0 0 0 0 DISABLE BROADCAST
11 ANALOG BANK PAGE SEL
MASTER PAGE (80h)
20 PDN ADC CHA PDN ADC CHB
21 PDN BUFFER CHB PDN BUFFER CHA 0 0 0 0
23 PDN ADC CHA PDN ADC CHB
24 PDN BUFFER CHB PDN BUFFER CHA 0 0 0 0
26 GLOBAL PDN OVERRIDE PDN PIN PDN MASK SEL 0 0 0 0 0
4F 0 0 0 0 0 0 0 EN INPUT DC COUPLING
53 0

0

 0 0 0 0 EN SYSREF DC COUPLING SET SYSREF
54 ENABLE MANUAL SYSREF 0 MASK SYSREF MASK SYSREF 0 0 0 0
55 0 0 0 PDN MASK 0 0 0 0
59 FOVR CHB 0 ALWAYS WRITE 1 0 0 0 0 0
ADC PAGE (0Fh)
5F FOVR THRESHOLD PROG
MAIN DIGITAL PAGE (6800h)

0

 0 0 0 0 0 0 0 PULSE RESET
40 IL ENGINE MODE
41 0 0 DECFIL MODE[3] DECFIL EN 0 DECFIL MODE[2:0]
42 0 0 0 0 0 NYQUIST ZONE
43 0 0 0 0 0 0 0 FORMAT SEL
44 0 DIGITAL GAIN
4B 0 0 FORMAT EN 0 0 CTRL IL ENGINE MODE 0 0
4D 0 0 0 0 DEC MODE EN 0 0 CTRL FREEZE IL ENGINE
4E CTRL NYQUIST 0 IMPROVE IL PERF 0 0 0 0 0
52 BUS_
REORDER EN1		 0 0 0 0 0 0 DIG GAIN EN
68 0 FREEZE IL ENGINE 0
72 0 0 0 0 BUS_
REORDER EN2		 0 0 0
AB 0 0 0 0 0 0 0 LSB SEL EN
AD 0 0 0 0 0 0 LSB SELECT
F7 0 0 0 0 0 0 0 DIG RESET
JESD DIGITAL PAGE (6900h)

0

 CTRL K 0 0 TESTMODE EN FLIP ADC DATA LANE ALIGN FRAME ALIGN TX LINK DIS
1 SYNC REG SYNC REG EN JESD FILTER JESD MODE
2 LINK LAYER TESTMODE LINK LAYER RPAT LMFC MASK RESET 0 0 0
3 FORCE LMFC COUNT LMFC COUNT INIT RELEASE ILANE SEQ
5 SCRAMBLE EN 0 0 0 0 0 0 0
6 0 0 0 FRAMES PER MULTI FRAME (K)
7 0 0 0 0 SUBCLASS 0 0 0
16 ALWAYS WRITE 1 0 0 LANE SHARE 0 0 0 0
31 DA_BUS_REORDER[7:0]
32 DB_BUS_REORDER[7:0]
JESD ANALOG PAGE (JESD BANK PAGE SEL = 6A00h)
12 SEL EMP LANE 1 ALWAYS WRITE 1 0
13 SEL EMP LANE 0 0 0
14 SEL EMP LANE 2 0 0
15 SEL EMP LANE 3 0 0
16 0 0 0 0 0 0 JESD PLL MODE
17 0 PLL RESET LANE PDN 1 0 LANE PDN 0 0 0 0
1A 0 0 0 0 0 0 FOVR CHA 0
1B JESD SWING 0 FOVR CHA EN 0 0 0
OFFSET READ PAGE (JESD BANK PAGE SEL = 6100h, JESD BANK PAGE SEL1 = 0000h)
68 FREEZE CORR DC OFFSET CORR BW DC OFFSET CORR BW DC OFFSET CORR BW DC OFFSET CORR BW BYPASS CORR ALWAYS WRITE 1 0
69 0 0 0 0 0 0 0 EXT CORR EN
74 ADC0_CORR_INT_EST[7:0]
75 0 0 0 0 0 ADC0_CORR_INT_EST[10:8]
76 ADC1_CORR_INT_EST[7:0]
77 0 0 0 0 0 ADC1_CORR_INT_EST[10:8]
78 ADC2_CORR_INT_EST[7:0]
79 0 0 0 0 0 ADC2_CORR_INT_EST[10:8]
7A ADC3_CORR_INT_EST[7:0]
7B 0 0 0 0 0 ADC3_CORR_INT_EST[10:8]
OFFSET LOAD PAGE (JESD BANK PAGE SEL = 6100h, JESD BANK PAGE SEL1 = 0500h)
00 ADC0_LOAD_INT_EST[7:0]
01 0 0 0 0 0 ADC0_CORR_INT_EST[10:8]
04 ADC1_LOAD_INT_EST[7:0]
05 0 0 0 0 0 ADC1_CORR_INT_EST[10:8]
08 ADC2_LOAD_INT_EST[7:0]
09 0 0 0 0 0 ADC2_CORR_INT_EST[10:8]
0C ADC3_LOAD_INT_EST[7:0]
0D 0 0 0 0 0 ADC3_CORR_INT_EST[10:8]
78h 0 0 0 0 0 IL ENGINE FREEZE SECONDARY CONTROL
(1) X = Don't care